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56F800 Series Introduction 

Purpose: 

• The intent of this module is to introduce the devices within the 56F800 

Series and understand the features associated with each peripheral. 

Objectives: 

• Identify the general benefits of the 56F800 Series. 

• Understand the available peripheral set for each device within the series. 

• Understand features of the peripheral set. 

Content: 

• 32 pages 

• 7 questions 

Learning Time: 

• 70 minutes 

The intent of this module is to introduce the devices within the 56F800 

Series and understand the features associated with each peripheral. Upon 

completion of this module, you will be able to identify the devices within the 

56F800 Series and understand the features associated with each peripheral.

Why 56F800? 

• MCU functionality and DSP performance 

resulting from a hybrid architecture 

• 30 & 40 MIPS FLASH performance 

• Reduction in system costs due to highly 

integrated features 

• Aggressive prices 

• Proven success - hundreds of applications in 

production today 

• New SW tools strategy supports low-cost 

development 

• Targets motor control for industrial, appliance, 

medical, and home/office environments 

• Continual investment into family 

The 56F800 series provides MCU functionality and DSP performance with its 

56800 Core hybrid architecture. This series integrates 40 MIPs FLASH 

performance and a host of other integrated features that reduce the overall 

system cost. The peripheral set is targeting motor control applications but 

has also been successful as a general purpose controller. Its feature set and 

aggressive pricing has met the market needs as proven by the hundreds of 

applications in production today. This series is just another example of our 

dedication to continual investment in its Hybrid Controller portfolio.

56F800 Features 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 

Module A,B,C,D 

Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

56F801 

56F802 

56F803 

56F805 

56F807 

32 – 160 pins 

Here, you can see the overall features of the 56F80x family of parts. You 

can also see the peripherals associated with each specific part. Roll your 

mouse pointer over each feature for more information; then, select the 

specific processor derivative to view available peripheral blocks for that 

processor.


Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SPI 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

Data RAM 

Data FLASH 

6-output 

PWM A 

Quad Timer 

Module C,D 

56F801 

56F802 

56F803 

56F805 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

2x4 input 

ADC 

Module A 

56F807 

48 pin LQFP 

Now, let’s discuss the features of the other 56F800 products. The 56F801 comes in a 48-pin 

LQFP configuration and is available in two maximum speeds: 80MHz/40MIPs and 

60MHz/30MIPs. 

The 56F801 has a peripheral set that, in addition to being optimal for motion and power 

control applications, is also very well-suited to address the needs and demands of the 

general-purpose market.


Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SPI 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

1x2 input 

1x3 input 

ADC 

Data RAM 

Data FLASH 

6-output 

PWM A 

Quad Timer 

Module C,D 

56F801 

56F802 

56F803 

56F805 

56F807 

32 pin LQFP 

Now, let’s look at the features of the 56F802 and its peripherals. The 56F802 

has the lowest pin count in the 56F80x family. It too is available in two 

maximum speeds: 80MHz/40MIPs and 60MHz/30MIPs. It further extends 

the 56F800 family down to better support low cost applications.


Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SPI 

MSCAN 

GPIOs 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

40 MIPS 

80 MHz 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

Quad Timer 

Module A,C,D 

Quadrature 

Decoder 0 

56F801 

56F802 

56F803 

56F805 

56F807 

System Clock 

Generator 

(OSC & PLL) 

2x4 input 

ADC 

Module A 

100 pin LQFP 

Here, we can see the features of the 56F803 and its peripherals. Compared to the 56F801 

and 56F802, the 56F803 contains some additional features. These include 32K words of 

Program FLASH, replacing the 8K contained in the 56F801. This offers customers flexibility 

for custom solutions. More additional features include 512 words Program RAM vs. 1K, 4K 

Data FLASH vs. 2K, and 2K Data RAM vs. 1K. The 56F803 includes additional fault input (3 

vs. 2), a Quadrature Decoder, and a shared Quad Timer. It has current sense inputs, and 

the maximum number of GPIO pins is increased from 11 to 16. Finally, the 56F803 has a 

CAN module that is 2.0 A/B compliant, an external bus that enables system memory 

expansion, and a 100-pin LQFP configuration.


Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

40 MIPS 

80 MHz 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

56F801 

56F802 

56F803 

56F805 

56F807 

System Clock 

Generator 

(OSC & PLL) 

2x4 input 

ADC 

Module A 

Quadrature 

Decoder 1 

144 pin LQFP 

Here, we can see the features of the 56F805 and its peripherals. Compared 

to the 56F803, the 56F805 provides many additional features, such as an 

SCI port, a second 6 channel PWM, a fault input (from 3 to 4), and a second 

Quadrature Decoder (from 1 to 2). The 56F805 also contains additional 

dedicated and shared Quad Timers, and GPIO pins (14 dedicated and 2 

shared). Note that the maximum GPIO increased from 16 to 32. Finally, the 

56F805 has a 144-pin LQFP configuration.


Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

40 MIPS 

80 MHz 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

56F801 

56F802 

56F803 

56F805 

56F807 

System Clock 

Generator 

(OSC & PLL) 

2x4 input 

ADC 

Module A 

2x4 input 

ADC 

Module B 

Quadrature 

Decoder 1 

160 pin LQFP & MBGA 

Here, we can see the features of the 56F807 and its peripherals. Compared to the 

56F805, the 56F807 provides additional peripheral features, such as Program FLASH, 

which increased from 32K to 60K; Program RAM, which increased from 0.5K to 2K; Data 

FLASH, which increased from 4K to 8K; and Data RAM, which increased from 2K to 4K. 

More additional features include four 4-input ADCs, instead of two 4-input ADCs

56F800 Series 

• 56F801 

• 56F802 

• 56F803 

• 56F805 

• 56F807 

Now that we have learned about the specific processor derivatives in the 

56F800 Series, and their peripherals, let’s take a moment to review what we 

have learned. Click “Comparison” to view a table that contains a side-by-side 

comparison of the processors available within the 56F800 Series.

56F800 Series 

Comparison 

56F801 56F802 56F803 56F805 56F807 

Performance 

80MHz/40MIPS 80MHz/40MIPS 

80MHz/40MIPS 



Temp. Range (-40, +85)°C (-40, +85)°C (-40, +85)°C (-40, +85)°C (-40, +85)°C 

Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 

On-Chip Flash 12K x 16 12K x 16 38K x 16 38K x 16 70K x 16 

Program Flash 8K x 16 8K x 16 32K x 16 32K x 16 60K x 16 

D ata Flash 2K x 16 2K x 16 4K x 16 4K x 16 8K x 16 

B oot Flash 2K x 16 2K x 16 2K x 16 2K x 16 2K x 16 

On-Chip RAM 2K x 16 2K x 16 2.5K x 16 2.5K x 16 6K x 16 

Program R AM 1K x 16 1K x 16 512 x 16 512 x 16 2K x 16 

D ata R AM 1K x 16 1K x 16 2K x 16 2K x 16 4K x 16 

Ext. M e mory Inte rface - - Yes Yes Yes 

PLL Yes Yes Yes Yes Yes 

O n-Chip Relaxation O SC ye s ye s - - - 

Watchdog Timer Yes Yes Yes Yes Yes 

Inte rrupt C ontrolle r Yes Yes Yes Yes Yes 

16-bit Timers 8 8 8 16 16 

Quadrature Decoder - - 1 x 4 ch 2 x 4 ch 2 x 4 ch 

PWM 1 x 6ch 1 x 6ch 1 x 6ch 2x 6ch 2 x 6ch 

PWM Fault Input 1 1 3 4 + 4 4 + 4 

PWM Current Sense Pins 0 0 3 3+ 3 3 + 3 

12-bit ADC 2 x 4ch 5ch 2 x 4ch 2 x 4ch 4 x 4 ch 

CAN 2.0 A/B - - 1 1 1 

SCI (UART) 1 1 1 2 2 

SPI (Synchronous) 1 - 1 1 1 

G PIO (D e d./Shrd/T ot) 0 / 1 1 / 1 1 0 / 4 / 4 0 / 1 6 / 1 6 1 4 / 1 8 / 3 2 1 4 / 1 8 / 3 2 

JTAG/OnCE Yes Yes Yes Yes Yes 

Packages 48LQFP 32LQFP 100LQFP 144LQFP 

160LQFP 

160MBGA 

Av ailability Now Now Now Now Now 

This is a reference page for the previous page

Question 

Which of the following devices has the lowest pin count in the 

56F80x family? Select the correct answer and then click Done. 

a) 56F803 

b) 56F802 

c) 56F805 

d) 56F807 

Consider the following question about the 56F800 Series. 

56F802 has the lowest pin count in the 56F80x family. It comes in a 32-pin 

LQFP configuration.

Question 

Which of the following devices includes two 6-output PWM Modules? 

Select the correct answer and then click Done. 

a) 56F801 

b) 56F803 

c) 56F805 

Here’s an opportunity to see if you can remember what you learned about 

the features of the 56F800 Series. 

The 56F805 includes two 6-output PWM Modules.

Memory 

Competitive Features: 

•FLASH with small page 

size: 512 words 

•EEPROM emulation 

supported by small Data 

FLASH page size 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

Let’s take a moment to discuss the memory in the 56F800 devices. Having separate and multiple 

buses available allows for concurrent accesses to both program and data memory. This parallelism 

enhances performance for repetitive fetch and process arithmetic loops. External program and data 

memory can have different wait states. Programmable wait states support lower cost external memory 

and are application dependent. 

Available FLASH memory reduces system cost by providing reprogrammable, non-volatile memory 

without the cost associated with ROM parts. Page erase versus the competitors’ bulk erase offers the 

most flexible FLASH memory configuration on the market. Boot FLASH technology allows for in-field 

application software update via JTAG/OnCE or serial ports. Boot FLASH also provides failsafe field 

upgrades. 

The 56F80x devices contain FLASH with small page sizes 512 words. The small Data Flash page size 

makes it possible to emulate EEPROM thereby reducing the overall system cost. This feature sets all 

FLASH based Hybrid Controller devices apart from the competition.

Features 

• On chip Harvard Architecture 

• Separate program and data buses 

• Permits up to three simultaneous accesses to program and data memory 

• On-chip and Off-chip memory 

• Up to 64K words Data memory 

• Up to 64K words Program memory 

• FLASH memory programmable via JTAG/OnCE interface or user-defined 

programming 

• Programmable wait states for low cost system memory solutions 


PWM 


• Complementary channel 

operation: 

• Deadtime insertion 

• ADC synchronization 

• Programmable fault inputs 

• Double-buffered PWM 

register 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

Now, let’s discuss the features of the Pulse Width Modulators (PWMs). PWMs generate 

timing waveforms with controlled duty cycles. An example application would be to use the 

PWMs with the Quadrature Decoder module and ADC modules to control the speed and 

direction of an electric motor. 

As many as two 6-channel PWM modules are available, depending on the 568xx device 

selected. PWM outputs can be configured to operate independently or as three 

complementary pairs. A typical three-phase power stage would use the PWMs in the 

complementary pair mode. Each complementary pair would provide the gating signal to the 

top and bottom transistors in one phase of the power stage. 

Here, you can see some of the features that the PWM devices offer. These features set 

these devices apart from the competition. 

You can set the PWM outputs to include automatic deadtime insertion. Deadtime insertion 

ensures a delay after the deactivation of one of the external power transistors and the 

activation of the complementary transistor. Deadtime accounts for the required turn off delay 

needed to avoid what are called ‘shoot through’ currents in a power stage. Unlike many 

competing devices, the 56F800 family PWMs offer both popular types of pulse alignment: 

edge-aligned and center-aligned. Customers can choose the alignment that best suits their 

application. 

PWMs have high 15-bit resolution, various reloading options, and individually programmed 

outputs. High current drive capability on the outputs simplify interfacing requirements, and 

key parameter registers are protected against inadvertent changes by a “write once” 

mechanism. Four additional programmable fault inputs monitor external events for error 

conditions and provide direct output disabling or software interrupt capabilities. 

The PWM unit incorporates enough flexibility to be configured for several different motor 

drive topologies.

Features 

• Three complementary signal pairs or six independent signals 

• Complementary channel operation 

• Separate top and bottom pulse width correction via current sensing or software 

• Separate top and bottom polarity control 

• Edge-aligned or center-aligned signals 

• 15-bits of resolution 

• Half-cycle reload capability 

• Programmable integral reload rates (half to 16) 

• Individually software-controlled PWM outputs 

• 16 mA current sink capability 

10 mA current source 

• Output polarity control 

• Write protected registers 

• Protection for key parameters 


PWM Distortion Correction 

Voltage with Correction Disabled 

Voltage with Correction Enabled 

Motor Voltage 

Current with Correction Disabled 

Quieter operation 

Smoother operation 

Less motor harmonic losses 

Current with Correction Enabled 

Motor Current 

Actual waveforms taken on a 1/2 horsepower motor 

These four figures describe actual voltage and current measurements made 

on a half horsepower electric motor. 

The two plots on the left show the motor voltage and current waveforms 

before our patented distortion correction is applied. The distortion consists of 

a periodic step in the waveform rise times. This distortion can lead to torque 

ripple, motor losses, audible noise emissions, and other problems in the 

motor. The distortion is caused by a combination of loading effects on the 

power drive stage and the imperfect nature of deadtime insertion. Our 

patented distortion correction effectively counter modulates the waveform, 

canceling out the effects of the distortion. 

The two waveforms on the right show the motor voltage and current after the 

distortion correction is applied. As you can see, the motor current and 

voltage are now close to ideal sine waves. The result of applying the PWM 

distortion correction feature is that the motor will experience reduced 

harmonic losses, reduced internal heating, and reduced torque 

perturbations. In effect, the motor will be using energy more efficiently by 

reducing the energy lost in the distortion. 

You can learn more about this distortion correction scheme in application 

note AN1728, available at our Web site.

Question 

Is the following statement true or false? “Deadtime insertion ensures a 

delay after the activation of one of the external power transistors 

and the deactivation of the complementary transistor. ” 

True 

False 

Consider this question about the PWM peripheral. 

In fact, the deadtime insertion feature of the PWM ensures a delay after the 

deactivation of one of the external power transistors before the activation of 

the complementary transistor.

Quad Timers 

Competitive Feature: 

• The 16-bit counters in the 

module can be daisy-chained 

to yield counter lengths up to 

2 64 . 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

Now, let’s discuss Quad Timers. A variety of count configurations are available with Quad Timer 

implementation. Counters support Count Once operation, a Count Repeatedly operation, and a 

programmable “Count Modulo”. Other operation modes of Quad Timers are: fixed frequency PWM, 

variable frequency PWM, Stop, Count, Edge Count, Gated Count, Quadrature Count, Signed Count, 

One-Shot, Cascade Count, and Pulse Output Mode. 

Timers are capable of counting internal and external events. You can count an internal clock source 

while an input signal is asserted, thus timing the width of the signal. You can also count the rising, 

falling, or both edges of a selected in/out pin. 

The value loaded into the timer after it reaches its terminal count is programmable. Flexible timer 

configuration allows for advanced application software development. The C and D Quad Timers have 

dedicated pins. The A and B Quad Timers share pins with Quadrature Decoders 

In the 56F800 devices, the 16-bit counters within the module can be daisy-chained to yield counter 

lengths up to 2 64 . This feature sets these devices apart from the competition.

Features 

• Four 16-bit general purpose up/down timers per 

module. 

• Individually programmable as input capture or 

output compare 

• Programmable count sources including internal and 

external clocks 

• Timer pins configurable as general purpose I/O 

when not being used by timer. 

• Input pins are shareable within a timer module. 


Quadrature Decoder 


• Watchdog timer 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

A quadrature decoder circuit decodes the quadrature encoder signals, 

normally two 90 degrees out-of-phase pulses, into count and direction 

information. The maximum counting resolution is 4x input signal. The 

quadrature decoder samples both incoming pulses. Based on the previous 

pulse information of the two signals and the present state, it outputs a count 

signal and a direction signal to internal position counts. 

The Quadrature Decoder uses phase difference in input signals to compute 

the direction of the shaft motion. Transition on the phases can be integrated 

to compute shaft position or differentiated to compute shaft speed. The A 

and B Quad Timers share pins with the Quadrature Decoders. 

The Quadrature Decoder in the 56F800 devices has a competitive feature 

that sets it apart from the competition. That is, the 16-bit watchdog timer can 

be enabled to detect a non-moving shaft. An optional interrupt can be 

generated when the watchdog timer times out, allowing the software to 

handle the non-moving shaft.

M 

General Features 

Channel A 

Channel B 

Index 

Quadrature 

Decoder 

Module 

Home limit switch 

Features: 

• Two encoder inputs per decoder 

• Index input 

• resets the current integration value 

• begins integrating a new revolution 

value 

• Configurable glitch filter for inputs 

• Optionally may operate as singlephase 

pulse accumulator 

• Captures all four transitions on two-phased 

inputs 

• extracts actual shaft position and direction 

• 32-bit position counter - initialized by 

software or external events 

• 16-bit position difference register 

• Pre-loadable 16-bit revolution register 

Based on inputs from motion control customers around the world, the 

56F800 family offers an unsurpassed level of motion control peripheral, 

integration, and flexibility. The features provided by the Quadrature Decoder 

Module reflect the attention to the needs of motion control customers. 

Some of the encoder interface features include two encoder inputs per 

decoder, index input for integration control, programmable digital glitch filters 

on all inputs, 32-bit bi-directional position tracking, and a 16-bit revolution 

counter based on the index signal. The encoder interface also offers velocity 

measurement via a 16-bit delta count. Also included are home and index 

signals that provide interrupts and optional position initialization.

Question 

In the Quadrature Decoder, which of the following events does the 16- 

bit watchdog timer detect? Select the correct answer and then click 

Done. 

a) Optional interrupts 

b) Count modulos 

c) Moving shafts 

d) Non-moving shafts 

Consider the following question about the Quadrature Decoder peripheral. 

The Quadrature Decoder uses phase difference in the input signals to 

compute the direction of the shaft motion. Transition on the phases are 

integrated to compute shaft position or differentiated to compute shaft 

speed. The 16-bit watchdog timer can be enabled to detect non-moving 

shafts.

ADC 


• Two ADCs per module 

• Single conversion in 1.2 µsec 

• 8 conversions in 5.3 µsec 

• Interrupt generating capabilities 

• End-of-Scan 

• Zero crossing 

• High/Low limit check 

• Two outputs formats available 

• Two’s complement 

• Unsigned 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

The next peripheral we’ll look at is the Analog to Digital Converter (ADC). 

The ADC includes 12-bit resolution and 9-bit accuracy. For motion control 

applications, the PWM can control the ADC to synchronize sampling with 

PWM reloads. 

The ADC can be configured to generate interrupts on a variety of events. 

This enables software control of the signal capture events. Availability of 

signed and unsigned output formats provide flexibility. Software can utilize 

the output format that best suits an application. 

It is important to note which ADC features set the 56F800 devices apart from 

the competition. Take a moment to review these features, which are listed 

here.

Features 

• 12-bit resolution 

• Up to Two ADC modules 

• 8 analog inputs per ADC module 

• 2 A/D converters per module 

• Sampling rate up to 1.66 million samples per second 

• Can be synchronized with Pulse Width Modulators (PWM) 

• Simultaneous or sequential sampling 

• Eight word result buffers 

• Sample correction via programmable offset 


ADC Interrupts Capabilities 

Programmable Upper Limit 

Digital Conversion Result 

Programmable Threshold 

Programmable Lower Limit 

Optional Interrupts 

• Each channel has its own upper, lower, and threshold 

comparators. 

• The ADC can perform limit checking and zero crossing detection 

with no CPU intervention. 

Each ADC channel includes unique registers that can generate an interrupt 

when the input crosses a threshold. Each channel has its own upper, lower, 

and threshold comparators. To use this feature, program the thresholds of 

interest, put the ADC in continuous convert mode, and then let the ADC 

“snoop” on the conversion results and interrupt the core when one of the 

thresholds is crossed. 

This feature is extremely useful for detecting “pre-fault” conditions in a motor 

control system. Software can use this feature to detect a condition that could 

quickly lead to a fault, and respond accordingly to avoid a hard fault 

condition. For example, suppose you program the ADC to watch the bus 

voltage via the upper limit and alert you when a “regen” situation pumps the 

voltage up dangerously close to a fault condition. When the appropriate 

voltage is reached, the software is interrupted and the deceleration of the 

motor, which is causing the rise in bus voltage, can be moderated. This 

avoids an overvoltage fault which abruptly trips the drive. 

Using the zero crossing feature, you can generate an interrupt on positive, 

negative, or both transitions through the zero crossing. Note that the level for 

the zero crossing threshold is programmable. An example application of this 

is a single-phase PF correction.

M 

Motor Control Design Using ADCs 

Trigger for both ADCs 

Perfect for 

Vector Control! 

ADC1 

ADC2 

i a 

i b 

B 

i b 

i c 

(implied) 

A 

B 

C 

i a 

A 

C 

Vector controlled applications require you to obtain a “snapshot” of the motor currents. If 

we view the motor as a floating “blob”, then we can deduce from Norton’s current law that 

the sum of currents flowing into phases A and B must equal the current flowing out on 

phase C. Therefore, only two measurements are required to capture the values of the 

current flowing in all three phases of the motor. 

An example vector diagram of these currents is shown at the right. The vectors can be 

added to obtain a composite vector representing the flux magnitude and angle at that 

particular time. The problem is that this vector is rotating, and it’s very important to have an 

accurate snapshot of the vector’s magnitude and angle at a particular time. 

As an analogy, consider using a camera to take a picture of a rotating object that’s moving 

very fast. If we use only one ADC to perform consecutive samples of the A and B currents, 

it’s like having two shutter exposures back to back on a camera. The acquired picture 

(vector) will be inaccurate due to movement between the two acquisitions. However, if we 

have two ADC inputs, which capture the currents simultaneously, the vector can be 

constructed accurately without “motion” artifacts. The same technique can be used to 

capture motor voltage vectors for “sensorless” control algorithms. 

The ADCs on the 56F80x family are specifically designed for accurate vector measurement 

by incorporating high resolution (12 bits), fast sampling (1.2 uS), and simultaneous 

sampling. Each ADC input is muxed to both ADCs, allowing for simultaneous sampling with 

any other input.

OCCS 


• On-chip Relaxation Oscillator 

• +/- 5% accuracy over 

temperature 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800/E 

Core 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

The next peripheral we’ll look at is the On-chip Clock Synthesis (OCCS) and 

Clock Generator. Multiple input clock configurations are supported by either 

the crystal clock or the clock source. The 801, 802 also have an internal 

Relaxation Oscillator that is trimmed at the factory to 8MHz and will vary plus 

or minus 5 percent over the entire temperature range of the part. This 

accuracy supports the requirements of the serial communication peripherals.

Features 

• Two different, dynamically selectable system clock sources available: 

• Crystal Oscillator - driven by external crystal 

• External clock source 

• On-Chip Relaxation Oscillator (on 56F801 and 56F802 devices) 

• Programmable 4-bit Prescaler 

• Divides Clock Source frequency by 1, 2, 4, or 8 

• Phase Locked Loop (PLL) - generates output frequencies of up to 80 MHz 

• Dynamically programmable PLL allows configurable power/speed options 

• Generates an interrupt if either loss of clock, or loss of lock, or both 

• PLL Postscaler 

• Divides PLL output frequency by 1, 2, 4 or 8 


OCCS Functions 

In some chips 

(56F801, 56F802) 

Relaxation 

Oscillator 

(8 MHz) 

Clock 

Input 

Crystal 

Oscillator 

2-10 MHz on 80x parts 

Prescaler 

(div by 1, 2, 4, 8) 

PLL 

Postscaler 

(div by 1, 2, 4, 8) 

80 MHz on 80x parts 

Clock Select 

Clock Source for 

Core & Peripherals 

Multiple input clock configurations are supported by either the crystal clock or 

the clock source. Note that the 56F801 and 56F802 also have an internal 

Relaxation Oscillator. 

The Phase Locked Loop (PLL) is used to multiply up the oscillator clock 

frequency to the frequency needed by the core and peripherals for operation. 

In the 800 family, the PLL can generate an 80 MHz system clock from a 2-10 

MHz external crystal. The PLL is dynamically programmable. This enables an 

application to set the appropriate execution speed for each mode of 

operation. 

The system clock is dynamically selectable from one of three sources. 

Competitor devices provide only a PLL as the system clock source. The system 

clock is one of the most flexible PLL implementations in the marketplace, 

according to our customers and distributor technical personnel.

CAN 


• Based on a Scalable Controller 

Area Network (MSCAN12) 

definition 

General Features: 

• Version 2.0A/B compliant 

• Double-buffered Rx 

• Triple-buffered Tx 

• Flexible, maskable identifier filter 

• Programmable wake-up 

functionality 

• Separate signaling and interrupt 

capabilities 

• Three low-power modes 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

CAN is version 2.0B compliant with standard and extended data frames, 0 to 

8 bytes data length, a programmable bit rate of up to 1 Mbps, and support 

for remote frames. It is double-buffered to receive storage schemes and 

triple-buffered to transmit storage schemes. CAN also has a flexible, 

maskable identifier filter, and a programmable wake-up functionality with an 

integrated low-pass filter. Another feature of CAN is that it has separate 

signaling and interrupt capabilities for all CAN Rx/Tx error states, as well as 

three low-power modes. 

CAN’s competitive feature is that it is based on a Scalable Controller Area 

Network definition, as implemented on the MC68HC12 Microcontroller 

family.

MSCAN Features and Benefits 

• Flexible message receiving filter scheme 

• Triple Buffered Transmit Storage Scheme with local prioritization 

• Double Buffered Receiving Queue with low latency interrupt 

• Three power saving modes - Sleep, Soft Reset, Power Down 

• Programmable wake up with an On Chip bus Noise Rejection circuit 

• Selectable Loop Back mode 

• Separate signaling and interrupt capabilities for all CAN receiver and 

transmitter error states 

• Transmit and receive error counters can be read 

The MSCAN includes several unique features that benefit customers using 

the 56F80x family devices with on-chip MSCAN. The MSCAN is a basic 

CAN controller. MSCAN implements the CAN specification version 2, parts A 

and B. 

Take a minute to review the features and benefits listed here.

Question 

Match each 56F800 peripheral with its feature by dragging the letters on 

the left to their corresponding items on the right. Click “Done” when you 

are finished. 

A 

ADC 

C 

It has a flexible, maskable identifier filter, and a 

programmable wake-up functionality with an 

integrated low-pass filter. 

B 

OCCS 

A 

Its interrupt generating capabilities include end-of-scan, 

zero crossing, and high/low limit check. 

C 

CAN 

B 

In the 56F801 and 56F802 devices, it has an on-chip 

relaxation oscillator, which provides +/- 5% accuracy over 

temperature. 

Done 

Reset 

Show 

Solution 

Here is a question for you on some of the 56F800 peripherals. 

The ADC peripheral has interrupt generating capabilities that include end-ofscan, 

zero crossing, and high/low limit check. The OCCS in the 56F801 and 

56F802 devices has an on-chip relaxation oscillator, which provides +/- 5% 

accuracy over temperature. The CAN has a flexible, maskable identifier filter, 

and a programmable wake-up functionality with an integrated low-pass filter.

SPI 


• Easy interface to 

MCUs, analog, and 

sensors 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

The Serial Peripheral Interface (SPI) is a four signal, independent, high-speed serial 

communications sub-system that enables all members of the 56F80x devices to 

communicate synchronously with peripheral devices such as Liquid Crystal Display 

(LCD) drivers, A/D sub-systems, and microprocessors. More sophisticated uses, such as 

inter-processor communication in a multiple-master system, are also easy to implement. 

The SPI can be configured as either a master or a slave device with high data rates. 

In master mode, a transfer is initiated when data is written to the SPI data register 

(SPDR). In slave mode, a transfer is initiated by the reception of a clock signal. Clock 

control logic allows a selection of clock polarity, and a choice of two fundamentally 

different clocking protocols to accommodate most available synchronous serial peripheral 

devices. In some cases, the phase and polarity are changed between transfers to allow a 

master device to communicate with peripheral slaves having different requirements. 

When the SPI is configured as a master, the software selects one of four different bit 

rates for the clock. Error detection logic is included to support inter-processor 

communications. A write-collision detector indicates when an attempt is made to write 

data to the serial shift register while a transfer is in progress. A multiple-master, modefault 

detector automatically disables SPI output drivers if more than one MCU 

simultaneously attempts to become bus master. 

In the 56F800 devices, the SPI provides an easy interface to MCUs, analog, and 

sensors. This feature sets these devices apart from the competition.

Features 

• Supports LCD drivers, A/D subsystems, and MCU systems 

• Supports inter-processor communications in a multiple master system 

• Supports demand-driven master or slave devices with high data rates 

• Full-duplex operation 

• Double-buffered operation with separate transmit and receive registers 

• Programmable length transmissions, 2 to 16 bits 

• Programmable transmit and receive shift order, MSB or LSB transmitted 

first 

• Four master mode frequencies (maximum = bus frequency / 2 ) 

• Maximum slave mode frequency = bus frequency 

• Serial clock with programmable polarity and phase 

• Two separately enabled interrupts: 

• Receiver Full 

• Transmitter Empty 

• Mode Fault and overflow error flag with interrupt capability 


External Data and Control Pins 

Master DSP 

Slave DSP 

SHIFT REGISTER 

MISO 

MISO 

MOSI 

MOSI 

SHIFT REGISTER 

Baud Rate 

Generator 

SCLK 

SS* 

SCLK 

SS* 

During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received 

(shifted in serially). The SPI serial clock (SCLK) line synchronizes shifting and sampling of 

the information on the two serial data lines. Each SPI device has four dedicated I/O pins. 

The SPI master in slave out pin (MISO) carries one of two unidirectional serial data signals. 

It’s an input to a master device and an output from a slave device. If a slave device is not 

selected, the MISO line of the slave device is placed in the high-impedance state. MISO 

can be programmed as a general purpose I/O (GPIO) when the SPI MISO function is not 

being used. 

The SPI master out slave in pin (MOSI) carries the second of the two unidirectional 

serial datasignals. It’s an output from a master device and an input to a slave device. The 

master device places data on the MOSI line a half-cycle before the clock edge that the 

slave device uses to latch onto the data. MOSI can be programmed as a GPIO when the 

SPI MOSI function is not being used. 

The SCLK, an input to a slave device, is generated by the master device and synchronizes 

data movement in and out of the device through the MOSI and MISO lines. Master and 

slave devices are capable of exchanging a byte of information during a sequence of eight 

clock cycles. Slave devices ignore the SCLK signal unless the Slave Select (SS) pin is 

active low. Both master and slave devices must operate with the same timing. The rate of 

the Master clock can be selected from four possibilities; the fastest is the IPBus Frequency/2. The 

Slave device can be clocked at any rate up to the IPBus Frequency. The SCLK pin can be 

programmed as a GPIO when the SPI SCLK function is not being used. 

The SPI SS line allows individual selection of a slave SPI device. Slave devices that are 

not selected do not interfere with SPI bus activities. On a master SPI device, the select line 

can be used to indicate a multiple master bus contention. The SPI SS input of a slave device 

must be externally asserted before a master device can exchange data with the slave device. 

SS must be low before data transactions and must stay low for the duration of the transmission.

SCI 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

The Serial Communication Interface (SCI) port enables Universal Asynchronous Receiver 

Transmitter (UART) type serial communications with other peripheral devices, Digital Signal 

Processors (DSPs), and MCUs that support the UART protocol. The SCI can be used to 

connect a CRT terminal or personal computer to the 56F800. Several widely distributed 

DSPs/MCUs can use their SCI subsystem to form a serial communication network. 

Let’s look at some of the SCI features. 

The SCI is a full-duplex UART type asynchronous system that uses a standard non-returnto-zero 

(NRZ) format (one start bit, 8 or 9 data bits, and a stop bit). An on-chip, baud-rate 

generator derives standard baud-rate frequencies from the DSP oscillator. Both the 

transmitter and the receiver are buffered. Therefore, back-to-back characters can be handled 

easily, even if the CPU is delayed in responding to the completion of an individual character. 

The SCI transmitter and receiver are functionally independent although they use the same 

baud rate generator and have the same data format and baud rate. A 13-bit modulus 

counter in the baud rate generator derives the baud rate for both the transmitter and the 

receiver. The module clock divisor is accomplished via the SCI baud rate register (SCIBR). 

Typically, the SCI uses two pins for transmitting and receiving. In single-wire operation, 

the receive data pin (RXD) is disconnected from the SCI. The SCI then uses the transmit 

data pin (TXD) for both receiving and transmitting. The CPU writes the data to be 

transmitted, processes the receive data, and monitors the SCI status.

Features 

• Full duplex operation provides simultaneous data transmit and receive. 

• Half duplex operation allows data transmit and receive via a single wire. 

• Separately enabled transmitter and receiver 

• 13-bit baud rate selection 

• Standard mark/space NRZ format 

• Programmable 8-bit or 9-bit data format 

• Separate receiver and transmitter CPU interrupts 

• Programmable polarity for transmitter and receiver 

• Two receiver wakeup methods: 

• Idle Line 

• Address Mark 

• Interrupt-driven operation with eight flags 

• Receiver framing error detection 

• Hardware parity checking 

• 1/16 bit-time noise detection 


Question 

How many SCIs does the DSP56F805 include? Select the correct 

answer and then click Done. 

a) none 

b) 1 

c) 2 

Here’s a question for you on the SCI peripheral. 

The DSP56F805 includes two interfaces: SCI0 and SCI1.

COP 

• Allows for detection of 

application software that may 

be operating incorrectly 

• Resets the part if not properly 

serviced 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

When active, the Computer Operating Properly (COP) requires periodic 

attention from the software or it will reset the part. The COP is essentially a 

down counter that continuously counts down to zero. When the software 

makes the appropriate sequence of writes to the COP registers, the counter 

is reloaded. If the counter ever reaches zero; the software is declared to be 

lost and not operating correctly. The part is automatically reset to get it out of 

whatever mode it is in.

Power Supervisor 

General Features: 

• Power Supervisor holds device in 

reset until there is enough voltage for 

on-chip logic to operate at the 

oscillator frequency. 

• Precludes any problems 

associated with false restart 

• Eliminates need for external power 

monitor 

Competitive features: 

• Two low voltage detect high-priority 

interrupts (Low voltage detect signals 

used to initiate a software controlled 

shutdown when the supply voltage 

drops below acceptable levels). 

• None of the competitors’ motor control 

devices include a Power Supervisor 

on-chip. 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

The integrated Power Supervisor reduces system cost by eliminating the 

need for an external power monitor. The Power Supervisor holds the device 

in reset until there is enough voltage for the on-chip logic to operate at the 

oscillator frequency. This precludes any problems associated with a false 

start. 

When using the integrated Power Supervisor, you must make sure that there 

is enough power (>2.2V) for the chip to operate properly before it is taken out 

of reset. The voltage level is continuously monitored. If voltage levels go 

below 2.7V or 2.2V, a low voltage interrupt is generated. Software is then 

responsible for saving any data prior to shutdown. The low-voltage interrupt 

can be enabled/disabled dynamically. 

Take a moment to review the features that set the 56F800’s Power 

Supervisor apart from the competition.

Interrupt Controller 


• Self-paced training 

available on Interrupt 

Handling 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

Boot 

RAM 

FLASH 

56800 

Core 

30-40 MIPS 

60-80 MHz 

2x4 input 

2x4 input 

ADC 

ADC 

Module A 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

The Interrupt Controller arbitrates IPBus peripheral interrupt requests and 

signals the DSP core when an interrupt of sufficient priority exists. It also 

provides the ISR address to service each interrupt and notifies the DSP core 

to restart the clocks out of WAIT and STOP mode. 

The Interrupt Controller supports 64 interrupt sources, two priority levels, two 

software trap interrupts, and low interrupt latency (14 to 24 system clock 

cycles). 

Self-paced training on Interrupt Handling is available. This feature 

differentiates the Interrupt Controller from the competition.

Voltage Management 


• Two internal regulators 

available 

• One for logic 

• One for analog 

Program 

FLASH 

JTAG/OnCE 

Voltage 

Regulators 

Interrupt 

Controller 

Power 

Supervisor 

COP 

SCI0 

SCI1 

SPI 

MSCAN 

GPIOs 

Relax. OSC 

System Clock 

Generator 

(OSC & PLL) 

Program 

RAM 

Boot 

FLASH 

56F800 

2x4 input 

ADC 

Module A 

2x4 input 

ADC 

Module B 

External 

Memory 

Interface 

Data RAM 

Data FLASH 

6-output 

PWM A 

6-output 

PWM B 

Quad Timer 


Quadrature 

Decoder 0 

Quadrature 

Decoder 1 

Next, let’s discuss the 56F800 peripherals related to voltage management, 

power management, and clock generation. 

In the 56F800 devices, I/O drivers are designed to interface at 3.3V, but they 

are 5V tolerant. External 3.3V supply voltage in the voltage manager is 

converted down to the 2.5V that is needed internally. The Voltage Regulator 

generates both the analog and digital voltages required by the chip from the 

external 3.3V supply. 

Competitive devices do not offer an integrated Voltage Regulator. The 

integrated solution results in reduced system cost, reduced opportunity for 

noise interference, and reduced system board size.

Question 

Match each 56F800 peripheral with its feature by dragging the letters on 

the left to their corresponding items on the right. Click “Done” when you 

are finished. 

A 

COP 

C 

Self-paced training on interrupt handling is available. 

B 

Power Supervisor 

B 

Low voltage detect signals are used to initiate a software 

controlled shutdown when the supply voltage drops below 

acceptable levels. 

C 

Interrupt Controller 

A 

It resets the part if its not properly serviced. 

D 

Voltage Management 

D 

It has two internal regulators available, one for 

logic and one for analog. 

Done 

Reset 

Show 

Solution 

Let’s review some of the 56F800 peripherals. 

When active, the COP requires periodic attention from the software or it will 

reset the part. The Power Supervisor has low voltage detect signals that are 

used to initiate a software controlled shutdown when the supply voltage 

drops below acceptable levels. The Interrupt Controller has self-paced 

training on interrupt handling. The Voltage Management has two internal 

regulators available, one for logic and one for analog.

Module Summary 

• 56F800 Series 

• Benefits 

• Devices 

• Peripherals 

• Peripheral features 

In this module, you learned about the devices within the 56F800 Series. 

Then, you learned about the general benefits of the 56F800 Series and the 

available peripheral set for each device within the series. Finally, you learned 

about the features of each peripheral set.

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