General Purpose Chip Select Machine - Freescale

General Purpose Chip Select Machine
Purpose:
• This module will discuss the standard chip select generation interface for SRAM, ROM
and basic devices only requiring a chip select.
Objectives:
• To provide you with an understanding of the twelve base and options register pairs to
which addresses are directed when using the general purpose chip select interface of the
memory controller.
Contents:
• This short module covers the memory block section, the basic timing and finishes with a
look at the registers.
Learning Time:
• There are 4 pages and 2 reference pages which will take approximately 8 minutes.
This module covers the standard chip select generation interface for SRAM, ROM and basic
devices only requiring a chip select.
To provide you with an understanding of the twelve base and options register pairs to which
addresses are directed when using the General Purpose chip select interface of the memory
controller.
This short module covers the memory block section, the basic timing and finishes with a look
at the registers.
There are 4 pages and 2 reference pages which will take approximately 8 minutes.

Memory block selection
Address
BR0
OR0
BRp
ORp
BRq
ORq
BRn
ORn
GPCM
CS-boot
CS-p
CS-q
CS-n
Memory
Boot ROM
Memory p
Memory q
Peripheral n
There are twelve base and options register pairs to which addresses are directed. The base
register defines the start address of a bank and the machine that will control it. The options
register defines the block size, and they both define the access attributes. When a bus cycle
is required, the address is compared to all the register pairs and if it lies between the base
pointer and length defined in the options register, and the base register is valid, the machine
selected will control the transfer.
When the GPCM is selected, the chip select and write enable or output enable signals are
asserted according to the timing specification, controlling the transfer. If there is more than
one bank of memory controlled by the GPCM, then the chip select relating to the base and
options register pair is asserted, defining which of the blocks is accessed.
One important feature is that although most of the base registers are invalid after reset, BR0
is valid, and defaults to a four gigabyte space. After reset, chip select zero can be used to
access the boot ROM. The boot code can be used to modify the range and control of chip
select zero if required, and initialize the rest of the memory controller to suit the system.

Basic Timing
Clock
Address
PSDVAL
CS
OE
Data
This diagram shows the relationship between the input clock and the timing controls. The
address is asserted on the rising edge of the clock and maintained for two clock periods.
The related chip select is asserted during the first half clock cycle. Partial data valid and
output enable asserted after one clock cycle, at the same time as data is driven onto the
bus. The data and control signals are negated after one clock cycle. The timing can be
extended by the use of wait states and relaxed timing, controlled by the options register.

Registers
0 31
BR
Base Register - one for each of 12 memory banks -
Defines the base address and attributes for each memory bank used.
0 31
OR
Options Register - one for each of 12 memory banks and associated with the related BR -
Defines the memory bank size and access attributes.
This and the next page identifies the registers required for use with the GPCM. The base
register determines the start address of the bank and the machine to be used. The
associated option register determines the size of the bank and some of the access
attributes.
If an address generated lies within the boundaries of these two registers and the valid bit is
set in the base register, then the controller defined in the base register will control the
transfer. To view the registers, click on the one of interest. That completes the general
purpose chip select machine section.