Integration of SiCN as a Low k Etch Stop and Cu Passivation in a ...

Integration of SiCN as a Low k Etch Stop and Cu Passivation in a High Performance
Cu/Low k Interconnect
Jeremy Martin, a) Stan Filipiak, b) Tab Stephens, b) Fred Huang, b) Massud Aminpur, a) Judith Mueller b)
Ertugrul Demircan, b) Larry Zhao, a) Jim Werking, a) Cindy Goldberg, b) Steve Park, a) Terry Sparks, b)
Christine Esber, a)
a) Advanced Micro Devices, AMD/Motorola Alliance, 3501 Ed Bluestein Blvd., Austin, TX 78721
b) Motorola, Dan Noble Center, 3501 Ed Bluestein Blvd., Austin, TX 78721
Abstract
This paper describes the integration of a silicon
carbon nitride (SiCN) copper passivation and etch stop layer
into a Cu low k dielectric interconnect technology. The incorporation
of SiCN improves interconnect performance by
virtue of its lower dielectric constant as compared to silicon
nitride, and through changes to the process integration made
possible by the improved etch selectivity and good copper
interface properties.
Introduction
The need to reduce circuit delay time due to the interconnect
as technology scales to smaller dimensions is
well known (1). The two principal approaches to this problem
are reduction of the resistance through use of Cu metallization,
and reduction of capacitance through the use of
lower dielectrics constant (κ) materials. The most prominent
changes to dielectric materials are the use of new low κ inter-
and intra-layer dielectrics (ILDs) (2). For example,
PECVD SiCOH (also know as organosilicate glass or OSG)
films or other low κ films have been used in place of SiO2 or
Fluorine doped SiO2 (FSG) (3). Changes to other dielectric
materials such as etch stop layers and Cu passivation layers
can also improve interconnect performance used either in
conjunction with SiO2 or FSG dielectrics (4), or together
with low k dielectrics (5).
Inlaid Cu process technologies (also called damascene)
have generally used silicon nitride (SiN) as Cu passivation
and etch stop layers (ESL). However, because the
dielectric constant of SiN is nearly double that of FSG and
more than double that of low κ films, it contributes disproportionately
to the effective κ value of the dielectric stack.
Integration schemes that require a thick SiN layer lose much
of the benefit of the low κ ILD. For SiCOH ILDs the problem
is exacerbated by poor etch selectivity between SiCOH
and SiN, relative to SiO2 or FSG and SiN. Due to the poor
etch selectivity a thicker SiN layer is required to achieve
etch performance with SiCOH that is equivalent to SiO2 or
FSG. The problems associated with SiN ESL can be mitigated
by the use of an alternate material. SiCN, in particular,
is an attractive replacement for SiN as both an ESL and
Cu passivation film. SiCN has a dielectric constant approximately
25% lower than SiN. SiCN also shows sub-
stantially improved selectivity compared to SiN in SiCOH
etch processes, while maintaining good etch characteristics
in etch processes developed to etch SiCN. In addition, SiCN
has excellent performance as a Cu passivation layer in terms
of electromigration and copper hillock density.
Experimental
A 0.13μm technology featuring a SiCOH intralayer
dielectric and FSG inter-layer dielectric was developed,
using an SiCN film as the etch stop and as Cu passivation
layers. In some cases an ESL is used under both
trench and via ILDs (designated Tr-ESL and Via-ESL respectively),
and in others only under the via layer ILD. A
schematic of the structure is shown in Figure 1 below.
Figure 1: Schematic of a hybrid SiCOH/FSG technology
The SiCN film is deposited in a standard parallel
plate PECVD system at temperatures between 300 and
350°C. The film properties are intermediate between an
amorphous silicon carbide and a conventional PECVD SiN,
it has a significant amount of hydrogen and has a κ value of
approximately 5.
Capacitance modeling is performed using a commercially
available finite difference solver. The structures
simulated are minimum pitch comb/comb structures with
combs at the layers above and below. Capacitance results
are presented in terms of an effective κ that is defined as the
κ value of a hypothetical dielectric without any caps, ESLs
or passivation layers that reproduces the total capacitance of
the modeled dielectric stack. The effective κ value is directly
proportional to total capacitance and captures the effect
of changes in the thickness of the different dielectrics in
a way that is intuitively related to ILD film κ values.

Results and Discussion
Implementation of an SiCN ESL reduces capacitance directly
because its dielectric constant is lower than SiN (approximately
5 for SiCN versus approximately 7 for SiN).
The effect of ESL thickness and material on κ effective is
shown in Table 1.
Table 1. Simulation data showing the effect of trench and via
ESL thickness and material on the effective dielectric constant
of the stack
ILD Ma- ESL Tr-ESL Via ESL K eff
terial
Thickness
Thickness
FSG SiN 300A 300A 4.21
FSG SiN 500A 500A 4.44
SiCOH SiN 300A 300A 3.86
SiCOH SiN 500A 500A 4.12
SiCOH SiN 700A 700A 4.35
SiCOH SiN 0A 300A 3.62
SiCOH SiN 0A 500A 3.73
SiCOH SiN 0A 700A 3.81
SiCOH SiN 0A 900A 3.87
SiCOH SiCN 300A 300A 3.62
SiCOH SiCN 500A 500A 3.74
SiCOH SiCN 700A 700A 3.86
SiCOH SiCN 0A 300A 3.50
SiCOH SiCN 0A 500A 3.54
SiCOH SiCN 0A 700A 3.57
It will be observed that the effective κ value of the
dielectric stack is dramatically affected by the thickness of
the ESL. If the ESL thickness is held constant while the
material is changed from SiN to SiCN the κ effective will be
reduced by 6%, 9% and 11% for 300A, 500A, and 700A
ESLs at both trench and via, respectively.
Figure 2 shows the measured total capacitance
plotted versus resistance for a 300A and 500A SiCN and a
300A SiN. Fitting a line to the distributions for each ESL
and comparing their values at relative resistance value of 1
shows a 6.3% capacitance improvement in the 300A SiCN
Figure 2: Total Capacitance versus Resistance
Relative Capacitance (arbitrary units)
1.1
1
.85 .9 .95 1 1.05 1.1 1.15 1.2
Relative Resistance (arbitrarty units)
(thin solid line) versus 300A SiN (thick solid line), and a
4.5% improvement comparing 500A SiCN (dashed line) to
300A SiN. These values are consistent with the 6% and 3%
κ effective reductions predicted in Table 1, and are confirmed
by more detailed statistical analysis of this and other
data. The larger than predicted improvement for the 500A
SiCN is attributable to the increase in the interlayer spacing
when the ESL thickness is increased. For simplicity of
comparison the layer to layer spacing was held constant in
the simulations shown in Table 1.
In addition to the direct improvements to κ effective
obtained by switching to a lower κ ESL, there are indirect
benefits resulting from the improved etch performance
of SiCN, especially when it used in conjunction with SiCOH
ILDs. Replacing SiO2 or FSG with SiCOH requires new
etch processes that generally have substantially lower
SiN/SiCOH selectivity than the SiN/SiO2 or SiN/FSG selectivities
in the original processes. Replacing the SiN with
SiCN restores some of the lost etch selectivity, which benefits
the overall integration.
Figure 3 shows cross sections comparing structures
built with a 500A SiCN ESL to 300A SiN ESL used at both
trench and via. Even with this increase in the SiCN ESL
thickness, the κ effective performance is still improved.
Moreover, the etch performance of the stack is improved.
The overetch of the trench into the underlying via dielectric
is reduced and the trench bottom profile is more controlled.
The integration benefits associated with the improved
selectivity of SiCN/SiCOH versus SiN/SiCOH become
even more critical for more challenging etch processes
such as a stop on ESL via etch in a via first dual inlaid integration
scheme. Figure 4 shows a set of SEM images of a
dual inlaid via etch process for a SiCOH trench ILD and an
FSG via ILD with no trench ESL. The requirement for the
etch process is to stop on the via ESL without exposing Cu
in any features across the wafer. The results in Figure 4
illustrate the effective etch selectivity by showing the ESL
removal in structures of widely varying etch rates. The ex-
Figure 3: SEM Cross sections comparing structures with 500A
SiCN (left) and 300A SiN (right)

Figure 4: Enhanced etch selectivity of SiCN versus SiN for a
dual inlaid via etch
treme slow etching feature (a center via) is shown on the left
and the fast etching feature (an edge die seal) is shown on
the right. The via etch depth was set to ensure the center
vias opened, and the figure indicates the measured ESL loss
in the edge die seal. In order to avoid exposing Cu, the ESL
thickness must be sufficiently greater than the observed loss.
For a 25% margin, approximately 500A of SiCN would be
required, while nearly 900A of SiN would be required to
achieve the same result. Referring back to Table 1, we see
that this will lead to a κ effective of 3.54 for the SiCN case,
and 3.87 for the SiN case, an 8.5% improvement for the
SiCN case.
In addition to the improvements in etch behavior
and capacitance reduction, using SiCN in a low κ interconnect
structure leads to improved Cu passivation performance.
Figure 5 compares the electromigration performance
of SiCN with and without a plasma pretreatment and SiN.
The SiCN without a pretreatment performs comparably to
the baseline SiN split. However, the SiCN split with the
pretreatment substantially outperforms the SiN, with higher
Median Time to Failure (MTTF). This split also has a
higher activation energy (6). The pretreatment modifies the
Cu SiCN interface, leading to excellent adhesion and reduced
CuO at the Cu/SiCN interface. More detailed analysis
of the effects of these treatments on the Cu/SiCN interface
may be addressed in a future publications.
Plasma pretreatments can sometimes lead to a high
density of Cu hillocks (5). These hillocks are undesirable
because they interfere with defect inspections and may lead
to reliability or integration issues. With SiN Cu passivation
layers, the density and size of the Cu hillocks grow rapidly
as treatment conditions get more severe and treatment times
are increased, and this poses a limitation on the treatment
conditions that can practically be implemented. Because the
deposition temperature of the SiCN (300-350°C) is lower
than SiN (400°C), the density of Cu hillocks is substantially
Figure 5: Reliability data for SiCN
Percent
99.99
99.9
99
95
90
80
70
50
30
20
10
5
1
reduced. Automated optical defectivity inspection shows a
20X reduction in Cu hillock density for SiCN versus SiN
where both films received pretreatments. AFM measurements
also show dramatic reduction in the size of the hillocks.
The lower tendency toward hillock formation allows
more flexibility in the optimization of pretreatments than
SiN passivation allows.
Conclusions
10 100 1000 10 4
.1
.01
The use of SiCN as a low κ etch stop and Cu passivation
layer provides significant improvements to the performance
of a Cu/SiCOH interconnect s, with a 25% lower κ
value compared to SiN. Additional benefits come from the
improved etch selectivity, which enhances the manufacturability
of etch processes and enables the use of thinner etch
stop layers, further reducing the capacitance. The Cu passivation
properties of the SiCN/Cu interface are also excellent.
With appropriate plasma pretreatments excellent electromigration
performance is observed, and the reduced deposition
temperature suppresses Cu hillocks compared to SiN.
Acknowledgements
Normalized Time to Failure
We gratefully acknowledge the staff at Motorola's Dan Noble
Center.
References
SiN
SiCN no treat
SiCN w/ treat
1. International Technology Roadmap for Semiconductors,
2001
2. W.W. Lee and P.S. Ho, MRS Bulletin Vol. 22, p. 19
(1997).
3. Aoki, H., et al., IEDM Tech. Digest, (2001)
4. Sleight, J. W., et al., IEDM Tech. Digest, (2001)
5. Shannon, V., Solid State Technology, Sept., S22 (2001)
6. Unpublished results.