nanoscience and society - IAP/TU Wien

468 Nanoelectronics
or bottom up. The present-day route to the fabrication
of nanelectronics devices relies on the top-down approach,
utilizing high-throughput optical lithography
for feature sizes down to 180 nm, and electron beam
lithography for feature sizes down to 30 nm with a low
throughput (for masks).
The top-down approach is the extension of established
methods of engineering and microelectronics
processing that relies on a selective patterning process,
often described in terms of depositing, patterning, and
etching layers of material to define the circuitry and active
elements. This approach continues with the miniaturization
of electronic components by the development
of strongly improved production processes and materials,
starting from current practices. These methods are
amenable to mass manufacturing, which has resulted in
reduced costs (per transistor) for high-end electronics
products. This approach enables developers to profit
from the low-cost mass manufacturing expertise already
acquired with silicon-based systems. However, exponentially
increasing fabrication costs and fundamental
physical limitations remain significant challenges for
continued top-down miniaturization over the next decade.
Top-down approaches rely on control of damage,
and as the structures become smaller, the defects make
device operation increasingly problematic.
In addition to the top-down approach of fabricating
nanoelectronics devices, nanoscientists are also
employing a bottom-up approach that is based on the
self-assembly techniques of atoms and molecules. Selfand
directed-assembly mechanisms are phenomena
often found in nature, from the growth of crystals to
the formation of complex functional biological systems,
including the cells of the human body. Therefore, in attempting
the bottom-up method, nature was used as a
model, and the assembly of complex structures was approached
by starting with single atoms and molecules.
However, the mechanisms of such processes are still not
well understood and research and development in this
field represents a formidable challenge.
Bottom-up nanofabrication refers to device fabrication
on an atom-by-atom basis. Bottom-up processes
use chemically or biologically inspired routes for synthesis
and assembly of nanoscale building blocks into complex
nanoarchitectures with novel electronic or optical
properties. Molecules, which are prefabricated arrangements
of atoms in a functional form, are also appealing
for bottom-up fabrication. The advantage of the bottom-up
approach lies in the design and chemical synthesis
of functional molecules by the billions, which can
then be assembled into nanoelectronic devices. Such an
approach will drastically reduce fabrication costs. However,
development of controlled assembly strategies for
integration of bottom-up nanostructures and nanoarchitectures
into electronic devices and circuits remains
a significant long-term challenge. In the medium-term,
development of hybrid top-down/bottom-up fabrication
strategies for electronics represents a key opportunity.
Progress along both of these avenues will entail a
massive amount of research effort and investment in resources.
Expert opinion is that eventually the top-down
and bottom-up approaches can both be combined into
a single nanoelectronics manufacturing process, where
certain manufacturing steps can then be carried out using
the top-down approach and others using the bottomup
approach. Such a hybrid method has the potential to
lead to a more economical nanomanufacturing process.
Emerging Devices
A single-electron transistor (SET) is a three-terminal
device that has switching properties controlled by the
addition or subtraction of one electron, or through
which only one electron may be transported at a time.
The single-electron transistor is an example of a threeterminal
device in which the charge of a single electron
is sufficient to switch the source-to-drain current. SET
devices are perceived by some to be the natural successor
to the metal-oxide semiconductor field-effect transistor
(MOSFET) although the research is also perceived
by some companies as a method to investigate the ultimate
limits of the MOSFET itself, as single electron
effects will limit normal transistor action at the smallest
length scales. SET devices are predominantly aimed at
high-density, low-power applications.
There are a number of designs for low-power SET
logics, but they do not look very encouraging due to
large time constants limiting the operation at very high
speeds. The SET, however, shows promise for memory,
probably not in the form of a single electron transistor,
but more likely in the form of a nanoflash memory,
since a number of the designs are a miniature version
of conventional flash-type memory devices. The SET
seems to be a natural extension for conventional flashtype
memory devices, and may even take over for static
random-access memory, possibly bridging the gap between
more standard CMOS and the single-electron