Virtuoso User Manual - ClassicCMP

Virtuoso : an overview
Data
ISR1
Event
Micro
Kernel
Task
Task
Task
ISR0
Sign
Process
Process
Nano Kernel
Global Interrupts Enabled
Global Interrupts Disabled
HW Interrupt
FIGURE 2
Multi level support mechanism in Virtuoso
LEVEL 2 : ISR1 level
The ISR1 level is invoked from ISR0. It is used for handling the interrupt with
global interrupts enabled. An ISR1 routine permits to raise an Event for a
waiting task. An ISR1 routine must itself save and restore the context but
permits interrupts to be nested. An ISR1 routine can be replaced by a
nanokernel process that is easier to program as the nanokernel takes care of
the context switch. When the processor supports multi-level interrupts, the
ISR1 level can be viewed as having itself multiple levels of priority. The use
of priority however should be limited only to determine what interrupts are
masked out when a given interrupt occurs.
LEVEL 3 : The nanokernel level (Processes)
This is a major breakthrough for DSP processors. The nanokernel level is
composed of tasks with a reduced context, called processes. These deliver a
P1 - 14 Virtuoso User Manual Copyright 1996 Eonic Systems