Virtuoso User Manual - ClassicCMP

Virtuoso : an overview
Most real-time kernels only provide a single ISR level and the C task level as
this is sufficient for supporting applications using standard microprocessors
and microcontrollers. This is also the case for ports of Virtuoso to this class
of processors.
3.4. An execution trace illustrated
Task/Prio1
Task/Prio2
Task/Prio3
Task/Prio4
IdleTask
T=20
LiteTask1
LiteTask2
LiteTask3
Micro-Kernel
➌
➌
➌
➍
➌
➌
T=1
ISR1-1
ISR1-2
ISR1-3
ISR1-4
➋
➋
➋
T=1
ISR0-1
ISR0-2
ISR0-3
ISR0-4
❶
❶
❶
❶
❶
❶
T=1
FIGURE 3
An execution trace of a hypothetical Virtuoso program segment
In Figure 2, we illustrate a hypothetical example that illustrates the interaction
between the different levels. The order of magnitude of the timestep is
indicated in microseconds. As can be seen any lower level has an effective
higher priority than any higher level and can preempt an activity executing at
any higher level.
The processor accepts an interrupt (1). This can be an external interrupt, a
comport interrupt or a timer interrupt. The interrupt is passed on to a higher
level for further processing. This disables interrupts for less than one microsecond
on a C40, or about 1.5 microseconds on a 96K.
P1 - 16 Virtuoso User Manual Copyright 1996 Eonic Systems