T-Kernel Specification (1.B0.02)

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170 CHAPTER 4. T-KERNEL/OS FUNCTIONS cycatr := (TA_ASM || TA_HLNG) | [TA_STA] | [TA_PHS] TA ASM TA HLNG TA STA TA PHS The handler is written in assembly language The handler is written in high-level language Activate immediately upon cyclic handler creation Save the cycle phase #define TA_ASM 0x00000000 /* assembly program */ #define TA_HLNG 0x00000001 /* high-level language program */ #define TA_STA 0x00000002 /* activate cyclic handler */ #define TA_PHS 0x00000004 /* save cyclic handler cycle phase */ cychdr designates the cyclic handler start address, cyctim the cycle time, and cycphs the cycle phase. When the TA HLNG attribute is designated, the cyclic handler is started via a high-level language support routine. The high-level language support routine takes care of saving and restoring register values. The cyclic handler terminates by a simple return from a function. The cyclic handler takes the following format when the TA HLNG attribute is designated. void cychdr( VP exinf ) { /* Processing */ return; /* Exit cyclic handler*/ } The cyclic handler format when the TA ASM attribute is designated is implementation-dependent, but exinf must be passed in a starting parameter. cycphs indicates the length of time until the cyclic hander is initially started after being created by tk cre cyc. Thereafter it is started periodically at the interval set in cyctim. If zero is designated for cycphs, the cyclic handler starts immediately after it is created. Zero cannot be designated for cyctim. The starting of the cyclic handler for the nth time occurs after at least chcphs + chctim × (n − 1) time has elapsed from the cyclic handler creation. When TA STA is designated, the cyclic handler goes to active state immediately on creation, and starts at the intervals noted above. If TA STA is not designated, the cycle time is calculated but the cyclic handler is not actually started. When TA PHS is designated, then even if tk sta cyc is called activating the cyclic handler, the cycle time is not reset, and the cycle time calculated as above from the time of cyclic handler creation continues to apply. If TA PHS is not designated, calling tk sta cyc resets the cycle time and the cyclic handler is started at cyctim intervals measured from the time tk sta cyc was called. Note that the resetting of cycle time by tk sta cyc does not affect cycphs. In this case the starting of the cyclic handler for the nth time occurs after at least cyctim × n has elapsed from the calling of tk sta cyc. Even if a system call is invoked from a cyclic handler and this causes the task in RUN state up to that time to go to another state, with a different task going to RUN state, dispatching (task switching) does not occur while the cyclic handler is running. Completion of execution by the cyclic handler has precedence even if dispatching is necessary; only when the cyclic handler terminates does the dispatch take place. In other words, a dispatch request occurring while a cyclic handler is running is not processed immediately, but is delayed until the cyclic handler terminates. This is called delayed dispatching. A cyclic handler runs as a task-independent portion. As such, it is not possible to call in a cyclic handler a system call that can enter WAIT state, or one that is intended for the invoking task. Copyright c○ 2002, 2003 by T-Engine Forum T-Kernel 1.B0.02
4.7. TIME MANAGEMENT FUNCTIONS 171 [Additional Notes] Once a cyclic handler is defined, it continues to run at the designated cycles either until tk stp cyc is called to deactivate it or until it is deleted. There is no designation of number of cycles in tk cre cyc. When multiple time event handlers or interrupt handlers operate at the same time, it is an implementationdependent matter whether to have them run serially (after one handler exits, another starts) or nested (one handler operation is suspended, another runs, and when that one finishes the previous one resumes). In either case, since time event handlers and interrupt handlers run as task-independent portion, the principle of delayed dispatching applies. Copyright c○ 2002, 2003 by T-Engine Forum T-Kernel 1.B0.02
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T-Kernel Specification T-Kernel 1.B
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Contents 1 T-Kernel Overview 1 1.1
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CONTENTS v tk set flg (Set Event Fl
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CONTENTS vii 5.2.2 Address Space Ch
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CONTENTS ix td cal que (Reference Q
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List of Figures 1.1 Position of T-K
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List of Tables 2.1 State Transition
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System Call Notation In the parts o
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Index of T-Kernel/OS System Calls T
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INDEX OF T-KERNEL/OS SYSTEM CALLS x
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Index of T-Kernel/SM Extended SVC L
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Index of T-Kernel/DS System Calls T
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Chapter 1 T-Kernel Overview 1.1 Pos
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1.2. SCALABILITY 3 • Middleware m
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Chapter 2 Concepts Underlying the T
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2.2. TASK STATES AND SCHEDULING RUL
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2.2. TASK STATES AND SCHEDULING RUL
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2.3. INTERRUPT HANDLING 11 preceden
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2.5. SYSTEM STATES 13 Transient sta
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2.7. MEMORY 15 which the upper and
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Chapter 3 Common T-Kernel Specifica
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3.2. SYSTEM CALLS 19 /* * Common co
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3.2. SYSTEM CALLS 21 Ordinarily a f
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3.3. HIGH-LEVEL LANGUAGE SUPPORT RO
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Chapter 4 T-Kernel/OS Functions Thi
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4.1. TASK MANAGEMENT FUNCTIONS 27 t
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5.1. SYSTEM MEMORY MANAGEMENT FUNCT
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5.2. ADDRESS SPACE MANAGEMENT FUNCT
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5.2. ADDRESS SPACE MANAGEMENT FUNCT
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5.3. DEVICE MANAGEMENT FUNCTIONS 22
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5.4. INTERRUPT MANAGEMENT FUNCTIONS
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5.5. IO PORT ACCESS SUPPORT FUNCTIO
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5.7. SYSTEM CONFIGURATION INFORMATI
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5.7. SYSTEM CONFIGURATION INFORMATI
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5.8. SUBSYSTEM AND DEVICE DRIVER ST
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260 CHAPTER 6. T-KERNEL/DS FUNCTION
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284 CHAPTER 7. REFERENCE INT tevptn
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286 CHAPTER 7. REFERENCE ER ercd =
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288 CHAPTER 7. REFERENCE INT ct = t
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290 CHAPTER 7. REFERENCE E OACV ERC
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T-Kernel Specification (1.B0.02)

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