Introduction to the Altera Nios II Soft Processor - FTP - Altera

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The Branch if Less Than Signed instruction blt rA, rB, LABEL performs the comparison rA < rB, treating the contents of the registers as signed numbers. The Branch if Less Than Unsigned instruction bltu rA, rB, LABEL performs the comparison rA < rB, treating the contents of the registers as unsigned numbers. The other Conditional Branch instructions are: • beq rA, rB, LABEL • bne rA, rB, LABEL • bge rA, rB, LABEL • bgeu rA, rB, LABEL (Comparison rA == rB) (Comparison rA != rB) (Signed comparison rA >= rB) (Unsigned comparison rA >= rB) • bgt rA, rB, LABEL (Signed comparison rA > rB) This is a pseudoinstruction implemented as the blt instruction by swapping the register operands. • bgtu rA, rB, LABEL (Unsigned comparison rA > rB) This is a pseudoinstruction implemented as the bltu instruction by swapping the register operands. • ble rA, rB, LABEL (Signed comparison rA
6.10 Control Instructions The Nios II control registers can be read and written by special instructions. The Read Control Register instruction rdctl rC, ctlN copies the contents of control register ctlN into register C. The Write Control Register instruction wrctl ctlN, rA copies the contents of register A into the control register ctlN. There are two instructions provided for dealing with exceptions: trap and eret. They are similar to the call and ret instructions, but they are used for exceptions. Their use is discussed in section 8.2. The instructions break and bret generate breaks and return from breaks. They are used exclusively by the software debugging tools. The Nios II cache memories are managed with the instructions: flushd (Flush Data Cache Line), flushi (Flush Instruction Cache Line), initd (Initialize Data Cache Line), and initi (Initialize Instruction Cache Line). These instructions are discussed in section 9.1. 6.11 Carry and Overflow Detection As pointed out in section 6.2, the Add and Subtract instructions perform the corresponding operations in the same way for both signed and unsigned operands. The possible carry and arithmetic overflow conditions are not detected, because Nios II does not contain condition flags that might be set as a result. These conditions can be detected by using additional instructions. Consider the Add instruction add rC, rA, rB Having executed this instruction, a possible occurrence of a carry out of the most-significant bit (C 31 ) can be detected by checking whether the unsigned sum (in register C) is less than one of the unsigned operands. For example, if this instruction is followed by the instruction then the carry bit will be written into register D. cmpltu rD, rC, rA Similarly, if a branch is required when a carry occurs, this can be accomplished as follows: add bltu rC, rA, rB rC, rA, LABEL A test for arithmetic overflow can be done by checking the signs of the summands and the resulting sum. An overflow occurs if two positive numbers produce a negative sum, or if two negative numbers produce a positive sum. Using this approach, the overflow condition can control a conditional branch as follows: add rC, rA, rB /* The required Add operation */ xor rD, rC, rA /* Compare signs of sum and rA */ xor rE, rC, rB /* Compare signs of sum and rB */ and rD, rD, rE /* Set D 31 = 1 if ((A 31 == B 31 ) ! = C 31 ) */ blt rD, r0, LABEL /* Branch if overflow occurred */ 15
Page 1 and 2: Introduction to the Altera Nios II
Page 3 and 4: The Nios II processor and the inter
Page 5 and 6: • Register ctl2 holds a saved cop
Page 7 and 8: • Absolute mode - a 16-bit absolu
Page 9 and 10: 6.2 Arithmetic Instructions The ari
Page 11 and 12: movui rB, IMMED16 zero extends the
Page 13: The srl instruction shifts the cont
Page 17 and 18: .global symbol Makes symbol visible
Page 19 and 20: Multiply instruction, it cannot be
Page 21 and 22: .org 0x20 /* Exception handler */ r

Introduction to the Altera Nios II Soft Processor - FTP - Altera

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