Introduction to the Altera Nios II Soft Processor - FTP - Altera

Altera’s Nios II is a soft processor, defined in a hardware description language, which can be implemented in
Altera’s FPGA devices by using the Quartus R○ II CAD system. This tutorial provides a basic introduction to the
Nios II processor, intended for a user who wishes to implement a Nios II based system on the Altera DE2 board.
1 Nios II System
The Nios II processor can be used with a variety of other components to form a complete system. These components
include a number of standard peripherals, but it is also possible to define custom peripherals. Altera’s DE2
Development and Education board contains several components that can be integrated into a Nios II system. An
example of such a system is shown in Figure 1.
Host computer
USB-Blaster
interface
Nios II processor
JTAG Debug
module
JTAG UART
interface
Cyclone II
FPGA chip
Avalon switch fabric
On-chip
memory
SRAM
interface
SDRAM
interface
Flash
memory
interface
Parallel I/O
interface
Serial I/O
interface
SRAM
chip
SDRAM
chip
Flash
memory
chip
Parallel
I/O port
lines
Serial
I/O port
lines
Figure 1. A Nios II system implemented on the DE2 board.
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