Digital Controller for an Interleaved Voltage Regulator - Inst.eecs ...

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$Assignment 2: Math Review$

System Issues: Steady state limit cycling of V out resulting from quantization Vout 1 bit error bin 0 bit error bin transient steady state DAC levels ADC levels -1 bit error bin
ADC and DAC Resolution Requirements ♦ Problem: Limit Cycling—Steady-state oscillations of Vout due to the quantization in the feedback loop. ♦ Solution: — To ensure that there is a steady-state DAC (DPWM) level in the zero-error bin, resolution (DAC) > resolution (ADC) (a factor of 2 seems sufficient) —Slow Integrator to settle Vout to the zero-error bin of the ADC
Page 1 and 2: Digital Controller for an Interleav
Page 3 and 4: Why Digital • Matching duty cycle
Page 5: Application: 4-Phase Buck VRM
Page 9 and 10: Transient Response without Integrat
Page 11 and 12: Introducing Sub-Bit Positioning ♦
Page 13 and 14: Dither Patterns Added To The Duty C
Page 15 and 16: Optimal Voltage Positioning What is
Page 17 and 18: Transient Response with Voltage Pos
Page 19 and 20: Block Diagram of Proposed Controlle
Page 21 and 22: Step Response with Voltage Position
Page 23 and 24: Ring Oscillator and Multiplexer Det
Page 25 and 26: Test Waveform (2) Outputs of 2 adja
Page 27: D-PWM generation Scheme Comparison

Digital Controller for an Interleaved Voltage Regulator - Inst.eecs ...

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