Digital Controller for an Interleaved Voltage Regulator - Inst.eecs ...

Digital Controller for an 

Interleaved Voltage Regulator 

Seth R. Sanders 

Angel V. Peterchev 

Jinwen Xiao 

sanders@eecs.berkeley.edu 

peterch@eecs.berkeley.edu 

xjw@eecs.berkeley.edu 

EECS Department 

U.C. Berkeley 

Berkeley, CA 94720

DIGITAL PWM CONTROL 

— Motivation 

• Develop Low-Cost High-Flexibility Digital 

Controllers for broad range of PWM Control 

Applications (e.g. high quality power supply 

for next generation of Pentium CPU’s for 

desktop and portable computing) 

• Capture high frequency applications (>500 

KHz) not usually addressed with existing 

digital controllers

Why Digital 

• Matching duty cycles among all phases in 

multi-phase converter, thus eliminating the 

need of current sensing at each phase 

• Immune to analog component variations on 

chip 

• Implement sophisticated control schemes for 

better performance 

• Programmable by a digital system like the 

CPU 

• Technology Scaling, shorter design period

Issues 

• Controller Architecture 

• Resolution—A/D, D/A 

• Development of control schemes that account 

for the non-linearity inherent in a quantized 

system 

• IC implementation of cost- and powerefficient 

modules such as PWM generation 

and A/D, D/A conversion functions

Application: 4-Phase Buck 

VRM

System Issues: 

Steady state limit cycling of V out resulting from quantization 

Vout 

1 bit error bin 


transient 

steady state 

DAC levels 

ADC levels 

-1 bit error bin

ADC and DAC Resolution Requirements 

♦ Problem: 

Limit Cycling—Steady-state oscillations of Vout due to the 

quantization in the feedback loop. 

♦ Solution: 

— To ensure that there is a steady-state DAC (DPWM) level in 

the zero-error bin, 

resolution (DAC) > resolution (ADC) 

(a factor of 2 seems sufficient) 

—Slow Integrator to settle Vout to the zero-error bin of the ADC

Transient response with res(DAC) = 2 • res(ADC) , and 

an integrator 

Vout 


transient 

steady state 


-1 bit error bin 

DAC levels 

ADC levels

Transient Response without Integrator (simulation) 

Vin = 5 V , Vref = 2 V, res (ADC) = 8 bit , res (DAC) = 9 bit 

2.01 

2 

1.99 

1.98 

light load ← → heavy load 

↑ 

reference voltage bin 

↓ 

Limit cycling ↑ 

in steady state 

V out 

1.97 

1.96 

1.95 

1.94 

ADC levels 

↓ 

1.93 

1.92 

1.91 

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 

time (msec)

Transient Response with Integrator (simulation) 


2.01 

2 

1.99 

1.98 

↑ 


↓ 

↑ 

No limit cycling 

light load ← → heavy load 

in steady state 

V out 

1.97 

1.96 

1.95 

1.94 

ADC levels 

↓ 

1.93 

1.92 

1.91 

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 

time (msec)

Introducing Sub-Bit Positioning 

♦ Problem: 

To provide accurate positioning of the output voltage at the 

order of 5 mV, the resolution of the DAC (DPWM) has to be 10 

bit with 5 V input. This resolution requires a DPWM module with 

a large number of stages running at a high frequency → high 

power dissipation. 

♦ Solution: 

Sub-Bit Positioning—use a DPWM module with lower 

hardware resolution (e.g. 7 or 8 bits) and add digital dither to the 

duty cycle to produce finer (sub-bit) levels of Vout.

Structure for Adding Arbitrary Dither 

Patterns to the Duty Cycle 

f sw 

switching 

frequency 

D c 

duty cycle 

n + m 

m-bit 

counter 

m 

m (LSB’s) 

m x m 

look-up 

table 

1 (LSB) 

saturated 

n-bit 

adder 

n 

D c 

’ 

dithered 

duty cycle 

n (MSB’s)

Dither Patterns Added To The Duty Cycle 

vs. Counter (Example For m = 2 Bits) 

counter 

Dc 

LSB’s 

00 

Sawtooth dither 

pattern 

00 01 10 11 

Modified dither 

pattern 

00 01 10 11 

Averaged 

sub-bit 

levels 

0 

01 

¼ 

10 

½ 

11 

¾ 

T sw * 4 

T sw * 4 

♦ Modified dither patterns have higher frequency for some 

sub-bit levels, and hence produce smaller ripple on Vout

Transient Response with Sub-Bit Positioning 

Transient Response with Sub-Bit Positioning 

11-bit ADC , 9-bit DAC + 3-bit SBP = effective effectve 12-bit DAC 

2.01 

2 

1.99 

↓ 

↑ 


1.98 

V out 

1.97 

1.96 

1.95 

→ heavy load 

Vout finds a steady state 

within the reference bin due 

to the effective increase in 

DAC resolution 

1.94 

1.93 

1.92 

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 

time (msec)

Optimal Voltage Positioning 

What is it? 

Io max 

Load Step 

Iout 

∆I o 

Io min 

Usual converter 

response 

Vout 

2 * ∆I o *R esr 

Response with 

optimal voltage 

positioning 

Vout 

∆I o *R esr

Implementation of Optimal Voltage Positioning 

with I L 

and I C 

sensing 

Vin 

Vref 

+ 

_ 

Ke 

error 

amplifier 

digital 

controller 

- 

L1 

I L 

Re 

Re*m 

Vc 

Co/m 

Re 

Co 

Iout 

Ic 

Vout 

- 

- 

Ic estimator 

Vo’ = Vout + Re * Iout 

Re * Iout = Re * (I L 

+ Ic) = Re * I L 

+ (Vc – Vout) 

Vo’ = Vc + Re * I L 

Advantage: Doesn’t add a resistive current sensor for Iout after Co (the voltage drop 

across such sensor would add to the ESR drop during transients).

Transient Response with Voltage Positioning (simulation) 


2.02 

2 

1.98 

↑ 

V out 

+ I out 

• R esr 

↑ 

reference bin 

↓ 

volts 

1.96 

1.94 

→ max load 

1.92 

V out 

↓ 

1.9 

1 2 3 4 5 6 

time (msec)

Pro’s and Con’s of Voltage Positioning 

Pro’s: 

♦ Resr can be increased by a factor of 2 

Output capacitor size can be reduced by a factor of 2. 

♦ Simple 3-level ADC (e.g. two comparators) can be used, since 

the controlled quantity V o ’ has small excursions from the reference 

bin. 

Con’s: 

♦ Output current sensing required. 

♦ Value of Resr should be known.

Block Diagram of Proposed Controller Architecture 

with I L sensing and I C estimation 

5 bit VID from 

microprocessor 

Vin 

Vref 

5,6bit 

slow 

DAC 

digital module 

feedforward 

L1 

I L 

= Σ I Li 

all phases 

Vout 

+ 

_ 

Ke 

Ve 

error 

amplifier 

simple 

3,5-level 

ADC 

PID 

SBP 

DPWM 

- 

to other 

phases 

Re 

- 

Re*m 

Vc 

Co/m 

- 

Re 

Co 

Vo’ = Vout + Re * Iout 

♦ This architecture avoids individual sensing of the different phase currents

Step Response with Voltage Positioning and Sub-Bit Positioning 

(simulation) 

V in 

= 5V, V ref 

= 2V, R esr 

= 3.5mΩ, ∆I = 10A, 

res(9-Bit ADC) = 10mV, res(DAC) = 5mV (7 bit + 3 bit dither = 10 bit) 

2.04 

2.02 

2 

steady-state 

(no limit cycling) 

ESR drop 

Transient before the 

integrator has adjusted 

V out 

(V) 

1.98 

1.96 

1.94 

1.92 

1.9 

Load step 

∆I = 10A 

550 600 650 700 750 800 850 900 950 1000 

time (usec)

Step Response with Voltage Positioning and Sub-Bit Positioning 

(test waveform) 

V in 

= 5V, V ref 

= 2V, R esr 

= 3.5mΩ, ∆I = 10A, 

res(9-Bit ADC) = 10mV, res(DAC) = 5mV (7 bit + 3 bit dither = 10 bit) 

steady-state 

(no limit cycling) 

ESR drop 

transient before the 

integrator has adjusted 

Load step 

∆I = 10A

PWM Generation Scheme 

— A Ring-Mux Structure

Ring Oscillator and Multiplexer 

Detail

Test Waveform (1) 

Differential outputs in one of 128 stages(1MHz)

Test Waveform (2) 

Outputs of 2 adjacent stages, showing 1 LSB phase shift 

Oscillation Freq. = 1MHz, 1LSB = 1µs • 1/2 8 = 4ns 

4ns

PWM Generation Scheme 2 

— Counter-Comparator Structure for Phase 1

D-PWM generation Scheme 

Comparison 

Scheme Technology Clock 

(MHz) 

Counter- .5µm 5V 200MHz 

Comparator 1 (4x) 

Ring-Mux 2 .25µm 2.5V 100K- 

1MHz 

Area 

(µm×µm) 

1200×700 

(normalized to 

600×350) 

Power 

(µW) 

Hardware 

Sharing for 

4 Phases 

50,000 LOW 

350×240 7.5 – 87.5 HIGH 

1. D-PWM has 10 bit resolution. 

2. D-PWM has effective 11 bit resolution, 8 MSB from the Ring-Mux 

structure and its accessory circuit , 3 LSB from Sub-Bit Positioning.

Digital Controller for an Interleaved Voltage Regulator - Inst.eecs ...

Create successful ePaper yourself

Delete template?

Save as template?