Latches and Flip Flops

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Flip Flops @ P. Klimo Excerxise: R-S Latch with Low Asserted Inputs. Design a sequential circuit which is described by the following Next State table: Base your design on NAND gates. Solution: Inputs Next State (*) R S Q* (Q’)* Comment 1 1 Q Q’ hold 1 0 1 0 set 0 1 0 1 reset 0 0 0 0 unstable TABLE 2 Step 1: Implement as a combinatorial circuit with a (single) feedback loop: Step 2: Break the feedback loop and analyse the transition from the present state Q to the next state Q*: Step 3: Draw the K map for output Q* in terms of inputs R, S and Q: INPUTS Q R S 00 01 11 10 0 X 0 0 1 1 X 0 1 1 K-map for Q* 2
Flip Flops @ P. Klimo Step 4: Solve the K map to obtain the so called characteristic equation : Q* = Q.R + S’ Step 5: Implement the characteristic equation using NAND gates: Q* = Q.R + S’ = ( (Q.R)’ .S )’ Figure 2: R S Latch with low asserted inputs. Characteristic Equation of R-S Latch : Expresses the next state Q* as a function of the present state Q and of the inputs (R and S). Q* = (forcing term) + Q. (holding term) Q* = S’ + Q .R Exercise: Derive the characteristic equations for the R-S latch in figure 1. Answer: Q* = S+R’. Q Excitation Map for R-S Latch: Given a state transition Q -> Q*, the excitation map shows the combination of R and S inputs which are required to produce it. Current State Next State Required Inputs Q Q* R S ______________________________________________ 0 0 X 0 0 1 0 1 1 1 0 X 1 0 1 0 3
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