Latches and Flip Flops

Flip Flops
@ P. Klimo
Propagation Delays and Static Hazards:
Single Gate Propagation Delay t pd : time delay (in nS) between gate output reaction
to the input change. (Sometimes t pd is specified separately for low to high and high to
low transitions.)
Example:
Figure 6: Cascaded XOR Gates.
Figure 7: Time Diagram of Cascaded XOR Gates.
Circuit in figure 5 shows that the implementation experiences a static 0 hazard on the
output. According to Boolean law the OUT should always remain low, but because of
the t pd (10 nS) of the XOR gates a high glitch will appear.
Figure 8: Improved design produces no glitch.
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