Latches and Flip Flops

Flip Flops
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Latches and Flip Flops
Bistable
State Q1 Q2 Comment
S1 1 0 stable
S2 0 1 stable
S3 1/2 1/2 unstable
Set – Reset (Set – Clear) Latch.
Figure 1
Inputs Next State (*)
R S Q* (Q’)* Comment
0 0 Q Q’ hold
0 1 1 0 set
1 0 0 1 reset
1 1 0 0 unstable
TABLE 1
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Flip Flops
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Excerxise: R-S Latch with Low Asserted Inputs.
Design a sequential circuit which is described by the following Next State table:
Base your design on NAND gates.
Solution:
Inputs Next State (*)
R S Q* (Q’)* Comment
1 1 Q Q’ hold
1 0 1 0 set
0 1 0 1 reset
0 0 0 0 unstable
TABLE 2
Step 1: Implement as a combinatorial circuit with a (single) feedback loop:
Step 2: Break the feedback loop and analyse the transition from the present state Q to
the next state Q*:
Step 3: Draw the K map for output Q* in terms of inputs R, S and Q:
INPUTS
Q R S
00 01 11 10
0 X 0 0 1
1 X 0 1 1
K-map for Q*
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Flip Flops
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Step 4: Solve the K map to obtain the so called characteristic equation :
Q* = Q.R + S’
Step 5: Implement the characteristic equation using NAND gates:
Q* = Q.R + S’ = ( (Q.R)’ .S )’
Figure 2: R S Latch with low asserted inputs.
Characteristic Equation of R-S Latch : Expresses the next state Q* as a function of
the present state Q and of the inputs (R and S).
Q* = (forcing term) + Q. (holding term)
Q* = S’ + Q .R
Exercise: Derive the characteristic equations for the R-S latch in figure 1.
Answer: Q* = S+R’. Q
Excitation Map for R-S Latch: Given a state transition Q -> Q*, the excitation
map shows the combination of R and S inputs which are required to produce it.
Current State Next State Required Inputs
Q Q* R S
______________________________________________
0 0 X 0
0 1 0 1
1 1 0 X
1 0 1 0
3

Flip Flops
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D (Data) Latch.
Figure 3: Implementation of D latch.
Characteristic equation of D latch :
Q* = D
D Latch with Enable (transparent latch):
Inputs Next State (*)
D E Q* Comment
0 0 Q n
hold
1 0 Q n
hold
0 1 0
reset
1 1 1 set
TABLE 3.
Example: Design of D Latch with Enable.
Draw a K map for Table 3:
D E
Q 0 0 0 1 1 1 1 0
0 0 0 1 0
1 1 0 1 1
Figure 4: K-map for Q*
Characteristic Equation of transparent D latch: Q* = D.E + E’.Q
4

Flip Flops
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Excitation map:
Current State Next State Required Inputs
Q Q* D E
______________________________________________
0 0 X 0
0 1 1 1
1 1 X 0
1 0 0 1
Implementation of transparent D latch.
Figure 5 : D-Latch with Enable.
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Flip Flops
@ P. Klimo
Propagation Delays and Static Hazards:
Single Gate Propagation Delay t pd : time delay (in nS) between gate output reaction
to the input change. (Sometimes t pd is specified separately for low to high and high to
low transitions.)
Example:
Figure 6: Cascaded XOR Gates.
Figure 7: Time Diagram of Cascaded XOR Gates.
Circuit in figure 5 shows that the implementation experiences a static 0 hazard on the
output. According to Boolean law the OUT should always remain low, but because of
the t pd (10 nS) of the XOR gates a high glitch will appear.
Figure 8: Improved design produces no glitch.
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Flip Flops
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Example:
The D Latch with enable, as implemented in figure 5, also produces a glitch.
Assume Q = D =1 and E changes from 1 to 0. The output should remain high.
However, because of the propagation delay introduced by the inverter, the output of
the upper AND goes low before the output of the lower AND goes high. So the Q
output swings low and because of the feedback loop it stays low. This is a so called
static hazard one.
E D
Q 0 0 0 1 1 1 1 0
0 0 0 1 0
1 1 1 1 0
Looking at the K-map of the D latch in figure 4 (reproduced above) one observes that
the possibility of a hazard one arises for the transitions across the boundary between
the two prime implicants E.D and E’.Q when Q=1 (bottom row).
.
To overcome the static hazard introduce an extra AND gate to cover the transition
between the cells indicated by the arrows. This requires an additional term D.Q:
Q* = E.D + E’.Q + D.Q
Figure 9: Improved D Latch with enable.
7

Flip Flops
@ P. Klimo
Flip Flops (FF) – Synchronous Devices.
With FF, the transitions to the next state are synchronised with a clock (rising or
falling ) edges.
D Flip Flop:
Figure 10: Symbol of a Negative (or Falling) Edge D Flip-Flop
Figure 11: Implementation of a Negative Edge Master-Slave D Flip-Flop.
Timing Diagram of the M-S D Flip-Flop
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Flip Flops
@ P. Klimo
Figure 12: Implementation of D Flip-Flop using a Pulse Transition Detector.
R-S Flip Flop:
Figure 13: Pulse Transition Detector.
Figure 14: Symbol for a Falling Edge R-S Flip-Flop
Figure 15: Implementation of a Master Slave RS FF.
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Flip Flops
@ P. Klimo
JK Flip Flop:
Figure 16: Implementation of RS latch using Pulse Transition Detector
Figure 17: Symbol for a Positive (Rising) Edge JK Flip-Flop
Description of JK Flip-Flop Behaviour.
J K Q* Mode
0 0 Q hold
0 1 0 reset
1 0 1 set
1 1 Q’ toggle
Truth Table for JK Flip Flop
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Flip Flops
@ P. Klimo
Next State Diagram for JK Flip Flop.
Present
State
Inputs
Next
State
Q J K Q*
0 0 0 0
1 0 0 1
0 1 0 1
1 1 0 1
0 0 1 0
1 0 1 0
0 1 1 1
1 1 1 0
Next State Table for JK Flip Flop.
Characteristic equation of JK Flip Flop:
Q* = J.Q’ + K’.Q
Homework: derive the above equation from the Next State Table.
Transition Req. inputs
Q -> Q* J K
0 0 0 X
0 1 1 X
1 1 X 0
1 0 X 1
Excitation map for JK flip flop
11

Flip Flops
@ P. Klimo
Exercise: Implementation of JK Flip Flop using a RS Flip Flop
Block Diagram.
Figure 18: JK Flip-Flop as a Finite State Machine
Next State Logic:
K - Map for S:
Q
J K 0 1
0 0 0 0
0 1 0 0
1 1 1 0
1 0 1 0
S = J.Q’
K-Map for R:
Q
J K 0 1
0 0 0 0
0 1 0 0
1 1 1 0
1 0 1 0
R = K.Q
Figure 19: A realisation of J K Flip Flop using a RS Flip Flop
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Flip Flops
@ P. Klimo
Timing Definitions for (Negative) Clock Edge Operation
Synchronous inputs have to be stable for a minimum time t s – set up time before the
arrival of the clock edge and remain stable for a a duration t h – hold up time.
Asynchronous inputs (set and reset) override the clock.
Figure 20: Definition of Set-up and Hold times.
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