Volume 3, Part 2 - Display Registers - Codon.org.uk

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2.4.4 DPFC_CPU_Fence_Offset — Y Offset CPU Fence Base to Display Buffer Base DPFC_CPU_Fence_Offset — Y Offset CPU Fence Base to Display Buffer Base Register Type: MMIO Address Offset: 43218h Project: All Default Value: 00000000h Access: R/W Size (in bits): 32 The contents of this register can not be changed while compression is enabled. Bit Description 31:22 Reserved Project: All Format: MBZ 21:0 Yfence_disp Project: All Y offset from the CPU fence to the Display Buffer base. [DevSNB] The CPU fence is always programmed to match the Display Buffer base, so this offset must be programmed to 0 to match. 26 IHD-OS-022810-R1V3PT2
2.5 Interrupt Control Registers 2.5.1 Display Engine Interrupt Registers Bit Definition Display Engine Interrupt Registers Bit Definition Project: All Size (in bits): 32 Display Engine (DE) interrupt bits come from events within the display engine, except for some which explicitly list a non-display engine source. The DEIIR and GTIIR and PMIIR are ORed together to generate the CPU interrupt. The Display Engine Interrupt Control Registers all share the same bit definitions from this table. Bit Description 31 Master_Interrupt_Control Project: All Format: This bit exists only in the DEIER Display Engine Interrupt Enable Register. This is the master control for the Display to CPU interrupt. This bit must be set to 1 for any interrupts to propagate to the system. 30 Reserved Project: All Format: 29 Sprite_Plane_B_flip_done Project: All Format: This is an active high pulse when a sprite plane B flip is done. 28 Sprite_Plane_A_flip_done Project: All Format: This is an active high pulse when a sprite plane A flip is done. 27 Primary_Plane_B_flip_done Project: All Format: This is an active high pulse when a primary plane B flip is done. 26 Primary_Plane_A_flip_done Project: All Format: This is an active high pulse when a primary plane A flip is done. 25 PCU_event [DevILK]: Project: DevILK Format: This is an active high pulse when a thermal or render geyserville event has occured. Interrupt source and status should be checked in RGVINTRSTS (MCHBAR+1184h) and TIS1 (MCHBAR+101Eh). This event comes display directly on a wire. 25 Reserved Project: DevSNB Format: 24 GTT_fault Project: All Format: This is an active high level while either of the GTT Fault Status register bits are set. 23 Poison Project: All Format: This is an active high pulse on receiving the poison message. 22 Performance_counter Project: All Format: This is an active high pulse when the performance counter reaches the threshold value programmed in the Performance Counter Source register. IHD-OS-022810-R1V3PT2 27
Page 1 and 2: Intel ® HD Graphics OpenSource PRM
Page 3 and 4: Revision History Document Number Re
Page 5 and 6: 2.9 Refresh Rate Hardware Control R
Page 7 and 8: 1.1.1 Terminology Description Softw
Page 9 and 10: Enable panel power as needed to ret
Page 11 and 12: 2. North Shared Functions (40000h-
Page 13 and 14: VGACNTRL—VGA Display Plane Contro
Page 15 and 16: 2.2 Sine ROM Registers 2.2.1 SINE_R
Page 17 and 18: DE_POWER1 - Display Engine Power Re
Page 19 and 20: DE_POWER1 - Display Engine Power Re
Page 21 and 22: DPFC_CONTROL— DPFC Control Bit De
Page 23 and 24: DPFC_CONTROL— DPFC Control 24:16
Page 25: 2.4.3 DPFC_RECOMP_CTL — DPFC ReCo
Page 29 and 30: Display Engine Interrupt Registers
Page 31 and 32: 2.5.4 DEIIR — Display Engine Inte
Page 33 and 34: 2.5.6 GT Interrupt Registers Bit De
Page 35 and 36: GT Interrupt Registers Bit Definiti
Page 37 and 38: 2.5.7 GTISR — GT Interrupt Status
Page 39 and 40: 2.5.10 GTIER — GT Interrupt Enabl
Page 41 and 42: 2.5.12 PMISR — PM Interrupt Statu
Page 43 and 44: 2.5.15 PMIER — Power Management I
Page 45 and 46: 2.5.17 GTT Fault Status Register Re
Page 47 and 48: GTT Fault Status Register 0 Primary
Page 49 and 50: 2.7 Display Arbitration Control 2.7
Page 51 and 52: DISP_ARB_CTL—Display Arbiter Cont
Page 53 and 54: 2.8 Display Watermark Registers The
Page 55 and 56: 2.8.3 WM1—Low Power 1 Display Wat
Page 57 and 58: WM3—Low Power 3 Display Watermark
Page 59 and 60: 2.10 Backlight Control and Modulati
Page 61 and 62: 2.10.3 BLM_HIST_CTL—Image Enhance
Page 63 and 64: BLM_HIST_CTL—Image Enhancement Hi
Page 65 and 66: 2.10.5 Histogram Threshold Guardban
Page 67 and 68: MBM_CTRL—MBM Control 28:27 MBM_Su
Page 69 and 70: 2.12 Color Conversion & Control Reg
Page 71 and 72: 2.12.1 Pipe A Color Control 2.12.1.
Page 73 and 74: 2.12.1.4 CSC_A_Coefficients 4 CSC_A
Page 75 and 76: CSC_A_Mode 2 CSC_Black_Screen_Offse
Page 77 and 78:
2.12.1.10 Pre-CSC_A Low Color Chann
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2.12.2.4 CSC_B_Coefficients 4 CSC_B
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CSC_B_Mode 2 CSC_Black_Screen_Offse
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2.12.2.10 Pre-CSC_B Low Color Chann
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2.13.2 LGC_PALETTE_B—Pipe B Legac
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PREC_PALETTE_A—Pipe A Precision D
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2.13.5 PIPEAGCMAX—Pipe A Gamma Co
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2.14.2 GT Scratchpad GT Scratchpad
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3.1.1.2 HBLANK_A—Pipe A Horizonta
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3.1.1.4 VTOTAL_A—Pipe A Vertical
Page 97 and 98:
VSYNC_A—Pipe A Vertical Sync Regi
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3.1.2 Pipe A M/N Values Calculation
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3.1.2.3 PipeADataN2— Pipe A Data
Page 103 and 104:
3.1.2.6 PipeADPLinkM2— Pipe A Lin
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3.1.3.2 PipeBDataN1— Pipe B Data
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3.1.3.6 PipeBDPLinkN1— Pipe B Lin
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PFA_PWR_GATE_CTRL—Panel Fitter A
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PFB_PWR_GATE_CTRL—Panel Fitter B
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PFA_WIN_POS—Panel Fitter A Window
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3.1.4.4 PF_CTRL_1—Panel Fitter Co
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PFB_CTRL_1—Panel Fitter B Control
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Panel Fitter Coefficient Definition
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PFB_HFILTL_COEF—Panel Fitter B Ho
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3.1.7.1 PF_VFILTL_COEF—Panel Fitt
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4. Plane Controls (70000h-7FFFFh) 4
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PIPEA_SLC—Pipe A Display Scan Lin
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PIPEACONF—Pipe A Configuration Re
Page 131 and 132:
PIPEACONF—Pipe A Configuration Re
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4.1.2 Display Pipeline A Counters a
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4.1.3 Display Timestamp This regist
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4.1.4.2 PIPEB_SLC—Pipe B Display
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PIPEBCONF—Pipe B Configuration Re
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PIPEBCONF—Pipe B Configuration Re
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4.1.5 Display Pipeline B Counters a
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4.1.6.1 CURACNTR—Cursor A Control
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5 Cursor Mode Select CURACNTR—Cur
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4.1.6.3 CURAPOS—Cursor A Position
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4.1.6.5 CURAPALET—Cursor A Palett
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4.1.7 Cursor B Plane Control Regist
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4.1.7.2 CURBBASE—Cursor B Base Ad
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4.1.7.4 CURBPALET—Cursor B Palett
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DSPACNTR—Primary A Control Regist
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DSPACNTR—Primary A Control Regist
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4.1.8.3 DSPASTRIDE—Primary A Stri
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4.1.8.5 DSPATILEOFF—Primary A Til
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DSPBCNTR—Primary B Control Regist
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DSPBCNTR—Primary B Control Regist
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DSPBSTRIDE—Primary B Stride Regis
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4.1.10 Video Sprite A Control Two v
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DVSACNTR—Video Sprite A Control R
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DVSACNTR—Video Sprite A Control R
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SPRITE YUV Y1 U Y2 V YUV 4:2:2 YUYV
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4.1.10.4 DVSAPOS—Video Sprite A P
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4.1.10.6 DVSAKEYVAL—Video Sprite
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4.1.10.8 DVSASURF—Video Sprite A
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DVSATILEOFF—Video Sprite A Tiled
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DVSASCALE—Video Sprite A Scaler C
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These registers are used to determi
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4.1.11.1 DVSBCNTR—Video Sprite B
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DVSBCNTR—Video Sprite B Control R
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DVSBCNTR—Video Sprite B Control R
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4.1.11.2 DVSBLINOFF—Video Sprite
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4.1.11.4 DVSBPOS—Video Sprite B P
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4.1.11.6 DVSBKEYVAL—Video Sprite
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4.1.11.8 DVSBSURF—Video Sprite B
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4.1.11.10 DVSBTILEOFF—Video Sprit
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DVSBSCALE—Video Sprite B Scaler C
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IHD-OS-022810-R1V3PT2 211
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