Volume 3, Part 2 - Display Registers - Codon.org.uk

Contents
1.1 Introduction and Register Summary.....................................................................................................6
1.1.1 Terminology ....................................................................................................................................7
1.1.2 Register Protection for Panel Protection ........................................................................................7
1.1.3 Display Mode Set Sequence ..........................................................................................................8
2. North Shared Functions (40000h–4FFFFh) .......................................................................................11
2.1 VGA Control Registers .......................................................................................................................11
2.1.1 VGACNTRL—VGA Display Plane Control Register.....................................................................11
2.2 Sine ROM Registers...........................................................................................................................15
2.2.1 SINE_ROM—Sine ROM...............................................................................................................15
2.3 Power Measurement Registers ..........................................................................................................16
2.3.1 DE_POWER1 – Display Engine Power Register 1 ......................................................................16
2.3.2 DE_POWER2 – Display Engine Power Register 2 ......................................................................19
2.4 DPFC Control Registers (43200h–433FFh) .......................................................................................20
2.4.1 DPFC_CB_BASE – DPFC Compressed Buffer Base Address....................................................20
2.4.2 DPFC_CONTROL— DPFC Control .............................................................................................20
2.4.3 DPFC_RECOMP_CTL — DPFC ReComp Control......................................................................25
2.4.4 DPFC_CPU_Fence_Offset — Y Offset CPU Fence Base to Display Buffer Base ......................26
2.5 Interrupt Control Registers .................................................................................................................27
2.5.1 Display Engine Interrupt Registers Bit Definition..........................................................................27
2.5.2 DEISR — Display Engine Interrupt Status Register.....................................................................29
2.5.3 DEIMR — Display Engine Interrupt Mask Register......................................................................30
2.5.4 DEIIR — Display Engine Interrupt Identity Register.....................................................................31
2.5.5 DEIER — Display Engine Interrupt Enable Register....................................................................32
2.5.6 GT Interrupt Registers Bit Definition.............................................................................................33
2.5.7 GTISR — GT Interrupt Status Register........................................................................................37
2.5.8 GTIMR — GT Interrupt Mask Register.........................................................................................37
2.5.9 GTIIR — GT Interrupt Identity Register........................................................................................38
2.5.10 GTIER — GT Interrupt Enable Register.....................................................................................39
2.5.11 Power Management Interrupt Registers Bit Definition [DevSNB] ..............................................40
2.5.12 PMISR — PM Interrupt Status Register .....................................................................................41
2.5.13 PMIMR — Power Management Interrupt Mask Register ...........................................................41
2.5.14 PMIIR — Power Management Interrupt Identity Register ..........................................................42
2.5.15 PMIER — Power Management Interrupt Enable Register .........................................................43
2.5.16 Digital Port Hot Plug Control Register ........................................................................................43
2.5.17 GTT Fault Status Register..........................................................................................................45
2.6 Display Engine Render Response .....................................................................................................47
2.6.1 Display Engine Render Response Message Bit Definition..........................................................47
2.6.2 DERRMR — Display Engine Render Response Mask Register..................................................48
2.7 Display Arbitration Control..................................................................................................................49
2.7.1 DISP_ARB_CTL—Display Arbiter Control ...................................................................................49
2.7.2 DISP_ARB_CTL2—Display Arbiter Control 2 [DevSNB] .............................................................51
2.8 Display Watermark Registers.............................................................................................................53
2.8.1 WM0_PIPE_A—Pipe A Main Watermarks ...................................................................................53
2.8.2 WM0_PIPE_B—Pipe B Main Watermarks ...................................................................................54
2.8.3 WM1—Low Power 1 Display Watermarks....................................................................................55
2.8.4 WM2—Low Power 2 Display Watermarks....................................................................................55
2.8.5 WM3—Low Power 3 Display Watermarks....................................................................................56
2.8.6 WM1S—Low Power 1 Sprite Watermark .....................................................................................57
4 IHD-OS-022810-R1V3PT2