Volume 3, Part 2 - Display Registers - Codon.org.uk

VBLANK_A—Pipe A Vertical Blank Register
28:16 Pipe_A_Vertical_Blank_End Project: All
This 13-bit field specifies the Vertical Blank End position expressed in terms of the absolute Line
number relative to the vertical active display start. The value programmed should be the VBLANK End
line position, where the first active line is considered line 0, the second active line is considered line 1,
etc. The end of vertical blank should be after the start of vertical blank and before or equal to the
vertical total. This register should be loaded with the Vactive+BottomBorder+VBlank-1. For
interlaced display modes, hardware automatically divides this number by 2 to get the vertical blank end
in each field. It does not count the two half lines that get added when operating in modes with half
lines.
The border must be 0, so this register must always be programmed to the same value as the Vertical
Total.
15:13 Reserved Project: All Format:
12:0 Pipe_A_Vertical_Blank_Start Project: All
This 13-bit field specifies the Vertical Blank Start expressed in terms of the absolute line number
relative to the vertical active display start. The value programmed should be the VBLANK Start line
position, where the first active line is considered line 0, the second active line is considered line 1, etc.
Minimum vertical blank size is required to be at least three lines. Blank should start after the end of
active. This register is loaded with the Vactive+BottomBorder-1. For interlaced display modes,
hardware automatically divides this number by 2 to get the vertical blank start in each field. It does not
count the two half lines that get added when operating in modes with half lines.
The border must be 0, so this register must always be programmed to the same value as the Vertical
Active.
3.1.1.6 VSYNC_A—Pipe A Vertical Sync Register
MMIO
Address Offset: 60014h
Project: All
Default Value: 00000000h
Access: R/W
Size (in bits): 32
Bit
VSYNC_A—Pipe A Vertical Sync Register
Description
31:29 Reserved Project: All Format:
28:16 Pipe_A_Vertical_Sync_End Project: All
This 13-bit field specifies the Vertical Sync End position expressed in terms of the absolute Line
number relative to the vertical active display start. The value programmed should be the VSYNC End
line position, where the first active line is considered line 0, the second active line is considered line 1,
etc. This register should be loaded with Vactive+BottomBorder+FrontPorch+Sync-1. For interlaced
display modes, hardware automatically divides this number by 2 to get the vertical sync end in each
field. It does not count the two half lines that get added when operating in modes with half lines.
96 IHD-OS-022810-R1V3PT2