Spacecraft Controller on a Chip - Microelectronics - ESA

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Building Blocks For System on a Chip – <strong>Spacecraft</strong> <strong>Controller</strong> on a Chip Performance of the system The SCoC presents limitation Bottleneck identified at CPU SRAM level and AHB bus Reduces maximum performances COMPUTATION OF PERFORMANCES ON CPU AHB BUS Global Hypothesis Masters Hypotheses Maximum allowed bus load 80% Processor Bus Frequency 100 MHz CPU usage ratio 65,5% Instruction cache hit ratio 80% Slaves Hypotheses Data cache hit ratio 80% Memory controller Load instruction ratio 10% RAM Read Wait states 0 Store instruction ratio 5% RAM Write Wait States 0 Instruction cache fill burst length 4 MCTRL AHB WS on first read access 3 MCTRL AHB WS on next read access 2 Spacewire MCTRL AHB WS on first write access 3 overall Spacewire TX bit rate 100 Mbits/s MCTRL AHB WS on next write access 2 overall Spacewire RX bit rate 100 Mbits/s PCI PCI write rate PCI read rate 0,5 Mwords/s 0,5 Mwords/s Page 10 Microelectronics Presentation Days. 4 and 5 of February 2004
Building Blocks For System on a Chip – <strong>Spacecraft</strong> <strong>Controller</strong> on a Chip Possible Performance Enhancement Use of Multi-layer AHB and a second external RAM interface LEON (CPU) CPU Memory controller Spacewire 1 Spacewire 2 Spacewire 3 PTCD PTME PCI High Speed IO Memory controller Low Speed IO Memory <strong>Controller</strong> DMA controller 1553 BC/BM/RT 3 layers AHB interconnect matrix Increases the number of external I/O (which is already high) Page 11 Microelectronics Presentation Days. 4 and 5 of February 2004
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