Spacecraft Controller on a Chip - Microelectronics - ESA

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Building Blocks For System on a Chip – <strong>Spacecraft</strong> <strong>Controller</strong> on a Chip Distributed DMA control DMA controller are integrated at IP core level in order to have Core specific capabilities –Into the PCI interface : burst access, prefetch … –Into the Spacewire : double buffer management, linked list of packets –Into the Mil-Std-1553 : Spacewire The Spacewire directly transmits a linked list of packet when the address of the first descriptor is provided Packet size Data Address Next Descriptor Packet size Data Address Next Descriptor Packet size Data Address 0 Packet Data Packet Data Packet Data programmable Bus <strong>Controller</strong> … The spacewire handles 2 programmable buffer areas in the memory and switch automatically between them CPU Memory StartArea1 EndPacketArea1 EndArea1 Area 1 Page 8 Microelectronics Presentation Days. 4 and 5 of February 2004 StartArea2 EndPacketArea2 EndArea2 Area 2
Building Blocks For System on a Chip – <strong>Spacecraft</strong> <strong>Controller</strong> on a Chip IP Core synchronisation Most of IP core can receive or distribute synchronisation signals : spacewire, PTME, 1553, CTM … Modular time distribution implemented to adapt the SCoC to specific system requirements Spacewire 2 Spacewire 1 Spacewire 3 1553 BC/BM/ RT Switch Matrix PTME External Pulses PTCD Page 9 Microelectronics Presentation Days. 4 and 5 of February 2004 CTM
Page 1 and 2: PIO/TEST/WDOGN/ 19 ERRORN 2 Clock,
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Spacecraft Controller on a Chip - Microelectronics - ESA

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