Slides - Microelectronics - ESA

ESTEC 

Spacecraft Controller On a Chip with LEON3-FT 

(SCOC3) 

Franck Koebel

ASTRIUM SAS 

Agenda 

• SCOC1 to SCOC3 

• SCOC3 architecture brief presentation 

• Development status 

• Follow-up activities 

• Conclusion 

2 

SCOC3 – MPSA Round Table – Noordwijk 4 November 2009 

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed.

ASTRIUM SAS 

SCOC3 heritage 

This document is the property of Astrium. It shall not be communicated to third parties without prior written agreement. Its content shall not be disclosed. 

• EADS ASTRIUM has been working on SoC for the last ten years: 

• SCOC3 has an heritage based on SCOC1 which was a study made with 

ESA funding. 

• SCOC3 benefits also of SCOC2 which was an internal EADS ASTRIUM 

study to continue the previous one. 

• These studies showed several key points like internal bus arbitration, 

I/O interfaces traffic and memory bandwidth. 

• SCOC3 was developed by EADS ASTRIUM under ESA contract 

supported by CNES and by EADS ASTRIUM internal funding. 

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SCOC3 – MPSA Round Table – Noordwijk 4 November 2009

ASTRIUM SAS 

Some SCOC3 features 


• SCOC3 is a System-On-Chip for Spacecraft Control and Data 

Handling, featuring: 

• The LEON3-FT processor with GRFPU-FT, 

• CCSDS TM/TC interfaces, 

• Various on-board interfaces (RMAP Spacewire, CAN, 1553, UART), 

• Time management and Event routing. 

• Internal communication is distributed over a double AMBA-AHB 

buses structure with separate external IO and processor memory 

ports. The two buses are linked by inter-bus bridges. 

• SCOC3 integrates functions which were before on several 

ASICs. It is very attractive : small size in a qualified BGA 

package, low power consumption and rad-tolerant technology. 

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ASTRIUM SAS 

SCOC3 architecture 

CPU MEMORY 

3 3 3 

17 48 


TMCLCWCLK 

TMCLCWSAMP 

TMCLCWD 

TMTIMESTRO 

TMIQCLK 

TMIOUT 

TMQOUT 

TMUECLK 

TMUEOUT 

SPWINTTXDO 

SPWINTTXSO 

SPWINTTXSI 

SPWINTTXDI 

SPWINTRXDO 

SPWINTRXSO 

SPWINTRXSI 

SPWINTRXDI 

SPWXSTRDO 

SPWXSTRSO 

SPWXSTRSI 

SPWXSTRDI 

SPWUSTMDO 

SPWUSTMSO 

SPWUSTMSI 

SPWUSTMDI 

8 

OnChip 

MemTM 

SCOC3 

PTME 

SpW 

IntTX 

SpW 

IntRX 

SpW 

XStrping 

SpW 

UserTM 

HKPF 

JTAG & 

SCAN 

S 

S 

M 

S 

M 

S 

M 

S 

M 

S 

CPU function 

TM/TC function 

S 

TCDD 

TMTC APB 

DMATM 

M 

SCOC3 

Ccsds 

TimeMng 

2 

8 

S 

S 

IO functionalities 

General 

S 

Switch 

Matrix 

M 

2 

S 

StatsBuffer 

IP Monitor 

MISC 

OnChip 

MemTC 

M 

APBR 

TMTC 

S 

TraceBuffer 

S 

S 

TCR 

& CONF 

S 

M 

IO APB 

Clock & 

Reset 

SpW 

IPL 

M 

S 

CPU AHB 

STATUS 

S 

FP 

CTL 

Main clock/Other clock interface 

APBR 

CPU 

S S M 

S 

S 

UART 

GP1 

M 

M 

M 

HADMA 

SpW 

SIF 

V 

IO AHB BUS (arbiter, decoder) 

APBR 

IO 

M 

S 

S 

S 

S 

S 

IO AHB 

STATUS 

S 

UART 

GP2 

SpW 

SIF 

O 

S 

S 

AHBR 

M 

M 

SpW 

IO 

LEON3/ 

GRFPU 

Inst/Data Cache 

S 

S 

M 

Timers 

CAN 

AV 

2 

CPU APB 

S 

M S 

BC 

RT53 

AV 

CAN/1553 IF 

DSU 

Inst TraceBuffer 

AHBTraceBuffer 

CPU AHB BUS (arbiter, decoder) 

IO Count: 342 

Gates Count: 

1800 kgates 

S 

Fst IRQ S 

controller 

S 

2nd IRQ 

controller 

2 2 2 2 

S 

CAN 

PL 

M S 

BC 

RT53 

PL 

CAN/1553 IF 

CPU MCTL (SRAM, 

SDRAM) 

2 2 2 

S 

S 

S 

M 

S 

S 

S 

S 8 

GPIOs 

UART 

1 

UART 

DSU 

IO MCTL 

(SRAM, 

SDRAM, 

PROMs) 

18 

48 

11 

6 

3 

6 

2 

3 

GPIO 

TXUA1 

RXUA1 

TXUA2 

RXUA2 

IOADD 

IODATA 

IOCS_N 

IORASRAMCS1_N 

IOCASRAMOE_N 

IOWERAMCS2_N 

IODQMADD18 

IOSDRCLK 

IOCKE1_2 

IOCKE3_4 

IOCKE5_6 

IOCKE7_8 

IOCKE0_9 

IORAMWE_N 

IOCS0RAMCS0_N 

IOCS1RAMCS3_N 

IOSGMPCS_N 

IOATCPCS_N 

IOSWPCS_N 

IOBPCS_N 

IOPROMOE_N 

IOPROMWE_N 

IOPROMDIR 

IOAREACS_N 

IOSWPEN 

IOBPEN 

IOATCPEN 

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ASTRIUM SAS 

A dual AHB bus architecture 


• Latency and data throughput performances on-chip data transfer 

are achieved with a system of two cross-coupled AHB buses (CPU 

AHB and IO AHB) => 

• Reduced number of bus agents on each bus, 

• Improves timing (maximum clock frequency), 

• Allows operating both buses at a different clock frequency, 

• Dual external IO and processor memory ports to keep maximum 

performance of the processor 

• Any master on the CPU AHB bus can access to the APB busses as 

Master. It is then possible to control the SCOC3 through the UART 

DSU interface. 

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ASTRIUM SAS 

TM/TC interfaces integration 

• One of the main key points of SCOC3 is the integration of the 

complete CCSDS TM and TC protocols and interfaces. 


• TCDD (Packet Telecommand Decoder) 

• Provides all functionalities of the TC system 

• A local memory permits to deal with authentication 

• STME (SCOC3 Packet Telemetry Encoder) 

• Provides all functionalities of the ground telemetry system (PTME), 

• The functionalities have been wrapped into a single module including 

an internal memory buffer. 

• SCOC3 may work as a powerful processor with the most 

needed peripherals including CCSDS TM/TC or as a whole 

CCSDS TM/TC chip. 

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ASTRIUM SAS 

Development status and commercialisation 


• Status: 

• SCOC3 is manufactured by ATMEL. Prototypes were received in May 

2009. 

• After a very thorough and important hardware, software and system 

validation, the prototype approval was signed on 27 October 2009 

confirming that the first ASIC run was the successful run 

• SCOC3 chipset is fully characterised and ready in due course for 

EADS ASTRIUM projects (ASTROTERRA, SEOSAT computers) and 

also for any platform computers projects. 

• Commercialisation: 

• SCOC3 chipset will soon be commercially released. 

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ASTRIUM SAS 

Choice of package 


• The SCOC3 ASIC is proposed as baseline with current ATMEL 

CCGA472 package, built with NTK interposer (SCI) 

• Two quality flow are proposed : QML Q & QML V 

• As an alternative to the SCI NTK interposer used with current 

ATMEL CCGA package, the SCOC3 could be also procured at LGA 

package 

• Hermetic package delivered with no column 

• Same quality level available : QML Q or QML V 

• This alternative is under analysis at ASTRIUM, and would allow to 

assemble LGA with different columns as NTK ones. 

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ASTRIUM SAS 

SCOC3 gate level characteristics 

• SCOC3 matrix: ATC18RHA95_504D (pad limited choice) 


• Matrix size: 13x13=169 mm² 

• Chip size area in the matrix (pads, logic, hard blocks): 57.7 mm² 

• Number of logic gates: 1.8 Mgates 

• Number of DFFs: 55000 

• Number of memory bits: 2.2 Mbits equivalent to 1.8 Mgates 

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ASTRIUM SAS 

Follow up activities (1) 


• Subject to signature of a new ESA contract, SCOC3 will be 

established as an Application Specific Standard Product 

available to all users in the ESA member and participating 

states, and the following SW tool roadmap will be developed. 

• The software activity will consist in developing: 

• A hardware software interface layer which is independent of the real 

time operating system. 

• A board support package adapted to operating system RTEMS 

• Driver software functions which allow the use of main input output 

peripherals. 

• Interface test applications which will be delivered with the provided 

board. 

• A software environment development and RTEMS operating system 

associated tools. 

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ASTRIUM SAS 

Follow up activities (2) 

• A development environment for SCOC3 will be provided to 

standardize the code production tools. 


• The main part of the environment integrates the tools used for the 

development of flight software (C compiler and RTEMS OS). 

• SCOC3 technical support definition will also be addressed in 

these follow up activities. 

• It will be necessary to perform radiation tests according to a 

Radiation test plan which is being prepared. 

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ASTRIUM SAS 

Customer complementary needs opportunities 


• SCOC3 chipset may be sold with a SCOC3 simulator under 

licensing for customer requiring software development in parallel 

with a board. 

• Although negotiation is running, a low cost starter kit based on 

SCOC3 implementation in a XILINX should be available for 

software and systems developments. This starter kit will be funded 

by CNES. 

• Current developed software run under RTEMS OS. 

Other OS might be available depending on funding and needs: 

• eCos 

• VxWorks up to 6.5 

• Linux, ThreadX, Nucleus… 

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ASTRIUM SAS 

Conclusion 


• EADS ASTRIUM has designed, manufactured and tested a high 

performance new computer product based on SCOC3 chipset: 

• Identified applications are both observation satellites with class 2 EEE 

quality level (ASTROTERRA, SEOSAT, …) or with class 1 EEE parts 

(Geostationary Telecom) 

• The first Prototype Flight Models of the SCOC3 on-board 

computer will be delivered by end 2010. 

14

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