Mathcad - ee217projtodonew2.mcd

'HVLJQDQG$QDO\VLVRID 

*+]/RZ1RLVH$PSOILHUÃ 

by 

John Wetherell 

and 

Burcin Baytekin 

EE217 Project 

June 14th 1999

Table of Contents 

Section 

Page 

I. Introduction 2 

II. Emitter Degeneration Sizing 3 

III. Input Parameters 4 

IV. Process Parameters 5 

V. Architecture Selection 6 

VI. Small Signal Analysis 7 

VII. Scattering Parameter Analysis 8 

VIII. Stability Analysis 9 

IX. Ballast Resistor Sizing 10 

X. Simultaneous Conjugate Matching Analysis 11 

XI. Noise Analysis 12 

XII. Equivalent Input Noise Elements 13 

XIII. Noise Correlation 14 

XIV. Optimal Source Impedance to Trade of Noise and Power 15 

XV. Gain Analysis 16 

XVI. Distortion Analysis 17 

XVII. LNA Figures of Merit 18 

XVIII. Optimization 19 

XIX. Package Deibedding 20 

XX. Impedance Matching 21 

XXI. Simulation Procedure 22 

XXII. Simulation Results 23 

XXIII. Comparison of Simulation and Calculation Results 24 

XXIV. Conclusions 25 

XXV. References 26

Introduction 

Low noise amplifiers are useful for a variety of applications, where small signals are received. 

This report is written specifically for the application in a IS-95B cellular telephone handset. The 

routines developed to design an analyze the amplifier are organized in a way so that the design 

process is completely automated after entry of the process parameters and high level system 

specifications. Also the procedure is general purpose that keyu equations can be replaced so the 

routine is suitable for other configurations and devices, such as GaAs and MOSFETs. After the 

Mathcad automated design is complete, the results are used as a starting point for simulations on 

a commercial simulation tool. The graphs of performance parameters as a function of device size 

and current serve as a guideline for the iterations of simulations. The final simulated results for 

amplifier are summarized and conclusions are made. 

The low noise amplifier designed for this project is part of a larger project. The specifications 

for the amplifier were developed for use in the handset of a 1900MHz CDMA cellular telephone. 

The actual specifications involve trade-offs with blocks which occur later in the receiver chain. A 

collection of more than 16 impedance matching routines were also developed in previous project 

unrelated to the system analysis. These collection of routines are easily available on the 

following website: http://www.eecs.berkeley.edu/~wetherel/rftoolbox/matcher.html. The 

system analysis and the impedance matching network design routines were used as a 

foundation for the automated low noise amplifier design tool. 

An interesting comment on the report for this project is that it is written entirely in Mathcad, a 

tool for simultaneuous word processing and mathematics computation. This combination of 

features makes the report a "living" document. With a few clicks the reader can modify the LNA 

design for his/her specific system and process specifications. In a world where processes 

change every few years and new specifications are needed just as often the design automation of 

LNAs is a very useful feature. The use of Mathcad also allowed the rapid entering of design 

equations from available books on radio frequency circuit design. These equations include those 

for simultaneous conjugate impedance matching [ ] and distortion analysis of common-emitter 

amplifiers [ ].

a 

es[] 

Emitter Degeneration Sizing 

It is known that inductive emitter degeneration is an effective method of making the optimal 

source impedance for minimum noise figure (noise match) close to the optimal source 

impedance for conjugate matching (power gain match). Increasing emitter inductance does this 

by increasing the input impedance, but with little effect on the noise match. Also on the positive 

side, inductive emitter degeneration also helps to linearize the device and improve high 

frequency stability. On the minus side emitter degeneration reduces the gain of the amplifier. 

Similarly, for a device with fixed lower limit for emitter degeneration, the device size may be 

changed match the noise and power source impedances. If the required device size to provide 

simultaneous match is too large, which is indicated by low gain, more inductance can be added 

to the emitter to provide the simultaneous match. If the device becomes too small to meet noise 

requirements, a simultaneous match cannot be acheived. For a given noise figure goal, an 

upper limit is set on emitter degeneration to acheive a simultaneous power and noise match. 

This upper limit is very frequently exceeded, as is in the case of this design, so a method has 

been developed to trade off the noise and power matches to find the optimal source impedance 

for the transistor. 

For all fabricated devices, there is some inherent inductance in the emitter of the transistor 

from the bonding wire which connects the emitter to the pin and the outside of the chip. The 

value of this inductance is in the range of 0.4nH to 4nH, with a carefully-designed typical value of 

around 2.2nH. For the following design a low inductance ball grid array package is assumed 

with an inductance of 1.5nH. 

Project To Do List 

Units and Constants 

Input Parameters 

The following list contains the input parameters used to optimize the amplifier. The 

optimization routine uses these values of intercept point, noise figure, and current as constraints. 

Ideally the optimal LNA design would ask the user enter in the backend noise figure and intercept 

point. The routine would then design the LNA for maximum output C/(N+I) (carrier to noise plus 

interference ratio). This is equivalent to maximizing SNDR (signal to noise plus distortion ratio) 

for the system. The derivation of C/(N+I) has not been completed so the input parameters are 

determined from the following system needs:

∆f: The frequency spacing of the undesired signals from the desired signals. This is used for 

distortion calculations. 

S11: The maximum desired S11 is determined by the external filter connected to the LNA. 

This external filter relies on the low noise amplifier to have a certain impedance to provide given 

filtering characteristics. 

Gain: The minimum and maxmium desired gain constraints are set by the noise of the 

system behind the amplifier. 

V DD : The supply voltage is set by the end-of life voltage of three Lithium Ion AA batteries 

plus some loss for a voltage regulator. Normally they are 1.5V each, which corresponds to a 

normal operating voltage of 4.5V. At end of life they are 1V each, which corresponds to a 3V 

supply. The voltage regulator output can vary up to 10%, which gives a minimum supply voltage 

of 2.7V. 

Temp: The normal operating temperature of the device is a room temperature of 27C plus 

some die heating of 15C to due nonideal heat sinking. The actual operating temperature in a 

worst case environment may vary between -30C and 105C, but was not added to the design 

routine, because of time constraints. 

Z bias : The bias impedance is chosen by the practical size limitation of an on-chip inductor to 

be used as a bias choke. A 50nH inductor is assumed with a Q of 3 at 1.9 GHz. 

K Factor: The desired minimum K factor is somewhat of a guess. In order to simultaneously 

conjugate match the input and output ports of the device, the K factor must be greater than one. 

If the K factor is set equal to one the real part of the conjugate matching impedance of the source 

becomes zero ohms, which is infeasible. For this reason the K factor is set to a value somewhat 

larger than one. Although the value was chosen with an educated guess, a real practical value 

for K can be calculated by setting a lower limit to the input impedance or an upper limit to the 

input matching network, and using it to solve for the K. 

NF: The noise figure is determined by the value of the received signal when the cellular 

phone is operated at it’s farthest distance from the base station. Here the noise level of the 

receiver must be a significant value below the small desired signal. 

IP 3 : The third order intercept point is a measure of the low noise amplifiers ability to reject 

unwanted signals, such as another cellular phone. When the cellular phone is being used at it’s 

greatest distance from base station the phone must be able distinguish the desired signal from 

another cellular phone. 

∆f 10 MHz Jammer Frequency Spacing 

f 1900 MHz ω 2. π . f s j. ω 

Frequency of Desired Signal 

S 11goaldB 15 dB Input Match Requirement 

IP 3goaldBm 10 dBm 3rd Order Intercept Point Requirement 

G goaldB 13.5 dB G min 12 dB G max 15 dB Available Power Gain Requirement 

Z bias 100 Ω j2 . . π . f 50 

. nH Bias Impedance 

K val 1.1 Desired In-band Stability Factor 

V DD 2.7 V Supply Voltage 

Temp 300 K Operating Temperature 

N 40 Number of Devices in Parallel 

10. mA 

Bias Current 

I C 

The optimizer will find the best value for current and area. The entered values are used for 

function testing purposes and graphing. 

C/(N+I) Optimization Inputs

Process Description 

The process used to simulate the amplifier is a 0.5 µm Silicon Germanium BiCMOS process. 

The following process parameters are measured for a single bipolar transistor, whose emitter size 

measures 5µm by 2.5µm. Although this device size is suitable for prescalers and low frequency 

operations, larger devices are better suited for low noise amplifiers. Increasing the device size 

has the beneficial effect of reducing the base resistance, and thus the input referred thermal 

noise of the amplifier. Increasing the device size has the detrimental effect of reducing the gain, 

increasing the input referred current noise. A more detailed discussion of these effects is given 

later. 

Other process parameters 

I S 

C µ0 

2.2 . 10 18 A 

3.41 fF 

Reverse Saturation Current of 

Base Emitter Diode 

. V jc 0.386 V m jc 0.11 x jc 0.82872 Collector Emitter Capacitance Parameters 

C cs0 6.47. fF V js 0.34 V m js 0.178 Collector Substrate Capacitance 

Parameters 

V A 71.87 V Forward Early Voltage 

β 0 146.15 DC Beta 

τ F 

2.15. pS 

Base Transit Time 

r b0 177.66 ohm R e0 11.71 ohm R c0 75.42 ohm Base, Collector, and Emitter Resistances 

C je0 

10.82 . fF V je 1.48 V m je 0.679 Base Emitter Capacitance Parameters 

Scaling Model Parameters with Device Size 

The small signal model used for the transistor is a relatively simple model. The resistances 

and capacitances of the transistor are assumed to scale linearly with the area of the emitter. The 

resistances are reduced by a factor of N as the device size increases, and the capacitances are 

increased by N as the device size increase. In reality, for small devices the base resistance 

stays relatively constant with device size, because of the added resistance and capacitance 

associated the contacts. In most practical LNA’s large devices are used so linear scaling is a 

good assumption. 

Small-signal parameters

Architecture Selection 

Amplifier Evolution 

The simplest versions of common emitter and common base amplifiers are shown in the 

following figure. They are essentially the same amplifier with the ground connection placed on 

the emitter and the base respectively. The distortion output power of these two amplifiers is 

identical, but the concept of input referred distortion and noise power is invalid, because the 

source impedance is zero ohms. 

I out 

I out 

V S 

V S 

Fig. 1: Unmatched Undegenerated Common Emitter and Common Base LNA 

All real amplifier have some value for source impedance. For high frequency amplifiers, this 

impedance is typically provided by a low loss matching network to a 50 ohm input. The value of 

the source impedance seen by the amplifier is usually somewhere between the optimal value for 

minimum noise and maximum gain. For a typical common emitter amplifier with good 

performance, the desired source impedance is close to 50 ohms. For a common base amplifier 

the desired source impedance is much smaller than 50 ohms. The large impedance difference 

of a common base amplifier from 50ohms requires a high-Q matching network. High Q matching 

networks usually have narrower bandwidths, more in-band loss, and are more sensitivity to 

process variations. This will degrade the performance of the common base amplifier. The 

distortion performance of the matched undegenerated common emitter and common base are 

similar. 

I out 

I out 

Z S 

V S 

V S 

Z S 

Fig. 2: Matched Undegenerated Common Emitter and Common Base LNA 

Usually the distortion and stability performance of a undegenerated amplifier is very poor, so 

it is desirable to place local or global feedback around the amplifier to improve it’s performance. 

For a bipolar amplifer, this is easily done with some inductance in the emitter of the amplifier. 

This inductance also helps to make the optimal source impedance for minimum noise figure 

closer to the conjugate match source impedance. For a common-base it is much more difficult to 

linearize the amplifier, because impedances in the base have little effect on the amplifier 

distortion. Furthermore, inductances in the base tend to destabilize the amplifier. Incidentally, 

inductance in the base is an common effective way to build an oscillator, such as the Colplitt’s 

oscillator. Our goal here is to build an amplifier, not an oscillator, so inductance in the base is 

undesirable.

undesirable. 

Common Emitter Amplifier 

For the reasons of stability, low distortion, low noise, and input matching described above, 

an inductively degenerated common emitter configuration was chosen for the input stage of the 

amplifier design. The circuit is shown in the following figure. A simplified equation for the 

intercept point is given in the following equation [2]. 

I out 

Z S 

V S 

L e 

Fig. 3: Matched Degenerated Common Emitter LNA 

IP 3ce 10 

10 log 

8I . 4. Cce ω 4 . 4 

L e . 1 

2 

V T 

I . C τ F 

V . T C . je0 Area 

2 

. Intercept Point of a Common-Emitter LNA 

Now that the first stage of the amplifier is chosen, we still have the architectural choice of 

adding a common base configuration (the cascode) to the output of the common emitter (the 

driver) configuration. This configuration is also known as a cascode configuration. The cascode 

configuration has the increased gain and reverse isolation advantages of all cascaded amplifiers. 

Unfortunately it also has the reduced dynamic range disadvantage of cascaded amplifiers from 

increased distortion and increased noise. 

When the cascode configuration is compared against two cascaded common emitter 

amplifiers, we see the performance is much worse. This is because first the common emitter is 

not matched to the common base and second because the second common base stage is not 

degenerated resulting in higher distortion. This disadvantage is reduced at lower frequencies as 

will be discussed below. If a primary goal of the amplifier was low noise and high gain it is 

possible to increase the performance of the amplifier with an impedance matching circuit 

between the common emitter and common base transistors. Unfortunately, this has the 

undesirable effect of reducing input referred distortion. This distortion increase comes from two 

different mechanisms. The first mechanism is from the increased swing at the emitter of the 

cascode transistor, which increases the distortion in the cascode transistor. The second 

mechanism comes from saturating the collector of first stage amplifier. The second mechanism 

can be alieviated with a higher bias for the base of the cascode transistor. In general the 

distortion of the cascode configuration is pretty bad without matching so it is undesirable to 

match the cascode and driver. 

An important advantage of the cascode configuration is it’s simplicity and it’s inherent bias 

current sharing, which shows up in cost and area comparisons. Ultimately the system requirements 

will justify one amplifier over another.

Common Base Amplifier 

To find the distortion of the cascode configuration we analyze the distortion due to the driver 

transistor and the cascode transistor separately. To find the distortion of the common base 

amplifier, we input-refer the distortion through an linear inductively degenerated transconductor. 

The result of the distortion from this configuration is given in the following equation. 

I out 

V S 

Z S 

V π 

g m* 

V π 

L e 

IP 3cb 10 

10 log 

Fig. 4: Common-base LNA (input-referred through ideal transconductor) 

4I . 3. Ccb ω . 2 

L e 

C . je0 Area . cb V T 

. Intercept Point of Common-Base LNA 

Now the distortion due to the common-emitter device can be compared to the distortion from the 

common base device in a cascode configuration. The following equation is result of taking the 

difference between the intercept point. From this difference equation we can see the common 

base is the dominant source of distortion at high frequencies and for large emitter degeneration. 

For typical values L e =1.5nH, I C =6mA, f=1.9GHz, f T =20GHz, the common emitter is 5.4dB more 

linear than the input referred common base. Which reduces the overall distortion of the cascode 

amplifier to 6.5dB below that of the common emitter alone. 

Intercept Point Difference between 

IP 3ce IP 3cb 3dB 20logg . . m ω . L e 10. 

log ω 

Common Base and Common Emitter 

Cascode LNA 

ω T 

V S 

Z S 

I out 

L e 

Fig. 5: Cascode LNA 

IP 3ce IP 3cb 

10 10 

IP 3cascode 10. log 10 10 IP 3ce 10. 

log 1 10 

∆IP 3ce_cb 

10 

Intercept Point of a Cascode LNA

Small Signal Analysis 

A small signal analysis of the network is necessary for noise, gain, and impedance matching 

calculations. Kirkoff’s Current Laws (KCL) were used to set up a general purpose matrix to solve 

for the necessary gains. The following figure was used perform the small signal analysis. 

C µ 

Z S 

r b 

i bn I cn R L 

V S 

Z π 

g m *v π 

Z bias 

Z L 

v nRbias 

Z e 

v nRL 

Fig. 6: Small Signal Model of LNA Circuit 

KCL at bias node, V bias 

V S 

V bias V bias V nbias V bias V b 

Z S Z bias r b 

V S 

Z S 

V bias 

Z S 

V bias V bias V b 

Z bias r b 

KCL at base node, V b 

V bias V b 

V b V . c j. ω . C µ 

r b 

KCL at collector node, V c 

V b V . c j. ω . C µ g . m V b V e 

V b V e 

V b 

0 

Z π 

V c 

r o 

V e 

V c 

R L 

V c V L 

Z L 

V bias 

V b V . c j. ω . C µ 

r b 

V . c j. ω . C cs 

V b 

Z π 

V e 

V L 

V c V . b j. ω . C µ g . m V b V e 

Z L 

V c 

r o 

V e 

V c 

R L 

V c 

Z L 

V . c j. ω . C cs 

KCL at emitter node, V e 

V b V e 

g . m V b V e 

Z π 

V c 

r o 

V e 

V e 

Z e 

0 

These KCL equations are now placed into a KCL matrix 

V S 

Z S 

0 

V L 

Z L 

0 

1 1 1 


1 

r b 

0 

0 

V e V e V b 

g . m V e V b 

Z e Z π 

1 

0 

0 

r b 

1 

j. ω . 1 

C µ 

j. ω . 

1 

C µ 

r b 

Z π 

Z π 

j. ω . C µ g m j. ω . 1 1 

1 

C µ 

g m 

Z L r o 

r o 

1 

1 1 1 1 

g m g m 

Z π r o Z e Z π r o 

Note that these equations don’t have R L in them. The necessary R L will be calculated later in the 

stability section. 

. 

V bias 

V b 

V c 

V e 

V e 

r o 

V c

KCL N, I C 

, s, Z S 

, Z L 

1 1 1 


1 

r b 

0 

0 

1 

0 

0 

r b 

1 

j. ω . 1 

C µ 

j. ω . 

1 

C µ 

r b 

Z π 

Z π 

j. ω . C µ g m j. ω . 1 1 

1 

C µ 

g m 

Z L 

r o 

r o 

1 

1 1 1 1 

g m g m 


KCLinv N, I C , s, Z S , Z L KCL N, I C , s, Z S , Z L 

1 

2 

V bias 

V b 

V c 

V e 

KCLinv N, I C , s, 50 ohm, 

50 ohm 

. 

50 ohm 

0 

ohm 

0 

ohm 

0 

ohm 

V bias 1.537 0.038i 

V e 

1.467 0.242i 

V b 1.498 0.03i 

= 

V c 0.129 4.151i 

Scattering Parameter Analysis 

Scattering-parameters are the most widely used representation of RF small signal networks. 

Their advantages stem from their ease of use for power gain and reflection calculations, and 

serve as standard output parameters from network analyzers. S parameter values can be 

calculated for a small signal network using a variety of procedures including calculating other 

parameters and converting to S parameters, but the following method is chosen for it’s simplicity. 

The S parameters are referenced to 50 ohms, because it a common value used in test 

equipment, passive components, such as filters and antennas, and commercially available active 

components, such as amplifiers and mixers.

2V 

50 Ω 

1V 

1 GΩ 

S 21 

Circuit 

S 11 

50 Ω 

S 12 

50 Ω 

50 Ω 

Circuit 

1V 

2V 

S 22 

1 GΩ 

Fig. 7: Circuit used for scattering parameter calculations 

2 

50 ohm 

0 

Sparam N, I C , s V KCLinv N, I C , s, 50 ohm, 

50 ohm . 

ohm 

0 

ohm 

0 

ohm 

S 11 , 

V 1 

1 

S 21 , 

V 3 

V 

KCLinv N, I C , s, 50 ohm, 

50 ohm 

S 22 , 

V 3 

1 

S 12 , 

V 1 

S 

. 

0 

ohm 

0 

ohm 

2 

50 ohm 

0 

ohm 

Sparam N, I C , s 

= 

0.537 0.038i 

0.129 4.151i 

0.015 0.098i 

0.648 0.278i

100 

10 

1 

0.1 

0.01 

0.01 0.1 1 10 100 

| S11 | 

| S21 | 

| S12 | 

| S22 | 

Fig. 8: S Parameters vs. Frequency 

Stability Analysis 

Often it happens a designer designs an amplifier, but he gets an oscillator in return. This 

scenario typically occurs at frequencies out of the desired band, where the source and load 

impedances can be unknown. If the out of band source and load impedances are unknown it is 

desirable to make the amplifier stable for all source and load impedances. This is known as an 

unconditionaly stable amplifier. If the out-of-band source and load impedances are known it is 

possible to design a conditionally stable amplifier design. Usually conditionally stable amplifiers 

can acheive higher performance levels than unconditionally stable amplifiers. This is becuase 

the amplifier performance must be degraded some with form of ballasting resistor to make it 

stable. 

It is desirable to make the stability factor greater than one for another reason other than 

stability. With a K factor greater than one it is possible to simultaneously conjugate match the 

input and output impedance of the amplifier. Conjugate matches are desirable, because the 

filters connected to the amplifier require a conjugate impedance to provide their specified 

frequency response. 

For a K factor of one, the real part of the matching impedances is zero ohms, so it is 

impossible to match with practical matching networks. For this same reason it is desirable to 

make the K factor some value significantly larger than one. 

KS ( ) ∆ S . 

1, 1 

S 22 , 

S . 

12 

, 

S 2, 

1 

1 ( ∆ ) 2 2 

S 1, 1 

2. S . 

1, 

2 

S 21 , 

2 

S 2, 2 

K Sparam N, I C , s = 1.016 

The mu factor is often a more desirable parameter to use for stability than K factor. This is 

because the K factor must be specified with other conditions, such as ∆. In this sense the µ 

factor is easier to use, because it does not require any other parameters to guarantee 

unconditional stability. Although the K factor and µ factor curves are different, their values are 

equal for the transition point between unconditionally stable and conditionally stable regions 

(K=µ=1). µ S 

. 

, , s = 1.102 

( ) ∆ S . 

1, 1 

S 22 , 

S 12 

S 1 1 

, 

S 2, 

1 

2 

1 S 22 , 

, 

∆ . S 2, 

2 

S . 

2 1 

, 

S 12 , 

µ Sparam N I C

10 

1 

K, Mu 

0.1 

0.01 

0.01 0.1 1 10 100 

K Factor 

mu Factor 

Desired Stability Factor 

Frequency 

Fig. 9: K Stability Factor vs. Frequency 

1.15 

1 

K, Mu 

1.1 

K, Mu 

0.8 

1.05 

0.6 

1 

0 20 40 60 80 100 

0.4 

0 5 10 15 20 

Number of Device in Parallel 

K Factor 

Mu Factor 


Bias Current (mA) 

K Factor 

Mu Factor 


Fig. 10: K Factor vs. Device Size 

Fig. 11: K Factor vs. Bias Current

Ballast Resistor Sizing 

The term ballast is of Swedish origin, where bal means " to bear," and llast means "load." 

Thus the term ballast means to bear the load. The load refers to a heavy weight placed at the 

bottom of ship to stabilize the ship in heavy waves. The term ballast is used here to describe a 

resistor, which is added to the circuit to provide stability. Most transistors given by a 

manufacturer are only conditionally stable. For this reason, and the reasons described above a 

ballast resistor is added to stabilize the transistor 

The following procedure is used to find the ballast resistor needed to make the amplifier 

unconditionally stable, or to provide the desired K factor. First, the procedure involves 

converting a given set of S parameters to ABCD parameters and multiplying them with the S 

parameters of a parallel resistor. Then the combination ABCD parameters are converted back 

into a new set of S parameters, which are used to find the K factor for the device. The value of 

resistance is swept to find the value need to meet a desired value of K factor. 

ABCD Parameters of a Parallel Resistor 

ABCD( R) 

1 

ohm 

R 

0 

1 

S to ABCD Parameter Calculation 

S2ABCD S, 

Z 0 

Note: The units are removed, for calculation purposes only 

1 S . 

1, 1 

1 S 22 , 

S . 

12 

. 

2S 2, 

1 

, 

S 2, 

1 

ohm 1 S . 

1, 1 

1 S 22 , 

S . 

. 

12 

Z . 

0 

2S 21 , 

, 

S 21 , 

Z 0 1 S . 

1, 1 

1 S 22 , 

S . 

. 

12 

ohm 

. 

2S 21 , 

1 S . 

1, 1 

1 S 22 , 

S . 

12 

. 

2S 2, 

1 

, 

S 21 , 

, 

S 2, 

1 

S2ABCD Sparam N, I C , s , 50 ohm 

= 

0.063 0.013i 

1.39. 10 4 1.384i . 10 3 

2.099 17.814i 

0.013 0.042i 

ABCD to S Parameter Calculation 

ABCD2S ABCD, Z 0 A ABCD 11 , 

B ABCD 12 , 

C ABCD 21 , 

A 

D ABCD 22 , 

1 

B . ohm 

Z 0 

Z 0 

C. D 

ohm 

. 

A 

B . ohm C. Z 0 

D 

Z 0 ohm 

2 

A 

2.( A. D BC . ) 

B . ohm 

Z 0 

Z 0 

C. D 

ohm 

ABCD2S S2ABCD Sparam N, I C , s , 50 ohm , 50 ohm 

= 

0.537 0.038i 

0.129 4.151i 

1 0 

KwithR( S, 

R) K ABCD2S S2ABCD( S, 

50 ohm) 

. ohm , 

1 

50 ohm 

R 

0.015 0.098i 

0.648 0.278i 

K Factor with Load Resistor 

KwithR Sparam N , I C , s , 1000 ohm = 1.082

1 0 

µwithR( S, 

R) µ ABCD2S S2ABCD( S, 

50 ohm) 

. ohm , 

1 

50 ohm 

R 

µwithR Sparam N , I C 

, s , 1000 ohm = 1.248 

µ Factor with Load Resistor 

1.3 

K and Mu Factor 

1.2 

1.1 

1 

100 1 .10 3 1 .10 4 

Ballast Resistance (kohm) 

K Factor 

Mu Factor 

Desired K Factor 

Fig. 12: K and Mu vs. Ballast Resistor 

Rguess 

0.1 kΩ 

Rneeded N , I C , s, Kval if K Sparam N, I C , s > Kval, 100 kΩ, 

root KwithR Sparam N, I C , s , Rguess Kval, 

Rguess 

Rneeded2 N , I C , s, Kval if µ Sparam N , I C , s > Kval, 100 kΩ, 

root µwithR Sparam N, I C , s , Rguess Kval, 

Rguess 

Rneeded2 N , I C , s, K val = 100 kΩ 

R L N, I C , s Rneeded N, I C , s, K val R L N, I C , s = 773.703 ohm 

It is interesting to plot the ballast resistor needed vs. the device size and current. These 

curves are shown in the following figures. From these plots we see the stability of the device 

increases with bias current and decreases with device size. Conversely we see we need a 

smaller parallel ballast resistor for more potentially unstable devices. Thus a smaller ballast 

resistor is needed for larger devices and devices with smaller currents. 

1 .10 6 Ballast Resistor Need to make K=Kval 

Ballast Resistor Size (ohms) 

1 .10 5 

1 .10 4 

1 .10 3 

100 

1 10 100 

Number of Devices in Parallel 

Ballast Resistor Need to make mu=Kval 

Fig 13: Ballast Resistor vs. Device Size

2000 

Ballast Resistor (ohms) 

1500 

1000 

500 

0 

0 5 10 15 20 

Resistance Needed w/ 25 Devices 




Fig. 14: Ballast Resistor vs Current 

Simultaneous Conjugate Matching Analysis 

It is desirable from a gain perspective to simultaneously conjugate the input and output of the 

amplifier. This maximizes gain, but may not be optimal for noise as we shall see later. If the 

device is unilateral (i.e. the reverse isolation, S12, is zero) the conjugate matching impedances 

can be calculated directly from S11 and S22. In reality S12 is some non-zero value, so matching 

the input will change the impedance at the output. Simultaneous matching can be done 

iteratively, which can be tedious and time consuming. An easier method involves solving a 

second order equation for the desired values. The derivation of Zpopt is done in [4]. To use the 

equation the S-Parameters must first be recalculated with the necessary ballast resistor. 

KCL N, I C , s, Z S , Z L 

1 1 1 


1 

r b 

0 

0 

1 

0 

0 

r b 

1 

j. ω . 1 

C µ 

j. ω . 

1 

C µ 

r b 

Z π 

Z π 

j. ω . C µ g m j. ω . 1 1 1 

1 

C µ 

g m 

R L Z L r o 

r o 

1 

1 

1 1 1 

g m g m 


KCLinv N, I C , s, Z S , Z L KCL N, I C , s, Z S , Z L 

1

Sparam N, I C 

, s KCLi KCLinv N , I C 

, s, 50 ohm, 

50 ohm 

V 

KCLi. 

S 11 , 

V 1 

1 

S 21 , 

V 3 

V 

KCLi. 

S 22 , 

V 3 

1 

S 12 , 

V 1 

S 

2 

50 ohm 

0 

ohm 

0 

ohm 

0 

ohm 

0 

ohm 

0 

ohm 

2 

50 ohm 

0 

ohm 

Sparam N, I C , s 

= 

0.548 0.015i 

0.256 3.975i 

5.547 . 10 3 0.095i 

0.599 0.115i

Z popt SZ , 0 ∆ S . 

11 , 

S 22 , 

S . 

1 2 

2 

B 1 1 S 11 , 

2 

B 2 1 S 22 , 

, 

S 21 , 

2 

S 22 , 

2 

S 11 , 

( ∆ ) 2 

( ∆ ) 2 

C 1 S 11 , 

∆ . S 22 , 

C 2 S 22 , 

∆ . S 11 , 

Γ Spopt 

B 1 B 1 

2 

2C . 1 

4. 

2 

C 1 

2 

B 1 B 1 

Γ Spopt if Γ Spopt < 1, 

Γ Spopt , 

Γ Lpopt 

B 2 B 2 

2 

2C . 2 

4. 

2 

C 2 

2 

B 2 B 2 

Γ Lpopt if Γ Lpopt < 1, 

Γ Lpopt , 

1 Γ 

Z Lpopt Z . Lpopt 

0 

1 Γ Lpopt 

1 Γ 

Z Spopt Z . Spopt 

0 

1 Γ Spopt 

Z Spopt 

2C . 1 

2C . 2 

4. 

2 

C 1 

4. 

2 

C 2 

Z Lpopt 

Z L N, I C , s Z popt Sparam N, I C , s , 50 ohm 

Z Sp N, I C , s Z popt Sparam N, I C , s , 50 ohm 

2 

1 

Z L N, I C , s = 120.278 52.473i ohmOptimal Load Impedance 

Z Sp N, I C , s = 91.811 18.536i ohmOptimal Source Impedance 

1 .10 3 Fig. 14: Max Gain Impedaces vs Frequency 

Impedance (ohms) 

100 

10 

0.1 1 10 100 

Frequency (GHz)

Noise Analysis 

Noise analysis for low noise amplifier design is important not only for the definition of the 

amplifier, but also for it’s application. The noise requirements are determined by the amplitude 

of the signal being received and the desired signal to noise ratio. It is also important to allow 

some of the total system noise budget to other elements in the receiver chain. For cellular 

phones the desired signal amplitude is calculated when the cellular phone is the farthest 

distance from the base station. 

To do the noise calculation we need to include all of the noise sources for the entire low noise 

amplifier circuit, including noise from the bias circuitry and ballast resistor. To simplify the bias 

noise calculations we first need to convert the bias circuit into an equivalent parallel resistance 

and inductance. The current noise from this parallel resistor is added to the input referred current 

noise of the amplifier and not in the input referred voltage noise. In reality it will also have a small 

affect on the voltage noise, but since the bias impedance is usually large it is acceptable to model 

the noise as a current source. 

Conversion from Z bias to L bias and R bias 

Im Z bias 

Q bias 

Q bias = 5.969 Q of an L S in series with R S 

Re Z bias 

2 

L bias if Q bias 0, 

j10 . 9 1 Q bias Im Z bias 

H, . 

L 

2 

bias 51.403 nH 

Q ω 

bias 

= Equivalent Parallel Inductance 

R bias 1 Q bias 

2 

. Re Z bias 

R bias 3.663 . 10 3 ohm 

= Equivalent Parallel Bias Resistance 

To simplify the noise analysis we neglect C µ . C µ is only important for stability and gain analysis. 

KCL analysis of the simplified circuit with noise sources is used to find the gains of the noise 

sources. 

at Base Node 

V s V b V b V e 

V s V b V b V e 

i bn 

r b Z S Z π r b Z S r b Z S Z π 

at Emitter Node 

V b V e 

V 

i bn g . e 

m V b V e i cn 0 

Z π Z e 

at Collector Node 

V b V e 

g . m V b V e 

Z π 

V 

g . c 

m V b V e i cn 0 0 g . m V b V e 

Z L 

V c 

Z L 

V e 

Z e 

KCLsimpleinv Z S , Z L 

1 

1 

0 

r b ( N) Z S Z π N, I C , s 

1 

g m I C 

Z L 

1 

g m I C 0 

Z π N, I C , s 

1 


1 


g m I C 

1 

g m I C 

Z e ( N, 

s) 

1 

79.793 13.307i 

0 

0.301 3.141i 

KCLsimpleinv Z Sp N, I C , s , Z L N, I C , s 

= 

377.04 445.504i 

120.278 52.473i 

94.09 50.208i 

ohm 

76.496 24.317i 

0 

1.793 3.307i

Solve 

r . b i . bn Z . e β β . V . s Z e Z . S i . bn Z . e β i . bn Z . π Z S i . bn Z . π r b Z . π V s Z . S i . cn Z e V . s Z e r . b i . cn Z e 

Z S r b g . m Z . π Z e Z e Z π 

Z . L 

Z . S i . bn Z . π g m r . b i . bn Z . π g m Z . π V . s g m i . bn Z . π Z . e g m Z . S i cn r . b i cn i . cn Z e i . cn Z π 


A v 

Z . e 

i . cn Z π r . b i cn i . bn Z π Z . S i . bn Z . π g m r . b i . bn Z . π g m Z . π V . s g m Z . S i cn V s 

β N, I C , s . para R L N, I C , s , Z L N, I C , s 

r b ( N) β N, I C , s 1 . Z e ( N, 

s) 



A v = 2.845 5.479i Zero Source Impedance 

Voltage Gain 

A i β N, I C , s . para R L N, I C , s , Z L N, I C , s A i = 1.438 2.475i kΩ Infinite Source Impedance 

Current Gain 

Now we can use the gains we just calculated to find the equivalent input voltage and current 

sources and the correlation between the two. In order to find the equivalent input noise source, 

we must first know the magnitude of each of the individual noise sources. These are well known 

values of 4kTr b for the base resistance thermal noise, 2qI B for the base current shot noise, and 

2qI C for the collector current shot noise. 

v bn ( N ) 4. k. Temp. r b ( N) 

v bn N = Base Thermal Noise Voltage 

( ) 0.271 nV Hz 

i cn I C 

i bn I C 

2q . . I C 

2q . 

I 

. C 

β 0 

i cn I C = 56.604 pA Collector Shot Noise Current 

Hz 

i bn I C = 4.682 pA Base Shot Noise Current 

Hz 

i biasn R bias 

i RLn R L 

4k . . 1 

Temp. i biasn R bias 2.126 pA 

R bias 

Hz 

4k . . 1 

Temp. i RLn R L 4.626 pA 

R L N, I C , s 

Hz 

= Bias Resistor Current Noise 

= Load Resistor Current Noise

Equivalent Input Noise Elements 

The equivalent input-referred voltage noise source is found by setting the source impedance 

to zero, finding the transfer function of all the noise sources to the output, adding the up all the 

noise powers at the output, and dividing by the voltage gain from the source itself. Similarly, 

the equivalent input-referred current noise can be found with an input current source and the 

source impedance set to infinity. 

Noiseless 

Noiseless 

v n 

Z L 

Z L 

i neq 

Fig. 15: Circuit used to find input-referred noise voltage 

Fig. 16: Circuit used to find input-referred noise current 

V neq N, I C , s 4k . . Temp. r b ( N ) r b ( N) Z e ( N, 

s) 

+ 

r b ( N) Z e ( N, 

s) Z π N, I C , s 

β N, I C , s 

4k . . 1 

+ Temp. 

. 


2 2 

. . q. 

I B I C 

2 

. 2 . q. 

I C ... 

r b ( N ) β N, I C , s 1 . Z e ( N, 

s) 


... 

β N, I C , s 

2 

I neq N, I C , s 4k . . Temp 

2q . . I B I C 

R bias 

V neq N, I C , s = 0.317 nV Equivalent Input Noise 

Hz 

Voltage 

2q . . I C 4k . . 1 

Temp. 


β N, I C , ω 

2 

Equivalent Input Noise 

Current 

I neq N, I C , s = 5.764 pA Hz 

The input referred noise can be represented by two noise resistances and the correlation 

impedance or admittance. R n is the value of a resistor whose voltage thermal noise is equal to 

the equivalent input voltage noise. g n is the value of a resistor whose current thermal noise is 

equal to the equivalent input current noise. 

R n N, I C , s 

g n N, I C , s 

2 

V neq N, I C , s 

4k . . Temp 

2 

I neq N, I C , s 

4k . . Temp 

R n N, I C , s = 6.064 Ω Equivalent Input Noise 

Resistance 

1 


498.381 Ω 

= Equivalent Input Noise 

Conductance

Noise Correlation 

Except in special cases, the optimal noise source impedance will be different from the optimal 

power source impedance. Thus, when using the optimal noise source impedance, the power 

gain will not be maximized. On the other hand lower power gain will increase the significance of 

the noise from later stages on the noise figure of the system. Thus a tradeoff exists between the 

optimal noise source impedance and optimal power source impedance for minimum overall 

system noise figure. The optimal source impedance for minimum system noise figure can be 

found by including the noise of the following stages, such as the mixer, in the optimal noise 

source impedance calculation. In many optimal source impedance calculations, other sources of 

noise are also neglected. The noise sources to be included in the source impedance calculation 

are noise from the bias source, bonding pad series resistance, series resistance of inductor 

degeneration from bond wires and especially from low-Q on-chip spiral inductors. The series 

resistance of these spirals tend to increase optimal noise source impedance, when they are used 

for emitter degneration of common emitter and common source amplifiers. 

To find the noise gains, a load impedance is assumed, which will in turn affect the gains and the 

optimal noise source impedance. The optimal load impedance for maximum power transfer is a 

good guess for the load impedance. It becomes a better guess as the noise of following stages is 

increased. Once the optimal source impedance is found using a guess for the load impedance, the 

load impedance for maximum power transfer should be recalculated from the complex conjugate of 

the output impedance of the device with the optimal system noise source impedance. 

Thus the steps for finding optimal system noise source impedance are as follows: 

1. Find S parameters of the circuit directly or indirectly by finding the Y 

parameters of the device directly. 

2. Find the optimal load and source impedance with the calculated S 

parameters. 

3. Find the gains of all noise sources and an input voltage source to the output 

with a zero source impedance. Include all noise source gains, including the 

noise of following stages and bias noise. 

4. Find the gains of all noise sources and an input current source to the output 

with a infinite source impedance. 

5. Use the gains to find the input referred equivalent voltage and noise sources 

and the correlation impedance. 

6. Use the equivalent voltage and current noise sources to find the equivalent 

series and parallel noise resistances. 

7. Use the correlation impedance and noise resistances to find the optimal 

source impedance. 

8. Recalculate desired output impedance given the optimal system noise 

source impedance. 

. 

I 

VI conj N, I C , s r b ( N) Z e ( N, 

s) . 2. 

C 

q. r b ( N ) Z e ( N, 

s) Z π N, I C , s 

β 0 

+ 

VI conj N, I C , s = 0 W Hz 

r b ( N ) β N, I C , s 1 . Z e ( N, 

s) 


. 

2q . I C 

β N, I C , s 

4k . . 1 

Temp. 


. 

β N, I C , s 

2 

2 

...

γ N, I C 

, s 

VI conj N, I C 

, s 

V neq N, I C 

, s 

2. 

I neq N, I C 

, s 

2 

γ N, I C 

, s = 0.111 0.088i 

Correlation Coefficient 

The correlation impedance is derived from the zero and infinite source impedance noise 

gains and the equivalent input noise sources. The noise correlation impedance is useful for 

finding the optimal source impedance for low noise. In the special case, where the input 

equivalent voltage and noise sources are 100% correlated, the correlation impedance is equal to 

the input impedance. This ideal scenario allows maximum power transfer to occur 

simultaneously with minimum noise figure. An example when this situation occurs is when the 

backend noise, such as the mixer noise, is high. 

The correlation impedance or admittance between the input equivalent current and voltage 

noise can now be calculated as shown in the following equations. Note that the correlation is not 

equal to the inverse of the correlation impedance, except in the special case, where current and 

voltage noise is 100% correlated. 

Noiseless 

Noiseless 

Z S 

v n 

i n 

Z L 

Z S 

v neq 

i n2 

=Y corr 

*V neq 

Z L 

i n1 

Fig. 17: Circuit with correlated noise sources 

Fig. 18: Circuit used to find Y corr 

Y corr N, I C , s γ N, I C , s 


. 1 

2 


2 

Y corr N, I C , s 

= 304.9 241.319i Ω Correlation Conductance 

Noiseless 

v n2 

=Z corr 

*I neq 

Z S 

v n1 

i neq 

Z L 

Fig. 19: Circuit used to find Z corr 

Z corr N, I C , s γ N, I C , s 

2 


. Z 

2 corr N, I C , s 6.094 4.823i Ω 


= Correlation Impedance

n is the noise resistance representing the portion of V neq 

2 which is uncorrelated with I neq 

2. 

It is always less than R n , and in the case where the noise is 100% correlated, it is equal to 0. 

r n N, I C 

, s R n N, I C 

, s . 1 γ N, I C 

, s r n N, I C 

, s 5.943 Ω 

2 

= Correlation Resistance 

G n is the noise resistance representing the portion of I 2 neq which is uncorrelated with V neq 

2. 

It is always greater than g n , and in the case where the noise is 100% correlated, it is equal to 

infinity. 

2 

G n N, I C 

, s g n N, I C 

, s . 1 γ N, I C 

, s 

1 

G n N, I C , s 

Optimal Noise Figure and Source Impedance 

= 508.546 Ω Correlation Conductance 

The optimal source resistance is then given by the following equation, using admittance or 

impedance noise parameters. Both cases should given the same answer. 

Z nopt N, I C , s 

r n N, I C , s 


Z nopt N, I C , s = 54.761 4.823i ohm 

Re Z corr N, I C , s 

2 

. Optimal Source Impedance 

for Minimal Noise Figure 

jImZ corr N, I C , s 

In the special case, where the noise of the following stages dominates, the optimal noise 

source impedance will equal the optimal power source impedance. In the special case, where the 

noise of the following stages is zero, the optimal system source impedance will equal the optimal 

device source impedance. An optimal system noise figure can be derived by cascading an 

infinite number of identical devices and finding the optimal source impedance. Friis explored this 

ideal to derive and optimal system source impedance given a single device charateristics. In 

reality, all of the devices in a receiver chain will not be the same for distortion purposes. 

NF min N, I C , s 10. 

log 1 2. 

g n N, I C , s . Re Z corr N, I C , s 

... 

+ 

g n N, I C , s . r n N, I C , s g n N, I C , s Re Z corr N, I C , s 

. 

2 

NF min N, I C , s = 0.949 dB 

Optimal Noise Figure 

Noise figure will also be increased by a jammer a frequency offset from the desired signal 

f off +f desired , mixing with bias noise at the same offset at basband, f off . This derivation is breifly 

described in the Mathcad file: biasnoise.mcd.

Noise Figure Plots 

NF N, I C 

, s, Z S 10. 

log 1 

r n N, I C 

, s 

Re Z S 

g n N, I C 

, s 

. Z S Z corr N, I C 

, s 

Re Z S 

2 

4 

5 

3 

4 

Noise Figure (dB) 

2 

Noise Figure (dB) 

3 

2 

1 

1 

0 

0 200 400 600 

0 

200 100 0 100 200 

Source Resistance (ohms) 

Source Reactance (ohms) 

Fig. 20:Noise Figure vs Source Impedance 

Fig. 21:Noise Figure vs Source Reactance 

1.4 

2.5 

Minimum Noise Figure (dB) 

1.2 

1 

0.8 


2 

1.5 

1 

0.6 

0 5 10 15 20 

0.5 

0 20 40 60 80 100 





Fig. 22: Min. Noise Figure vs. Current 

Fig. 23: Noise Figure vs. Device Size 

150 

150 

100 

100 


50 


50 

0 

0 

50 

0 5 10 15 20 

50 

0 20 40 60 80 100 


Imaginary Part of Optimal Source Impedance 

Real Part of Optimal Source Impedance 


Imaginary Part of Optimal Source Impedance 

Real Part of Optimal Source Impedance 

Fig 24: Optimal Noise Impedance vs Ibias 

Fig. 25:Optimal Source Impedance vs Size

Optimal Source Impedance to Trade-Off Power and Noise 

The following method is a crude, but quick and relatively easy method for finding the optimal 

source impedance to trade-off power and noise. A more accurate method is discusses below 

but not implemented. 

Optimal Noise Source Impedance: 

Z n =r n +jx n , 

NF=NF min 

Optimal Gain Source Impedance 

Z p =r p +jx p , 

G=G max , 

S 11 =0 

Constant S 11 contour 

Desired Source Impedance 

Z=r+jx 

S 11 =Desired Specification 

Fig. 26: Figure used to illustrade noise and power trade-off 

In the design of a low noise amplifier,LNA, or mixer driver stage there exists an optimal source 

source impedance to provide the maximum power transfer into the transistor and thus the 

maximum gain. There also exists an optimal source impedance, Z nopt , to provide the minimum 

noise figure for the circuit. At the maximum power source impedance, Z popt , the input is matched 

to the source impedance and no reflections occur. This is desirable, because the filters attached 

to designed for the LNA or mixer, are designed for a matched load impedance, but can tolerate a 

certain amount of deviation from it’s desired impedance. The amount of acceptable deviation is 

usually specified by the maximum return loss, or S 11 , the filter can handle. The routine below 

finds the source impedance to the LNA or mixer, which will provide the lowest noise figure and 

maximum gain, while maintaining a desired S 11 specification. 

The calculation is performed by drawing a straight line between the optimal noise and power 

source impedances and finding where it intersects the desired S 11 contour. This line intersects 

the contour at two points, so the point must be chosen, which is closet to the optimal noise 

source impedance. Sometimes, the desired S 11 specification is acheived at the optimal noise 

source impedance. In this case the optimal noise source impedance is chosen over the 

intersecting point. This calculation is not optimal in the truest sense, because the noise and 

power gain circles are not coencentric, but it serves as an good estimate to meet design criteria.

Z Ss11 Z p 

, Z n 

, S 11goaldB S 11goal 10 

S 11goaldB 

20 

Z in 

r i 

x i 

r p 

x p 

r n 

x n 

Z p 

Re Z in 

Im Z in 

Re Z p 

Im Z p 

Re Z n 

Im Z n 

S 11n 20 log Z in Z 

. 

n 

Z in Z n 

g 

1 S 11goal 

2 

1 S 11goal 

2 

m x p x n 

r p r n 

a 1 m 2 

b 2. x i x n mr . . n m 2r . . i g 

c r i 

2 

x i x n mr . 2 

n 

1 

r . 1 

( 2a . ) 

b b 2 4a . . c 

x 1 m. r 1 r n x n 

d 1 r 1 r n 

2 

x 1 x n 

2 

1 

r . 2 

( 2a . ) 

b b 2 4a . . c 

x 2 m. r 2 r n x n 

d 2 r 2 r n 

2 

x 2 x n 

2 

r if d 1 < d 2 , r 1 , r 2 

x if d 1 < d 2 , x 1 , x 2 

Z Sans 

if S 11n < S 11goaldB , Z n , r 1. 

x 

Z Sans 

Z Sp N, I C , s = 91.811 18.536i ohm 

Optimal Source Impedance for Conjugate Matching 

Z nopt N, I C , s = 54.761 4.823i ohm 

Optimal Source Impedance for Minimum Noise Figure 

Z S N, I C , s Z Ss11 Z Sp N, I C , s , Z nopt N, I C , s , S 11goaldB Z S N, I C , s = 67.707 3.339i ohm 

Optimal Source Impedance to trade-off Noise and 

Power

Gain Analysis 

Z2Γ( Z) 

Z 

Z 

G T 

Γ G 

, Γ L 

, S 

50 ohm 

50 ohm 

Available Power Gain 

1 Γ L 

2 

2 

S 2, 1 

Power 

2 

. . 1 Γ G 

1 S . 

22 , 

Γ . L 

1 S . 

1, 1 

Γ G S 12 

Impedance to Reflection Coefficient Conversion 

. . Γ L 

Γ G 

, 

S 21 , 

. 

2 

Transducer Gain 

G avail N, I C 

, s 10. log G T Z2Γ Z S N, I C 

, s , Z2Γ Z L N, I C 

, s , Sparam N, I C 

, s G avail N, I C 

, s = 14.166 dB 

15 

25 

Available Power Gain (dB) 

14 

13 


20 

15 

12 

0 5 10 15 20 

10 

0 20 40 60 80 100 





Fig. 27: Power Gain vs. Bias Current 

Fig. 28: Power Gain vs. Device Size 

Distortion Analysis 

The distortion analysis routines were copied directly from the thesis of Keng Fong [2]. They are 

the most inaccurate portion of the design routine as they do not reflect the impact of the input 

matching network on distortion performance. From comparisions to simulations we see the results 

differ by 3-9dB. Future work will add the effects of the input matching network and bias circuitry. 

Low distortion in a low noise amplifier is important to prevent undesired signals from 

interfering with the desired signal. The most important measure of distortion performance is the 

third order intercept point. The scenario where third order distortion is important is when the 

receiving device is located a distance far from the transmitting device, and two devices are 

transmitting signals close to the device, spacing at frequencies ∆f and 2*∆f from the desired 

signal. Through third order distortion, the undesired signals, jammers, mix together to produce a 

signal in the desired band. To prevent this signal from degradation the performance of the 

receiver the low noise amplifier must be acceptably linear. 

A measure of the third order intercept point is used define at acceptable level of linearity. The 

third order intercept point is defined the as the jammer power required to make the amplitude of the 

jammer equal to the power of the undesired signal produced through third order intermodulation. 

This is shown graphically in the following figure.

P jammer 

P jammer 

Amplitude 

P desired 

P IM3 

IM 3 

P IM3 

f 

Fig. 29: Nonlinear LNA Output Spectrum with Undesired Signals 

Amplitude (dBm) 

P jammer 

P IM3 

IM 3 

IP 3 

P jammer 

Fig. 30: Intermodulation as a function of Undesired Signal Power 

This routine finds the two-tone third-order intermodulation intercept point, IP 3 , given device 

size, current, and base and emitter impedances. The collector base capacitance is neglected for 

simplicity. 

f 1 f ∆f ω 1 2. π . f 1 s 1 j. ω 1 

Frequency of First Jammer 

f 2 f 2. ∆f ω 2 2 π 

. Frequency of Second Jammer 

. . f 2 s 2 j ω 2 

2. π . f 1 s 3 j. ω 1 

Third Frequency for Distortion Analysis 

= Base Impedance for Distortion 

ω 3 

Z b N, Z S , s r b ( N) Z S Z b ( N, 50 ohm, 

s) 54.441 ohm 

ZNZ , S , s Z b N, Z S , s Z e ( N, 

s) 

A 1 N, I C , Z S , s 

A 1 N, I C , 50 ohm s 

g m I C 

Calculations 

ZNZ , 

sC . je N, 

I . C ZNZ , S , s s. τ . F g m I . S , s 

C ZNZ , S , s g m I . C 1 g m I . C Z e ( N, 

s) 

β 0 

, = 6.412 48.737i mA 

Linear Term 

V 

A 2 N, I C , Z S , s 1 , s 2 A 1 N, I C , Z S , s 1 s . 2 A 1 N, I C , Z S , s . 1 A 1 N, I C , Z S , s 2 

A 2 N, I C , 50 ohm, s 1 , s 2 91.636 2.859i mA 

A1A2 N, I C , Z S , s 1 , s 2 , s 3 

V 2 

V 

. T . 1 s 

2 1 s . 2 C je N, 

I . C Z 

2I . C 

= Second Order Distortion Term 

A 1 N, I C , Z S , s 1 

. A 2 N, I C , Z S , s 2 , s 3 ... 

+ A 1 N, I C , Z S , s 2 

. A 2 N, I C , Z S , s 1 , s 3 ... 

+ A 1 N, I C , Z S , s 3 

. A 2 N, I C , Z S , s 1 , s 2 

A1A2 N, I C , 50 ohm, s 1 , s 2 , s 3 412.597 3.031i . 10 3 mA 2 

3 

= Second Order Interaction Term 

V 3

A 3 N, I C 

, Z S 

, s 1 

, s 2 

, s 3 A 1 N, I C 

, Z S , s 1 s 2 s 3 

A 3 N, I C 

, 50 ohm, s 1 

, s 2 

, s 3 8.458 5.157i mA 

V 3 

V 

. T . A 

3 1 N, I C 

, Z S 

, s . 1 

A 1 N, I C 

, Z S 

, s . 2 A 1 N, I C 

, Z S 

, s 3 

3I . C + 3I . . C A1A2 N , I C , Z S , s 1 , s 2 , s 3 

= Third Order Distortion Term 

Z in N, I C 

, s r b ( N) Z π N, I C 

, s 1 g m I . C Z π N, I C 

, s Z e ( N, 

s) 

. Input Impedance 

Z in N, I C 

, s = 463.053 21.963i ohm 

IP 3 N, I C , Z S , f, ∆f s j. 2. π . f 

∆s j. 2. π . ∆f 

10. 

log 

IP 3 N, I C , Z S N, I C , s , f, ∆f 12.046 dB 

1 4 A 

. 1 N, I C , Z S , s 

. . 1 . 1 

1mW3 

A 3 N, I C , Z S , s, s, 

( s ∆s) 

8 50 ohm 

= Third Order Intercept Point 

20 

16 

Intercept Point (dBm) 

10 

0 

3rd Order Intercept Point (dBm) 

14 

12 

10 

10 

0 5 10 15 20 

8 

0 20 40 60 80 100 


3rd Order Intercept Point (dBm) 


Third Order Intercept Point (dBm) 

Fig. 31: IP3 vs. Bias Current 

Fig. 32: IP3 vs. Device Size 

It is interesting to understand the shape of the 3 rd order intercept point curve as a function of 

device size. For small device sizes, as the device size is increased the distortion performance gets 

worse, but for very large devices the distortion performance gets better as the device size 

increases. This fact is not explained with the simplified equations for the distortion given above. 

The simplified equations for distortion given above neglect the resistance of the emitter as a 

function of device size. The shape can be described better by separating the interept point into it’s 

two components: The linear term, A 1 , and the nonlinear term, A 3 . As we plot A 1 and A 3 as a 

function of device size, we notice A 3 is a much stronger function of area than A 1 , but they both 

have a similar shape. The intercept point reaches it’s minimum about the same time A 1 reaches it’s 

maximum.

maximum. 

So why does A 1 increase intially for small devices and decrease for large devices? For small 

devices the device is operating well below the maximum frequency, f T , for the device. In this 

region capacitive effects are less significant and resistive effects are more significant. Here A 1 

is approximately gm/(1+g m *r e0 /N). As the device size gets larger the effective degeneration is 

reduced, which increases the linear gain, A 1 . However for large devices, the base emitter 

capacitance increases to the point, approaching f T , where the capacitive effects become 

significant, the effective device f T is reduced with increasing device size, and we see losses in 

the high frequency gain. The resistive and capacitive effects tend to cancel at some point, and 

which gain only varies slowly as a function of device size. 

Now we must answer the more important question: Why does A 3 decrease for large devices? 

If we look carefully at the equations for the intercept point, we notice A 3 is a strong function of 

A 1 

3. If this is true A 3 will have a similar shape to A 1 , except exaggerated more. This is exactly 

what we see if we plot A 1 and A 3 independently as a function of frequency. 

0.05 

0.04 

Linear and Third-Order Terms 

0.03 

0.02 

0.01 

0 

0 20 40 60 80 100 

Device Size 

Linear Term 

Third Order Term 

Fig. 33: A1 and A3 vs. Device Size 

Overall LNA Figure of Merit 

The input referred minimum detectable signal with an amplifier is defined below for a signal 

of a given bandwidth and noise figure. The noise figure is given in dB and MDS in dBm. 

MDS( BW, 

NF) k. T. BW 3 NF 

The spurious free dynamic range, DR f , is defined as the ratio between vmax and vmin, where 

vmax the input signal where the IM 3 just breaks the noise floor defined by vmin. IP 3 is specified 

in dBm, G in dB, and MDS in dBm. 

DR f IP 3 , G, 

MDS 

2 . 

3 IP 3 G MDS 

The dynamic range is defined similarly with the 1dB compression point defined as vmax. 

DR P 1dB , G, MDS P 1dB G MDS

Optimizing Area and Current 

I C 0.006 Unitless Guesses at optimal bias current 

and device size 

N 50 

NF N, I C NF min N, I . C A, 

s 

Given 

I C 

> 0 

Bias Current Constraint 

N> 0 

Device Size Constraints 

G avail N, I . C A, s G goaldB 

IP 3 N, I . C A, Z nopt N, I . C A, 

s , f, ∆f IP 3goaldBm 

46.572 

P Minimize NF, N, I C P = 

7.277 . 10 3 

N opt P 1 

N opt 46.572 

I Copt 

> Available Power Gain Constraint 

> Intercept Point Constraints 

= Optimal Device Size 

P . 

2 

A 

I Copt = 7.277 mA Optimal Bias Current Size 

NF min N opt , I Copt , s = 0.84 dB 

Optimal Minimum Noise Figure 

, , , s , f, ∆f = 10 dBm Optimal Intercept Point 

IP 3 N opt , I Copt Z nopt N opt I Copt 

Z S N opt , I Copt , s = 62.211 5.063i ohm 

Optimal Source Impedance 

Z L N opt , I Copt , s = 110.436 61.585i ohm 

Optimal Load Impedance 

G avail N opt , I Copt , s = 13.5 dB 

Optimal Gain 

Package (Bonding Wire/ Bonding Pad) Deimbedding 

The actual impedance matching network is outside of the chip, but calculations for the desired 

source and load impedances were calculated for the device inside the chip. These internal 

source and load impedances must be transformed into the source and load impedances seen by 

the matching networks. To find these conversion equations we first write the equation for 

impedance seen by the device, Z S , given an impedance seen by the outside of the chip, Z Schip . 

Then we use this equation to solve for Z Schip in terms of Z S . 

Source Impedance Bonding Pad/Wire Deimbedding 

Z Schip 

L bond 

C pad 

Z S 

AMP 

Fig. 34: Circuit Used to Solve for Source Impedance Bonding Deimbedding

First we write the equation for the impedance seen by transistor. Then use this equation to solve 

for the desired impedance seen by the chip given the impedance the transistor wants to see. 

Z S para 

1 

, sL . 

sC . bond Z Schip 

pad 

Z Schip N opt , I Copt , s 

1 . 

sC . pad 

1 

sC . pad 

1 . Z 

sC . S N opt 

, I Copt 

, s 

pad 

1 

sC . pad 

Z S N opt , I Copt , s 

sL . bond Z Schip 

sL . bond Z Schip 

Load Impedance Bonding Pad/Wire Deimbedding 

sL . bond 

Z Schip N opt , I Copt , s = 60.362 6.225i Ω 

Z L 

L bond 

Z Lchip 

AMP 

C pad 

Z L para 

Fig. 35: Circuit Used for Solve for Load Impedance Bonding Deimbedding 

1 

, sL . 

sC . bond Z Lchip 

pad 

Z Lchip N opt , I Copt , s 

1 . 

sC . pad 

1 

sC . pad 

1 . Z 

sC . L N opt , I Copt , s 

pad 

1 

sC . pad 

Z L N opt , I Copt , s 

sL . bond Z Lchip 

sL . bond Z Lchip 

sL . bond 

Z Lchip N opt , I Copt , s = 86.832 53.027i Ω

Impedance Matching 

High-pass impedance matching networks are chosen to compensate for the gain loss of the 

transistor at higher frequencies. This also helps to stabilize the transistor at lower frequencies. 

Highpass L Matching Network 

highL Z S 

, Z L 

, f ω 2. π . f 

C 1 if Im Z L 0, 

1000 F 

1 

, 

ω . Im Z L 

R S 

Q S 

Re Z L 

Im Z S 

Re Z S 

R p 1 Q S 

2 

.Re Z S 

2 

1 Q S Im Z 

L . S 

1 

2 

Q ω S 

Q 

R p 

R S 

1 

L p 

R p 

ω . Q 

1 

C S 

Q . ω . R S 

C 

L 

L 

H 

C 

F 

C . 1 C S 

C 1 

L . p L 1 

L 1 

C S 

L p

Source Matching Network #1: Highpass 

50 ohms 

C 

Z S 

AMP 

V S 

L 

Fig. 36: Highpass source matching network 

x 

L S 

C S 

highL Z S N opt , I Copt s 

, , 50 ohm, 

f 

x . 

1 

H 

L S = 8.985 nH Source Matching Inductance 

x . 

2 

F 

C S = 3.334 pF Source Matching Capacitance 

Load Matching Network 

Z L 

L 

AMP 

C 

50 ohms 

Fig. 37: Highpass load matching network 

x 

L L 

C L 

highL Z L N opt , I Copt s 

, , 50 ohm, 

f 

x . 

1 

H 

L L = 6.269 nH Load Matching Inductance 

x . 

2 

F 

C L = 1.217 pF Load Matching Capacitance

Low Frequency Stabilization 

It is desirable to convert the parallel combination of the load matching network inductor and 

the ballast resistor into a series combination. This has the beneficial effect of improving the 

stability of the amplifier at lower frequencies, at the expense of stability at higher frequencies. 

The assumption is that stability is acheived at higher frequencies because of the reduced gain 

and because the small parasitic losses of the passive elements become significant 

Ballast Resistor 

R S 

R p 

L p 

L S 

AMP 

AMP 

C 

50 ohms 

C 

50 ohms 

Fig. 38: Ballast resistor conversion from parallel to series 

Q LP R P , L P , ω 

R P 

L . P ω 

Q of an L P in parallel with R P 

LP2S R P , L P , ω 

L LS 

R LS 

Q LP R P , L P , ω 

1 Q LP R P , L P , ω 

1 

1 Q LP R P , L P , ω 

LP2S R L N opt , I Copt , s , L L , ω 

LP2S R L N opt , I Copt , s , L L , ω 

2 

1 

2 

2 

L 

. P 

H 

R 

. P 

ohm 

. H L LS 6.205 nH 

2 

Conversion from L P and R P to L S and R S 

= Series Load Inductance 

. ohm R LS 7.508 ohm 

= Series Load Resistance 

Outputs 

I Copt = 7.277 mA 

N opt = 46.572 

L S 

C S 

= 8.985 nH 

= 3.334 pF 

C L = 1.217 pF 

L LS 

R LS 

= 6.205 nH 

= 7.508 ohm 

Optimal Bias Current 

Optimal Device Size 

Optimal Source Matching Inductance 

Optimal Source Matching Capacitance 

Optimal Load Matching Capacitance 

Optimal Load Matching Inductance 

Optimal Series Load Ballast Resistor

Simulation 

Fig. 39: Circuit schematic used in Cadence simulations 

After the initial design with Mathcad, we simulated the circuit using Cadence. Cadence’s IC 

design tools allow the LNA design to be taken to the next levels of layout and fabrication. Just like 

its counterpart, Cadence is also capable of displaying stability, gain and noise figure circles on a 

Smith chart. However, setting up Cadence requires a considerable amount of time to guarantee 

reliable 

results. 

The distortion specification for our LNA is the input-referred third-order intercept point, IIP 3 , 

which is measured with a two-tone test. The two tone test is simulated by adding two sinusoidal 

signals at 1.90 GHz and 1.91 GHz to the input, each having a -20 dBm available input power, 

P in (dB). The amplitude of the third order intermodulation, products, IM3(dB), is then measured by 

performing a discrete-time Fourier transform of the output signal. When plotted in decibels 

against input power, the output power and IM 3 curves are relatively straight lines with slopes of 1 

and 3 respectively, which is shown in figure 1 below. IIP 3 , is defined as the input power at which 

the extrapolated IM 3 and output power curves intercept. As we know the slope of each curve and 

a point through which each one passes, we can easily calculate IIP 3 with a single transient 

simulation with the following formula: 

IIP 3 ( dBm) 

IM 3 ( dB) 

2 

P in ( dBm) 

The schematic used for the simulation is presented in figure 39. For additional accuracy in 

modeling the fabricated amplifier, the inductance of the bonding wires, capacitance of the bonding 

pads, and the resistance of the bond wires were added to the schematic. The vias from the ground 

plane of the PC board were calculated to be 0.11nH, and were initially added to the schematic with 

little effect.

To insure stability over the spectrum, resistors were strategically placed throughout the circuit. 

The best method to improve low frequency stability is to add a resistance in series with an inductor 

connected from the signal path to ground. Similarly, high frequency stability is enhanced with a 

resistance in series with a capacitor connected from the signal path to ground. Resistors degrade 

the noise and gain performance of the amplifier so it would be desirable to use reactive elements to 

improve stability. Unfortunately, although reactances affect the input and impedances of the 

amplifer, they have no effects on the unconditionaly stability factor, K around the K=1 point. In this 

LNA resistance was intentionally placed in series with the output and input bonding pads to 

achieve unconditional stability condition at high frequencies. The simulation results for the K-factor 

of the final version of our circuit have been plotted in Fig. 40 and Fig. 41. 

Fig. 40: Simulation results for K-factor 

Fig. 41: A closer look at K-factor at high frequencies

After the amplifier was unconditionally stabilized, the input-matching networks were optimized 

to trade-off gain and noise while meeting the specifications of 12 dB gain and 1.5dB NF. 

Although including more parasitic elements in our simulations than in the Mathcad calculations 

prevented us from getting exactly the predicted values, we have happily observed that the 

general trends stayed the same. The device size, bias current, value of the degeneration 

inductance and the input-matching network based on our simulations of power gain, noise figure, 

linearity, 

Fig. 42: Input reflection coefficient as a function of frequency 

Fig. 43: Transducer power gain vs. frequency

It is possible to use on-chip inductors to increase integration, decrease external component 

count, thus reducing the price of the overall LNA. Unfortunately, on-chip inductors have a series 

resistance, which reduces their Q to 3-5 at 1GHz. On-chip inductors were not used for the 

input-matching network to prevent a noise figure increase, but it is possible to use on-chip 

inductors for the load inductance without degradation of performance. A load inductance loss is 

already introduced to stability the amplifier at low frequencies. This resistance of the on-chip 

inductor can be subtracted from this loss to yield the same performance amplifier. Off-chip 

inductors manufactured by Toko, with Q values between 30 and 60 at around 2 GHz, were 

assumed for the input matching network. When compared with an on-chip inductor with a Q value 

of 3, the input-referred noise power increased by 20%, which would give a large 0.3dB increase 

in noise figure. 

The input-matching network used is a first order high-pass filter. In our final version we used a 

series input capacitance of 2.5pF and a shunt inductance of 11nH (Q is assumed to be 50). DC 

coupling between the input and the LNA has been achieved by using a capacitance of 100pF. 

According to our simulations, this network provides a good compromise between the power and 

noise source input impedance. 

The output-matching network used is a 5.5nH shunt inductor and a series capacitance of 

800fF. The inductor is in series with a 10 ballast resistance and both of them are placed between 

the voltage supply and the output node. The capacitance also enables us to get DC coupling 

between the amplifier and the output. 

Conclusions 

A 2.7V 1.9 GHz low noise amplifier with a noise figure of 1.31 dB, transducer power gain of 

14.25 dB, an S11 of -14 dB and IIP3 of 7.75dBm has been presented. Unconditional stability at 

all frequencies with negligible loss in performance has been guaranteed with carefully placed 

resistances in the load matching networks. An automated LNA design procedure has been 

developed to optimize and enhance the speed of the designing low noise amplifiers. The design 

procedure includes a new method for trading the optimal noise and power source impedances of 

the amplifier. 

References 

[1] Microwave Engineering, 2nd edition, 1998, David M. Pozar, pg. 208. 

[2] "Analysis and Design of Monolithic Integrated Mixer," by Keng Fong, U.C. Berkeley Ph. D. 

thesis, 1997. 

[3] "The implementation of a High Speed Experimental Transceiver Module with an Emphasis on 

CDMA Applications," by Arya Reza Behzad, U.C. Berkeley Electronics Research Laboratory 

Memorandum No. UCB/ERL M95/40 

[4] "RF Circuit Design," by Chris Bowick, 1982, Butterworth Heinemann Publishers

N, Z S , s 1 s 2

... . 1 s 1 s 2 s . 3 C je N, 

I . C ZNZ , S 

, s 1 s 2 

s 3

Mathcad - ee217projtodonew2.mcd

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