DRAFT IEEE Standard for Binary Floating-Point Arithmetic - Sonic.net

DRAFT IEEE Standard for Floating-Point Arithmetic – 2003 August 12 10:20
• When the combination field G is 110xx or 1110x, the leading
significand digit d 0 is 8+G 4 , a value 8 or 9, and the leading
exponent bits are 2G 2 +G 3 , a value 0, 1, or 2.
• When the combination field G is 0xxxx or 10xxx, the leading
significand digit d 0 is 4G 2 +2G 3 +G 4 , a value in the range 0..7,
and the leading exponent bits are 2G 0 +G 1 , a value 0, 1, or 2.
And consequently if T is 0 and G is 00000, 01000, or 10000,
then v = (–1) S 0.
[So there are emax + -emin representations of a signed zero.
-JDD]
The trailing significand field T contains J declets, groups of ten
bits encoding three decimal digits using the densely packed
decimal encoding scheme described in Cowlishaw, M.F.,
“Densely Packed Decimal Encoding,” IEE Proceedings -
Computers and Digital Techniques, ISSN 1350-2387, Vol. 149,
No. 3, pp102-104, May 2002.
Copyright © 2003 by the Institute of Electrical and Electronics Engineers, Inc. This document is an unapproved
draft of a proposed IEEE-SA Standard - USE AT YOUR OWN RISK. See statement on page 1.
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