Tutorial - Semiconductor Wafer Test Workshop

June 9-12, 2013 San Diego, CA, USA
Tutorial Sunday, June 9, 2013
Tutorial (Part 1): Use of resource sharing techniques to increase parallel test
and test coverage in wafer test
The tutorial will discuss methods being developed and used in HVM for DRAM and NAND
testing to increase parallel testing on wafer level. Starting from straight forward driver sharing to
the most advanced use of electronic switches to multiplex all kind of tester resources (AC, DC
and Power).
It will be discussed as well how this methods can be used in other applications like SOC,
Embedded Memory test etc. as well. On top of that other examples of using electronics to extend
the testers capabilities will be shown, e.g. use of DC/DC converters to increase the current
capability of tester power supplies.
Presenter: Michael Huebner, Ph.D.
Michael Huebner got his PhD in technical Physics from the University of Bayreuth in
Germany. After his PhD he started at Siemens Semiconductors in the Memory division, which
later became Infineon Technologies. At Siemens/Infineon Michael was responsible for wafer test
equipment with special focus on probe cards. He also worked on test concepts for DRAM SORT,
high frequency test and WLBI. 2006 he joined FormFactor in Livermore first as Sr. Director of
Product Marketing. For the first couple years he was focused on advanced TRE (tester resource
enhancement) and new test strategies with the target to further increase in parallel test and by this
reduce the overall cost of test. After this he was the marketing owner for probing technologies.
He is now Sr. Director of Engineering leading the development activities for electronics on probe
cards (A-TRE).
SWTW 2013 Office
1 Marsh Elder Lane, Savannah, GA 31411
Phone: 540-937-5066 • Fax: 540-937-7848

June 9-12, 2013 San Diego, CA, USA
Tutorial (Part 2): Methods of analyzing/predicting scrub margin for pads and
bump applications
The tutorial will discuss methods of specifying and measuring scrub capability of probe cards.
The material will compare and contrast the commonly used scrub margin approach of
establishing specifications for various probe card elements and worst-case stack-up of those
probe card parameters with a more direct scrub mark measurement approach and quantification
of scrub capability.
Presenters: Tom Watson and Amy Leong
Tom Watson is a currently a FormFactor Manufacturing Fellow having joined FormFactor in
September of 2000. Tom received his bachelor’s degree from the University of California at
Berkeley (Go Bears!) in Electrical Engineering and his master’s degree from the University of
Santa Clara also in Electrical Engineering. His work history includes 13 years at IBM where he
held various equipment, process engineering, and managerial positions in the disk storage
technology division and 8 years at thin film disk manufacturer Komag Inc., where he was
responsible for test engineering and later product engineering and product qualification. Since
joining FormFactor, Tom has served in multiple areas including Development Program
Management, Assembly and Test Engineering, Device Engineering, Product Performance, and
Product Integration. Additionally, Tom developed and delivers statistical process control training
within FormFactor.
Amy Leong is currently Vice President of Marketing at Form Factor MicroProbe Business
Unit. She has been with Form Factor and MicroProbe for more than 8 years. Prior to
FormFactor, Ms. Leong worked in a variety of semiconductor process engineering and product
marketing roles at KLA-Tencor, IBM and Gartner. Ms. Leong is part of SWTW program
committee, and a regular presenter at the conference. Ms. Leong holds an M.S. in Material
Science and Engineering from Stanford University and a B.S. in Chemical Engineering from the
University of California, Berkeley.
SWTW 2013 Office
1 Marsh Elder Lane, Savannah, GA 31411
Phone: 540-937-5066 • Fax: 540-937-7848