Qualcomm's Assessment of 3D Interconnect Equipment ... - Sematech

An Assessment of 3D Interconnect,
Equipment Readiness and ITRS 3D
Through Silicon Stacking (TSS) 3D technologies are approaching
application readiness. We will present Qualcomm’s assessment of
3D equipment readiness for the adoption of TSS technology in
ASICs used in mobile and wireless markets. The presentation will
focus on the challenges that are specific to our application space and
compare Qualcomm’s TSS requirements to those proposed by ITRS
and how having solid requirements should assist the industry in
closing these gaps for successful, cost-effective, high volume
production in the near future.
Thomas R. Toms July 16, 2008
PAGE 1

3D TSS
• Many Advantages
• Many Challenges
Aggressive Roadmap
Process
Materials
Perception
Technology is
MANY years from
High Volume Production
Equipment
Design Tools and Methodologies
Cost
An Alignment of these Challenges with real Applications
3D TSS Technology can be implemented sooner
Thomas R Toms July 16, 2008
PAGE 2

Outline
• Terminology
• Growth in mobile and wireless markets
• Capabilities vs. Application driven 3D
• A TSS case study
TSV selection counts/tier
Si Growth
Tier to Tier interconnects
Si tier thickness
Feature size vs. Throughput and Yield
• Issues for TSS
• Concluding remarks
Thomas R Toms July 16, 2008
PAGE 3

Terminology
3 Tier TSS
TSS – Through Silicon Stacking
AF – The active face of the silicon wafer/die
BF – The back face side of the wafer/die
TSV – Through Silicon Via
KOA – Keep Out Area
Tier – 2D Silicon layer
T2T – Tier to Tier
RDLB – A BF metal layer
Tier 2
Tier 1
BF
Tier 3
T2T
RDLB
KOA
Farm – An N by M array of TSVs connected to the same circuit node
TSV
Farm
AF
Thomas R Toms July 16, 2008
PAGE 4

Growth in mobile and wireless markets
In 2007 Qualcomm shipped
273 million MSM chips,
up 25% from 2006. For
the latest quarter
Qualcomm shipped ~85
million MSM chips, up
39% year-over-year
2
1
Global Handset Demand in Billions
Source: ABI Research
Smartphone/Feature Phone
Enhanced Phone
Low-End
Source: Qualcomm Q2 FY08 Earnings
April 23, 2008, Pages 4, 13
0
2006 2007 2008 2009 2010 2011 2012
Thomas R Toms July 16, 2008
PAGE 5

Which comes first
Capabilities driven vs. Application driven requirements
The equipment or the design
High density TSV and T2T or the µ-architecture to use the very large bandwidth that
TSS offers
Cost-effective, high volume TSS production for mobile and wireless or High
performance TSS applications
volume ramp
qualification
development
study
time
Thomas R Toms July 16, 2008
PAGE 6

ITRS Draft Specification for 3D
30K
TSV/mm 2 vs. Year at 1% TSV KOA
Source:
INTERNATIONAL TECHNOLOGY ROADMAP
FOR SEMICONDUCTORS
2007 EDITION
INTERCONNECT page 46
TSV count
25K
20K
15K
10K
5K
Year:
1315 – 3248 TSV/mm 2
Small TSV
Large TSV
2007 2008 2009 2010 2011 2012 2013 2014 2015
Acceptable TSV Densities
Thomas R Toms July 16, 2008
PAGE 7
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A TSS case study
What impact does the TSV type, TSV pitch, # of tiers, TSV farm size, TSV
size, bonding order, Metallization layers and T2T bonding pitch have on
the COO and Yield
Factors
TSV 1 st or Last
Power delivery (PDN)
A single supply, Number of TSS tiers, intra-tier I*R losses and TSV I*R losses
External I/O count and Si tier size
For this study the I/O count was fixed at 400
The number of T2T signals (non-power/ground)
Via last - 200 (the approximate I/O count for two 64 bit channels of DDR1 memory)
Via 1 st - 2500 (arbitrarily selected)
The Si tier size
Base tier size of 50 – 100mm 2
Thomas R Toms July 16, 2008
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TSV selection
TSV Keep Out Area (KOA) and availability
Via Last
Via 1 st
6000
150
KOA (
(µm 2 /TSV)
5000
4000
3000
2000
1000
125
100
75
50
25
0
Today 2009 2010
0
Today 2010
200mm Wafers
300mm Wafers
200mm Wafers 300mm Wafers (50um) 300mm Wafers (25um)
Thomas R Toms July 16, 2008
PAGE 9

Tier Growth
12%
Tier Growth
9%
6%
3%
0%
AF2AF no RDL AF2BF no RDL AF2AF with RDL AF2BF with RDL
Via 1 st is the reasonable selection for the
TSV based on the area impact
Via Last Via 1st
RDL reduces PDN lateral resistance by 90%
Via Last 2010 300mm Wafer
400 I/O (TSV farm 1x1)
200 T2T (TSV farm 1x1)
Via 1 st 2010 300mm Wafer (50µm)
400 I/O (TSV farm 2x2)
2500 T2T (TSV farm 1x1)
Thomas R Toms July 16, 2008
PAGE 10

Power & Ground in a TSS stack
How many TSV and T2T connections are required to distribute
power and ground
PDN TSV Requirements
TSV I*R pitch
TSV farm pitch
200 µm
Intra-Tier I*R pitch
TSV farm density
50/mm 2
TSV farm density
Low Tier Count High
Thomas R Toms July 16, 2008
PAGE 11

Tier to Tier connection pitch
T2T Pitch(µm)
40
30
20
T2T Pitch
ITRS Draft Specification for 3D (larger pitch)
Pitch for 1:1 match of large TSV KOA count (page 7)
Current T2T
Application
needs
Future
needs
10
Year:
2007 2008 2009 2010 2011 2012 2013 2014 2015
Thomas R Toms July 16, 2008
PAGE 12
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Factors that impact Tier thickness
• TSV 1 st with a constant aspect ratio
Resistance
Capacitance/KOA
Cost
Yield
• Thin tier handling
Cost
Yield
?
?
?
? ? ?
?
?
25µm?
There are various “?” that must be determined before the
optimum tier thickness can be selected
To be conservative Qualcomm is targeting thicker (50 µm
minimum) vs. the thinner tier that shall be available for
TSS products
50µm?
Thickness
Thomas R Toms July 16, 2008
PAGE 13

TSS cost models
Qualcomm has access to several TSS cost models but all lack two key inputs
COO – What are the equipment throughputs and consumables vs. TSS feature
specifications and time
Yield – The yield function of TSS processes and time
What is the TSS system COO in 2 – 3 or more years
Process COO
Acceptable COO
Time
TSS Process Options
A B C D
Time
Process Yield
100%
98%
96%
94%
92%
90%
Thomas R Toms July 16, 2008
PAGE 14

Feature size vs. Throughput and Yield
• COO & Yields for TSS
Function of feature size
Standardization
• Qualcomm has defined TSS feature size to standardize, improve throughput
and yields; while, meeting our anticipated µ-architecture needs
• Qualcomm TSS feature size requirements are relaxed compared to the data in
the 2007 ITRS 3D targets by
Tier Thickness 2 – 10X
TSV pitch/size 4 – 9X
T2T pitch 7 – 10X
Thomas R Toms July 16, 2008
PAGE 15

Issues revealed by the TSS case study
• ITRS 3D feature projections are too aggressive for the needs of an early adoption of TSS
in mobile and wireless markets
Are these aggressive requirements driving higher COO?
Are the requirements based on niche or mainstream applications needs?
• Key Questions to be answered in relaxing the TSS requirements
Will more relaxed targets reduce the COO?
Improve yields to an acceptable level for HVM?
Will relaxed requirements accelerate the adoption of TSS?
• Equipment, materials and processes gaps that need to be closed for successful, costeffective,
high volume production
Predictive COO and Yield information for use in the TSS cost models – process
HVM 300mm Die to Wafer alignment – equipment
Low temperature Tier to Tier bonding – material and equipment
Backside metallization on thinned TSS Si wafer – process and equipment
More in backup
Thomas R Toms July 16, 2008
PAGE 16

Concluding remarks
To improve the situation Qualcomm has defined a set of requirements for TSS
with our Foundry and SAT partners. These define both short term and longer
term targets for adoption of TSS technology in the mobile and wireless markets.
It is our belief that having defined requirements for TSS will assist the industry
in closing the gaps for successful, cost-effective, high volume production in the
near future.
Thomas R Toms July 16, 2008
PAGE 17

Contributors
I would like to than the following people at Qualcomm who helped put this
presentation together
Arvind Chandrasekaran
Sam Gu
Rakesh Kumar
Matt Nowak
Riko Radojcic
Urmi Ray
Thomas R Toms July 16, 2008
PAGE 18

Thank You
PAGE 19

Backup material
Thomas R Toms July 16, 2008
PAGE 20

Calculation of TSV count for 1% tier growth
KOA assumptions
TSV KOA = 2X TSV area
TSV KOA shape is circular
Ignores standard cell step size
TSV KOA = 0.5 * pi * (TSV diameter) 2
1% of 1mm 2 = 10,000µm 2
TSV count = 10,000/TSV KOA
For example using the 2008 ITRS TSV diameters:
TSV diameter: 1.4 – 2.2µm
Small TSV KOA = 0.5 * pi * (1.4µm) 2 = 3.078µm 2
Small TSV count = 10000/3.078 = 3248
Large TSV KOA = 0.5 * pi * (2.2µm) 2 = 7.603µm 2
Large TSV count = 10000/7.603 = 1315
Thomas R Toms July 16, 2008
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Calculation of Tier to Tier connection pitch
The number of T2T bonds that are required for the PDN is equivalent to the number
of TSV farms (~50/mm 2 )
A reasonable tier size for the 2500 T2T I/O signals of 50 – 100mm 2
Average T2T I/O density would be 25 – 50/mm 2
Sum the PDN and I/O to get an average T2T connection density of 75 – 100/mm 2
To provide floor planning flexibility and to minimize routing distances increase the
T2T density by 8-12
Resulting T2T pitch 28.8 – 40.8µm
In the future (3 – 6 years) it is anticipated that
2D Si process continues to scale
The µ-architecture changes to take greater advantage of TSS
Results in the T2T densities and I/O counts increase
Anticipate a heterogeneous TSS stack shall require another 4-8 fold increase in the T2T
density
Resulting T2T pitch 10.1 – 20.4µm
Thomas R Toms July 16, 2008
PAGE 22
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300mm Equipment/Process/Materials Gaps Table
High – Level Module
Equipment
Process
Material
Wafer crack during demount
Adhesive max temperature
Carrier (Mount/Demount)
Lead time, cost
µbump
conformality
Carrier material selection
Number of carrier cycles
Adhesive residue
TSV Contact preparation
CMP
PECVD
TTV process optimization
Passivation material
(stress/temperature)
RDL
BF Alignment
Stepper resolution
Planarity
Polymer temperature
T2T Bonding
Bonding accuracy
Under fill
Material stack up
TSS stack assembly
TSS stack bumping
Thomas R Toms July 16, 2008
PAGE 23
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