VLSI Engineering - UCSC Extension Silicon Valley

SiliconValley 

KNOWLEDGE YOU PUT TO WORK 

VLSI 

Engineering 

PROGRAM SUMMARY 

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Silicon Valley's Most Comprehensive 

IC Curricuum 

UCSC Extension in Silicon Valley offers the VLSI 

(Very Large Scale Integration) Engineering Certificate 

Program for professionals working in the integrated 

circuit, ASIC, semiconductor, EDA, device and system 

industries. With more than 20 cutting-edge courses, 

our VLSI curriculum includes the most complete 

integrated circuit courses of any school in the area. 

Lab-Based Instructional Environment 

At our new Santa Clara facility, students build 

practical experience using the latest EDA tools on 

Linux, in our fully upgraded state-of-the-art VLSI Lab. 

Our courses do not just focus on the tools but also 

offer an overall understanding of the design 

methodology and flows. Studying here, you will 

benefit from: 

• Compute server with quad-core CPU and 

high memory 

• Real EDA tools used by professionals in the field 

• Labs integrated with lectures 

• Real-world test cases for practice 

• Lab access whenever our building is open 

Keep Pace with Industry Developments 

Our instructors are working professionals who are 

experts in their disciplines, so course content reflects 

what is really going on in the industry. They share 

real-world, applied knowledge to help you expand and 

solidify your skills. We cover hardware specification, 

logic design, verification, synthesis, physical implementation, 

circuit design, testing and manufacturing 

integrated circuit products. 

Benefits of Studying at UCSC Extension 

• Hands-on learning of marketable skills 

• Up-to-date knowledge of best design practices 

• UC-quality curriculum 

• Convenient location and schedule 

Who Should Attend This Program 

We offer the opportunity for individuals to acquire 

skills in multiple areas, expand expertise and advance 

their careers. 

Technical professionals can count on us to provide 

the training needed to achieve cost, schedule and 

customer requirements on the job. 

Entry level engineers can acquire hands-on 

knowledge in VLSI development while networking 

with fellow students and teaching staff. 

Free Program Overviews 

Embedded Systems 

and VLSI Engineering 

This free event is a program overview covering 

two certificate programs. The VLSI Engineering 

Certificate Program is for professionals working 

in the integrated circuit, ASIC, semiconductor, 

EDA, device and system industries in Silicon 

Valley. The Embedded Systems Certificate 

Program is for professionals working in the 

hardware and system design fields, with 

courses in DSP, DV, embedded programming, 

hardware architecture, and board design. 

Presenters will discuss new developments in 

both areas. Curriculum and recommended 

course sequence will also be presented. This 

course is offered twice a year. 

Course Number 20544 

Embedded Systems and 

VLSI Engineering Open House 

This free event is an informal information session 

for new or returning students who are interested 

in the Embedded Systems and VLSI Engineering 

certificate programs. The evening includes a 

short presentation with an overview and highlights 

of new courses, followed by an open-floor 

discussion with questions and answers of 

general interest.The program staff and program 

coordinator (or senior instructor) will be 

available to answer individual questions about 

specific courses, or provide recommendations 

for suggested course sequence. This is an 

opportunity to receive course counseling for 

the coming quarters. 

This information session is offered once a year. 


ucsc-extension.edu/EngTech 

Copyright © 2010 The Regents of the University of California. All rights reserved. Not printed or mailed at state expense. 611796-3-08 (3/15/10)

U C S C E X T E N S I O N I N S I L I C O N V A L L E Y — V L S I E N G I N E E R I N G 

VLSI Engineering Certificate 

Course Descriptions 

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Certificate Requirements 

To obtain the Certificate in Embedded Systems, you 

must successfully complete a total of 14 units. 

Prerequisites 

Prospective students should review prerequisites 

that apply to individual courses. 

Recommended Course Sequence 

Courses may be taken in any order. 

Only one course may be shared between two 

Engineering and Technology certificate programs 

unless otherwise noted. 

Course 

14-unit minimum (Units) Number 

Design Methodology 

VLSI and ASIC Design, Introduction..........(1.5) ......3497 

Logic and Functional Design 

Logic Synthesis, Introduction ....................(3.0) ......4377 

Practical Logic Design by Example ..........(3.0) ....22607 

Practical DFT Concepts for ASIC: 

With Nanometer Test Enhancements........(3.0) ......5373 

Embedded System-on-Chip Design 

Using Verilog ............................................(3.0) ....21959 

IO Concepts and Protocols: PCI Express, 

Ethernet, and Fibre Channel ....................(3.0) ....22177 

SystemVerilog and Verification 

Design Simulation with Verilog 

and System Verilog ..................................(3.0) ......6932 

Digital Design Using Verilog ....................(3.0) ......0764 

SystemVerilog for Logic Synthesis 

and Simulation..........................................(3.0) ....20095 

SystemVerilog Assertions 

for Design Verification ..............................(3.0) ....20062 

Analog IC Design, Introduction 

This course introduces analog IC design fundamentals 

including single/multiple-transistor amplifiers, current 

mirrors, current/voltage reference, output stages, 

frequency response, feedback, stability, noise, 

nonlinearity, and mismatches. Transistor models and 

CAD tools for analog design will also be covered. 

Students will gain a basic understanding of analog 

IC design and become familiar with circuit analysis 

and simulation tool flow.The fundamentals presented 

in this course prepare students to tackle advanced 

analog IC topics such as Op-amp, PLL, ADC and DAC. 


ASIC Physical Design Using IC Compiler 

This course is an introduction to ASIC physical design 

and covers the basics of the floorplanning, place 

and route, RC extraction and layout verification flows. 

The course includes test case exercises in the lab. 

Topics include flat and hierarchical floorplanning, 

placement, physical synthesis, clock-tree synthesis, 

routing, post-route optimization, static timing analysis, 

and timing closure techniques. Students will acquire 

hands-on experience with the backend physical 

design flows from a synthesized netlist all the way 

to layout completion ready for ASIC chip tapeout. 


SystemVerilog for Advanced 

Design Verification....................................(3.0) ....18966 

ASIC Physical Design, Advanced 

Mixed-signal IC Verification 

with Verilog-AMS......................................(3.0) ....22183 

Physical Design and Timing Closure 

ASIC Physical Design Using 

IC Compiler ..............................................(3.0) ......4436 

ASIC Physical Design, Advanced ..............(3.0) ......0634 

Static Timing Analysis Using 

PrimeTime ................................................(3.0) ......4775 

Circuit Design 

Low-Power Design of Nano-Scale 

Digital Circuits ..........................................(3.0) ....21941 

Analog IC Design, Introduction ................(3.0) ......3799 

Mixed-Signal IC Design ............................(3.0) ......1999 

PLL and Clock/Data Recovery Circuits ......(3.0) ......2283 

Digital Baseband Communications: 

Fundamentals of PHY Transmission..........(3.0) ....22628 

Technology, Manufacturing and Test 

IC Manufacturing, Introduction ................(1.5) ......2496 

Renewable Energy....................................(3.0) ....22410 

This course covers the advanced topics of ASIC 

front-to-back design automation. It introduces 

backend design and low power techniques in 

65nm technologies and beyond.Topics include floorplanning 

considerations, physical design synthesis, 

timing closure after detail route, RC extraction 

and static timing analysis, congestion analysis, IR 

drop, signal integrity, power planning and analysis. 

Instructor will share his extensive experience in 

ASIC implementation over many generations and 

will also provide lab exercises for students to 

practice some techniques learned in class. 


Design Simulation with Verilog 

and SystemVerilog 

This course covers basic Verilog language. It introduces 

students to the digital simulation process with 

hands-on exercises using the simulation tool in the 

lab. Discussions cover simulation techniques such as 

coding style, event ordering, delta cycle debugging, 

zero width glitch, race conditions, time slices, 

conditional compilation, simulation performance 

and code coverage. The second half of the course 

introduces the SystemVerilog language including 

syntax and semantics. 


Check our catalog for new 

and advanced courses. 



Digital Design Using Verilog 

Logic Synthesis, Introduction 

PLL and Clock/Data Recovery Circuits 

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This course prepares students for designing logic 

circuits with the Verilog Hardware Description 

Language and covers examples from simple gatelevel 

models to more complex RTL/behavioral 

models. The course will highlight structural and 

functional modeling techniques, and verification 

methods using Verilog HDL. Students write Verilog 

code for various hierarchical Verilog models and 

develop test benches and simulate their designs. 

The course introduces concepts to describe hardware 

using a language instead of drawing schematics, 

and prepares students for courses in design, synthesis, 

testability and verification. Other topics include 

modeling tips and techniques for debugging, 

synthesis, and high-performance simulation. 


Embedded System-on-Chip Design 

Using Verilog 

This course introduces the SOC (System-on-Chip) 

with a focus on implementing embedded hardware 

system using Verilog. The course covers the SOC 

concept and the basic embedded system architecture, 

then discusses combinational and sequential designs 

in datapath and control path with clocked timing 

methodology. Students learn the integrated design 

of embedded memories, customized microcontroller 

core and I/O interface, the design methodology of 

RTL flow, synthesis, optimization and Design for 

Test on chips. 


Introduction to IC Manufacturing 

This course presents an overview of the process 

used to manufacture integrated circuits and the 

various steps involved in the fabrication, assembly 

and testing of complex VLSI devices. Each step of 

the process is discussed in detail as to its purpose 

and implementation as well as the real-world 

and technical problems associated with the step. 

The interrelationships between these steps are 

also covered. Every step from tape-out to volume 

production is discussed. 


This course outlines various concepts of logic 

synthesis. Starting from the basics of synthesis, the 

course explains the Synopsys tools and their use 

in synthesizing high-level language into gates. 

It also covers various options such as partitioning, 

design, gate-level optimization, time/area constraints 

and library management. This course is intended for 

design engineers with some knowledge of hardware 

description languages such as Verilog HDL or VHDL. 

It is a lab-based course with hands-on exercises. 


Low-Power Design of Nano-Scale 

Digital Circuits 

This course introduces advanced topics in nano-scale 

(below 90nm) VLSI device and circuit design. Highperformance 

and low-power design issues in 

modern and future nano-scale CMOS technologies 

are discussed in detail. Students will learn the 

low power design approaches and techniques at 

different levels of abstraction. New design techniques 

will be introduced to deal with nano circuit 

designs under excessive leakage and process 

variations. Several non-classical CMOS devices for 

circuit design in such technologies will be explored. 

Prospects of future non-silicon nanotechnologies 

will be reviewed. 


Mixed-Signal IC Design 

This course helps students understand basic analog 

circuits and systems, and problems encountered when 

analog circuits share substrate with digital circuits. 

Students also are made aware of precautionary 

measures and techniques used to circumvent these 

problems. Topics include: MOS transistors, basic 

analog building blocks, phase-locked-loop circuits, 

sample and hold circuits, comparator design, A/D 

and D/A converters, and layout considerations in 

mixed-signal circuits. This course is intended for 

practicing engineers and design managers who 

want to understand analog circuit and layout 

techniques in mixed-signal IC design. 


Phase-locked-loop (PLL) circuits are used extensively 

in system and chip designs for frequency 

multiplication, data extraction, and re-timing 

purposes. This course provides students with the 

knowledge required for analysis and design of PLL 

circuits and their applications in clock and datarecovery 

circuits. The instructor will discuss various 

components involved in the design of a PLL circuit. 

Topics include transceiver design, high-speed I/O, 

ring and LC oscillators, charge-pump PLL, practical 

issues at transistor-level design, noise and jitter in 

PLL, delay-locked loop, frequency multiplier, and 

clock and data recovery circuits. 


Practical DFT Concepts for ASICs: 

With Nanometer Test Enhancements 

This hands-on course first builds a solid foundation 

in scan-based design, testing, and pattern generation 

(ATPG), using Synopsys RTL DRC, DFT Compiler and 

TetraMAX. It then explores nanometer enhancements 

and recent trends in testing, including bridging and 

delay fault models, BIST logic, source-synchronous 

clocking to overcome I/O bandwidth limitations on the 

ATE, physical design modifications such as scan-chain 

reordering, and digital (IEEE 1149.1) and on-chip 

analog (1149.4) boundary-scan. This course is ideal 

for IC designers and test engineers wanting to stay 

current with emerging test trends and tools. 


Practical Logic Design By Example 

This course teaches the logic design of real-world 

digital systems. The emphasis is on how to break 

down a complex digital design specification, logic 

design of the sub-designs, and integration into 

the top level design, validated with respect to the 

specification. The course goes deep into the logic 

design of common to re-useable sub-systems. There 

will be a guided project to design a complete digital 

system from specification to validation. Students 

will also learn the concepts of designing for speed, 

power, area, testability, cost, and physical design. 


IO Concepts and Protocols: 

PCI Express, Ethernet, and Fibre Channel 

This course focuses on IO technologies and walks 

students through the complexities of IO subsystems 

in modern computers, and the networking and 

storage subsystems to which they are attached. 

After an introduction to the basic concepts of IO, 

we will delve into the details of PCI Express, Ethernet 

and Fibre Channel. Discussion will include operation 

and protocols and an exploration of how these 

technologies work. We will follow an application’s 

IO request all the way from the system call, to when 

the data actually makes it out the wire. 


Mixed Signal IC Verification 

with Verilog-AMS 

With growing product functionality, more mixed-signal 

designs are emerging. This course is intended to 

provide students with mixed-signal IC design and 

verification experience. Students will learn the 

fundamental concepts via practical application and 

hands-on experience. The course begins with digital 

and analog design concepts, Verilog and Verilog- 

AMS basics, and mixed-signal interfaces. It will also 

cover simulation techniques, debugging tips, behavior 

modeling, system-level integration, and verification 

strategies. Students will develop a complex mixedsignal 

design using Verilog-AMS in the lab, and then 

learn how to verify it. 


Renewable Energy 

This survey course provides engineers, managers 

and technical professionals with a foundation in 

the basic principles of renewable energy and its 

associated industries. In preparation for advanced 

study, or to pursue new careers or ventures, students 

will gain a solid understanding of the fundamentals, 

opportunities, challenges, and limitations of each of 

the seven major forms of clean renewable energy: 

solar, wind, biomass, hydro, ocean (tidal, wave) 

and geothermal. The course will also cover energy 

industry management and policy issues, such as 

new solar, wind companies, carbon emissions, 

California Solar Initiative, and the Kyoto Protocol. 




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Static Timing Analysis Using PrimeTime 

This course introduces various approaches to 

Static Timing Analysis (STA). PrimeTime is the gold 

standard in timing closure and sign-off. In this 

course, PrimeTime is used in our VLSI lab, where 

its application to the entire design flow (from postsynthesis 

gate level design to post-route design) 

is examined. Topics include constraints, assertions, 

exception definition, delay calculation, and 

advanced timing analysis features. Design engineers 

completing this course will be able to perform 

Static Timing Analysis using PrimeTime in several 

phases of the integrated circuit design process. 


SystemVerilog Assertions 

for Design Verification 

As more functionality is packed into denser chips, 

verification is becoming a daunting task. Leading 

design and verification teams are using the power 

of assertions to manage their verification challenge. 

With the ratification of SystemVerilog language by 

IEEE (IEEE 1800), there has been standardization 

of assertion language. This course teaches students 

details from language constructs to assertion coding 

guidelines to practical examples of how to use 

assertions in their verification task. The course 

also covers methodology choices and introduces 

assertions in formal context. 


SystemVerilog for Advanced 

Design Verification 

This course prepares students for designing and 

implementing coverage-driven, constrained-random 

verification environments using the latest techniques 

for testing complex integrated circuits. The course 

is based on the advanced verification features of 

the SystemVerilog hardware design and verification 

language. The latest architectural methodologies 

and techniques available for verification are covered. 

Concepts introduced in class are reinforced in the 

UCSC Extension SystemVerilog lab where students 

implement a verification environment for an audio 

application. Topics include hardware verification 

evolution and test-bench automation methodology; 

random, constrained, and directed testing; testbench 

re-use; constrained randomization stimulus 

and measuring coverage; and layered test-bench 

and object-oriented design. 


SystemVerilog for Logic Synthesis 

and Simulation 

For hardware designers, SystemVerilog offers 

new capabilities in synthesis, RTL assertions, and 

pre-silicon emulation modeling. SystemVerilog is 

far more capable than just Verilog coupled with a 

++ operator. This lab course calls upon students to 

write SystemVerilog code and synthesize the logic 

at 90 nm. It introduces hardware engineers to the 

use of struct, enum, and 2- or 3-D arrays. In the 

final lab, students synthesize a video-acquisition 

module using an “interface” unit for on-chip busing. 

Students will also embed design assertions into 

their RTL code, and then simulate at the block level. 


VLSI and ASIC Design, Introduction 

This course provides the fundamentals of VLSI 

and ASIC design, and an overview of the different 

ASIC architectures, design methodologies and 

design tools. Topics include an introduction to 

ASIC architecture; ASIC design flows; CAE tools 

and requirements for design entry, simulation and 

layout; packaging technology and related issues; 

simulation and sign-off requirements; test and 

testability; and guidelines for evaluating and 

selection of ASIC vendors. 


About UCSC Extension 

in Silicon Valley 

The vital learning community at 

UCSC Extension in Silicon Valley 

is well known for its collegial 

atmosphere and rigorous 

preparation. Our faculty of 

expert practitioners teaches 

state-of-the-art solutions to the 

everyday problems confronting 

technology professionals working 

in Silicon Valley. The professional 

education programs we offer 

build expertise, open doors to new 

opportunity, and deliver tangible 

value. Our broad portfolio of 

open-enrollment courses and 

certificates, affordable pricing, 

experience-based instruction, 

and central location in Silicon 

Valley help turn jobs into careers.

VLSI Engineering - UCSC Extension Silicon Valley

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