JEDEC STANDARD

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JESD79E Page 28 CK CK COMMAND READ NOP BST NOP NOP NOP ADDRESS Bank a, Col n CL = 2 DQS DQ DO n CK CK COMMAND READ NOP BST NOP NOP NOP ADDRESS Bank a, Col n CL = 2.5 DQS DQ DO n CK CK COMMAND READ NOP BST NOP NOP NOP ADDRESS Bank a, Col n CL =3 DQS DQ DO n DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n DON’T CARE Figure 15 TERMINATING A READ BURST - REQUIRED CAS LATENCIES
JESD79E Page 29 CK CK COMMAND READ BST NOP WRITE NOP NOP ADDRESS Bank, Col n Bank, Col b CL = 2 tDQSS min DQS DQ DO n DI b DM CK CK COMMAND READ BST NOP NOP WRITE NOP ADDRESS Bank, Col n Bank, Col b CL = 2.5 tDQSS min DQS DQ DO n DI b DM CK CK COMMAND READ BST NOP NOP WRITE NOP ADDRESS Bank, Col n Bank, Col b CL = 3 tDQSS min DQS DQ DO n DI b DM DON’T CARE DO n (or b) = Data Out from column n (or column b) Burst Length = 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data In elements are applied following DI b in the programmed order Figure 16 READ TO WRITE - REQUIRED CAS LATENCIES
Page 1 and 2: JEDEC STANDARD Double Data Rate (DD
Page 3: PLEASE! DON’T VIOLATE THE LAW! Th
Page 6 and 7: JEDEC Standard No. 79E -ii-
Page 8 and 9: JESD79E Page 2 CONTENTS Features ..
Page 10 and 11: JESD79E Page 4 (x4) (x8) 1 2 3 7 8
Page 12 and 13: JESD79E Page 6 TABLE 2: PIN DESCRIP
Page 14 and 15: JESD79E Page 8 The Mode Register mu
Page 16 and 17: JESD79E Page 10 CK CK COMMAND READ
Page 18 and 19: JESD79E Page 12 COMMANDS Truth Tabl
Page 20 and 21: JESD79E Page 14 TRUTH TABLE 3 - Cur
Page 22 and 23: JESD79E Page 16 TRUTH TABLE 4 - Cur
Page 24 and 25: JESD79E Page 18 Power Applied Power
Page 26 and 27: JESD79E Page 20 PRECHARGE The PRECH
Page 28 and 29: JESD79E Page 22 Reads READ bursts a
Page 38 and 39: JESD79E Page 32 T0 T1 T2 T3 T4 T5 T
Page 42 and 43: JESD79E Page 36 CK CK T0 T1 T2 T3 T
Page 50 and 51: JESD79E Page 44 T0 T1 T2 T3 T4 Tn T
Page 52 and 53: JESD79E Page 46 TABLE 7: AC OPERATI
Page 54 and 55: JESD79E Page 48 - DDR266A (133 MHz,
Page 56 and 57: JESD79E Page 50 TABLE 11: ELECTRICA
Page 58 and 59: JESD79E Page 52 TABLE 12: AC TIMING
Page 60 and 61: JESD79E Page 54 SYSTEM CHARACTERIST
Page 62 and 63: JESD79E Page 56 TABLE 22. Clamp V -
Page 64 and 65: JESD79E Page 58 k. Table 15 is used
Page 66 and 67: JESD79E Page 60 TABLE 23: Full Stre
Page 68 and 69: JESD79E Page 62 TABLE 24: Weak Driv
Page 70 and 71: JESD79E Page 64 tDQSH tDQSL DQS tDS
Page 72 and 73: JESD79E Page 66 t CK t CH t CL CK (
Page 74 and 75: JESD79E Page 68 CK ( ( ( ( CK ) ) )
Page 76 and 77: JESD79E Page 70 t CL t IH t IS t IH
Page 78 and 79: JESD79E Page 72 t CK t CH t CL CK C
Page 80 and 81: JESD79E Page 74 t CK t CH t CL CK C
Page 82 and 83: JESD79E Page 76 t CK t CH t CL /CK
Page 84:
JESD79E Page 78
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JEDEC STANDARD

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