Digital IC Design

Digital IC Design
Tsung-Chu Huang
Department of Electronic Engineering
National Changhua University of Education
Email: tch@cc.ncue.edu.tw
2004/12/07
T.-C. Huang, NCUE Fall 2004
TCH
NCUE
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Introduction to Memory
1. Development of Memory Industry
2. Taxonomy of Memory
3. Standardization
4. CCD
5. SRAM
6. DRAM
7. ROM
8. CAM
9. Memory Hierarchy
10.Timing Diagram
11.Factors Lowing Down a Memory System
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Moore’s Law on Transistor Counts
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Units of Memory
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Moore’s Law on Memory
10 20 bits
10 17 bits
1985 2000
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MOS Memory Learning Curve
$10
−3
$10
−4
$10
−5
12
13
14
15
10 bits 10 bits 10 bits 10 bits
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Taxonomy
1. by Access Structure
1. Random Access Memory (RAM)
2. Serial Access Memory (SAM)
3. Content Access Memory (CAM)
2. by Alterability
1. RAM: R/W Memory, SRAM, DRAM, CCD
2. ROM
3. EPROM
4. EEPROM
5. Filed Alterable ROM, e.g., Flash
3. by Device: BJT, NMOS, CMOS, CCD
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Basic CCD
φ41
φ1
φ12
φ2
φ23
φ3
φ34
φ4
φ 41 φ1
φ12
φ2
φ23
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Basic Static RAM (SRAM)
Bit Line
Bit Line
Word Line
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Basic SRAM Architecture
C
M
= 2
Columns
N
Row Address Buffer
N
N
Row Decoder
R
Memory Array
w 0
w R−1
WL
BL
b b
0
0 b b
c−1
c− 1
R
N
= 2
Rows
Din
Dout
R /W
CS
Control
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Column Decoder
M
Column Address Buffer
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M
M
SA
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Amplification of SA
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SRAM
Circuitry
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Basic SRAM Architecture
Row/Column
Multiplexer
And Buffer
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A Simple Sense Amplifier (SA)
V DD
Bit
Bit
CS
TCH
Typically, the SA must be sensitive enough to read about 10mV.
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Basic SRAM Architecture
An Embedded SRAM
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Standard DRAM Development
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Related Techniques of DRAM
1. EDO: Extended Data Output
+ Fast Page Mode
2. BEDO: Burst EDO (4 addr. per burst)
+ Burst Mode: 4 Addresses per burst
3. DDR: Double Data Rate Technique
4. SDRAM: Synchronous DRAM
5. RDRAM: RAMBus DRAM
6. VDRAM: Video RAM
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Op Frequency vs. Customizability
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Write
Historical Evolution of DRAM
Read Select
R/W Select
Write
Read
Read
Write Select
Read Select
R/W Select
Data
Data
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Write Select
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Historical Evolution of DRAM
Basic Planar and Trench DRAM Cells
Planar Cell
Bit
Word
Trench Cell
Bit
Word
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DRAM Cylindrical Stacked Cells
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Basic ROM Architecture
Bit Line
Word Line
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Typical Storage Hierarchy
FF
Register
L1 Cache
SRAM
L2 Cache
SRAM
DRAM
Main Memory
Archive I
DRAM
Magnetic disk
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Archive II
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Optical disk
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Basic Standards of Timing Diagrams
Basic I/O Signals
1. CS: Chip Select
2. Adr.: Address
3. WE: Write Enable
4. OE: Output Enable
5. Di: Data-input
6. Do: Data-output
7. RAS: Row Address Strobe
8. CAS: Column Address Strobe
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Basic Standards of Timing Diagrams
Approaches
1. JEDEC (Joint Electronics Device Engineering)
2. EIAJ
3. IEC
1. JEDEC Standard Timing Symbol
2. Order notes in parentheses
3. Causal Arrows
4. Description
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Basic Standards of Timing Diagrams
Example
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Write Cycle
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Factors Slowing Down Memory Sys.
Bus Contention
Ground Bounce
System Bandwidth
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Address-Multiplexed Read Timing
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Address-Multiplexed Write Timing
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Brief Introduction to Memory Test
Fault Model:
0 0 1 1 0
1 0 1 0 1
0 1 0 0 0
0 0 1 1 0
0 1 0 0 0
Basics:
⇓ w0 ⇓ r0
⇓ w1
⇓ r1
⇓ ( w1r
1w0r0)
Detailed in the Introduction to IC Test.
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