50~chapter 11 ams.pdf

Chapter 11 Exercise Solutions
11.1
The equivalent circuit with Ri, Ro, and RL is as follows.
∆V
A
x
o =101⋅
∆Vy
Vy
Vx
10K
10K
10K
100
Vi
100
50 (Ro)
100 (RL)
Therefore the open loop gain measure result is
A
o
100 Ri
R
V L
x =
× A×
× Vy
10K
+ 100 Ri
Ro
+ RL
∆V
∆V
x
y
1K (Ri)
(b)
100 Ri
R
=
× A×
L
10K
+ 100 R R + R
∆V
90 100
= 101 ×
x
= 101×
× 100×
= 60.1
∆V
10090 150
y
i
o
L
11.2
(a) ft = A×
f3 dB = 1000×
1KHz
= 1MHz
(b) Suppose that the maximal output voltage is Vmax then
SR
VMAX
≤
2πf
If Vmax=5V,
Fmax=31.8KHz
fMAX
=
2π
MAX
SR
VMAX
VLSI Test Principles and Architectures Ch. 11 – Analog & Mixed-Signal Testing – P. 1/5

11.3 (Ask student to check the definition first.)
∆V
5.2 − 4.9
(a) Load _ Regulation = 100% × o
= × 100% = 6%
V
5
o _ NOM
Max(
∆I
L ), Min(
Vi
)
∆V
5.15 − 4.9
(b) Line _ Regulation = 100% × o
= × 100% = 5%
V
5
o _ NOM
Max(
∆VI
), Max(
IL
)
(c) Drop out voltage is 5.8V. The minimum input voltage for Vout > 4.75V.
11.4
Solution A
Capacitor Voltage
Zener Diode
Max Iout
Min Cap Voltage
At Vc=7V
At Vc=14V
Solution B
7V ≤ VC ≤ 14V
10
VZD = 5.7V
+ ( VC
− 5.7V
) × , 5.83
≤ V ZD ≤ 6. 53V
90 + 10
V − 5.7V
I = CMin
oMax
× 100 , (all the current goes to the base)
90Ω
I ms
V V
oMax ×16.6
CMin = c −
(at maximal current after ripple
10000µ F
deducted)
V CMin = 6. 2V
I oMax = 0. 5A
(solve the above two equations)
V CMin = 13. 2V
I oMax = 0. 5A
(ripple is 0.8V at 0.5A output
current)
Max Output 14V-0.2V (VCE Sat) Minimun Output 6.2V-0.2V
Output Voltage (6V, 13.2V) 9 .6V ± 3. 6V
Line Regulation 7.2V
× 100% = 75%
9.6V
Load Regulation 6.8V
− 6.2V
× 100% = 6.25% (Vo=6.8V without load)
9.6V
Solution C Dropout voltage is 5V (AC) under 0.5A load.
VLSI Test Principles and Architectures Ch. 11 – Analog & Mixed-Signal Testing – P. 2/5

11.5
(a) 2.7V (2V + 0.7V)
(b) Once there is a positive bias of the diode, there is distortion. Hence, due to the nonlinear
characteristics of the diode, the distortion free input amplitude is 2V. In other words, the
diode is always reverse biased for distortion free.
11.6
(c) Require SPICE simulation. For V in = 2 .7V
× sinωt
, simulate the output waveform. Then,
transform the output waveform (integer number of cycles), into frequency domain by FFT.
Then, use (11.11) to find the SNR. Note that the result may be different for different diode
models.
(a)
(b)
(c)
I 1 A
V Leak µ
droop = = = 100V
CH
10nF
/ sec
1LSB =
10
1V
/ 2 = 1mV
, T = 0 .5 LSB / V = 5 s
T acq
holdMAX droop µ
−
VA × e τ V
V
≤ 0. 5LSB
, T
A
1
acq = τ × ln = (100 × 10nF)
× ln = 7. 6µ
s
0.5LSB
0.5mV
fmax = 1/( Tacq + TADC
) = 1/8.6µ s = 116KHz
.
(d) The leakage after 1us is
Hence, 1LSB=0.2mV.
n
Hence 2 ≤ 1V
/ 0.2mV
= 5000 ∴ n = 12
(e) Same as (c).
11.7
(a) The maximal slop of a sine wave is
For 1KHz, the maximal error is
For 1MHz, the maximal error is
(b) 1LSB=0.5mV, hence,
n
T
1 µ s × Vdroop = 0.1mV
= 0. 5LSB
0.1mV.
2 πf ×VA
Tjitter × 2πf
× VA
= 100 p × 2π
× 10 × 0.5V
= 0. 314µ
V
Tjitter × 2π
f × VA
= 100 p × 2π
× 10 × 0.5V
= 0. 314mV
× 2π f × V ≤ 0. mV , f 1. 59MHz
jitter A 5
max =
(c) For 1KHz, 2 ≤ 1V
/ 0.314µ
V = 3.184×
10 ∴ n = 21
n
For 1MHz, 2 ≤ 1V
/ 0.314mV
= 3.184×
10 ∴ n = 11
6
3
3
6
11.8
Code 000 001 010 011 100 101 110 111
Frequency 80 163 159 149 140 135 130 68
DNL -0.38 0.27 0.24 0.16 0.09 0.05 0.02 -0.47
INL -0.38 -0.11 0.13 0.29 0.38 0.43 0.45 -0.02
VLSI Test Principles and Architectures Ch. 11 – Analog & Mixed-Signal Testing – P. 3/5

f avg
= 1024 /8 = 128
The INL for code (111) should be zero. The nonzero is because of the rounding.
11.9
Transfer Curves
3
f ×
16
Histograms
3
f ×
16
3
f ×
16
f
16
f ×
14
16
f ×
14
11.10
(a) (b) (c)
(f) for (d), INL=4LSB
7
i
16
For (e), INL = ∫ 0.5×
sin( π ) = 2×
0.5×
16
π
0
(d)
(e)
(a)
(b)
7
i
16
DNL = 0 .1×
16 = 1. 6LSB
, INL = ∫ 0.1×
sin( 2π
) = 2×
0.5×
= 2. 55LSB
0 16
2π
Offset = 0 .1×
16 = 1. 6LSB
, Gain Error=0
(c) Same as (a)
11.11
(a)
(a)
(b)
VLSI Test Principles and Architectures Ch. 11 – Analog & Mixed-Signal Testing – P. 4/5

(b)
(a)
y
y
11
12
I
=
V
1
I
=
V
1 V2
= 0
1
2 V1
= 0
y
y
21
22
I
=
V
2
I
=
V
1 V2
= 0
2
2 V1
= 0
H P1 P2 P3 P4
y11 Vs/Im GND GND GND
y12 Im GND Vs GND
y21 Vs GND Im GND
y22 GND GND Vs/Im GND
z
11
V
=
I
1
1 I2
= 0
V
1 I2
= 0
z
1
2
12 = z22
=
I2
I
I 0 2
1=
I1=
0
H P1 P2 P3 P4
y11 Is/Vm GND Open GND
y12 Vm GND Is GND
y21 Is GND Vm GND
y22 Open GND Is/Vm GND
g
g
11
12
I
=
V
1
I
=
I
1 I2
= 0
1
2 V1
= 0
z
g
g
21
21
22
V
=
I
V
2
V
=
V
2
V
=
I
1 I2
= 0
2
2 V1
= 0
H P1 P2 P3 P4
g11 Vs/Im GND Open GND
g12 Im GND Is GND
g21 Vs GND Vm GND
g22 GND GND Is/Vm GND
VLSI Test Principles and Architectures Ch. 11 – Analog & Mixed-Signal Testing – P. 5/5