48~chapter 10 bscan

VLSI Test Principles and Architectures Ch. 10 – Boundary Scan & Core-Based Testing – P. 1/10
Chapter 10 Exercise Solutions
10.1
The following is just an example for testing chips and interconnects on a board. One may adjust
the procedure based on the actual test requirement.
Test chips on board
1 The INTEST instruction is shifted into the IR of the chip(s) to be tested through TDI.
At the same time, the BYPASS instruction is shifted into the IR’s of those chips that
will not be tested at this test session. Note that several ICs might be tested concurrently,
depending on the results of test scheduling.
2 The contents of the instruction registers are updated and decoded by the decoders
associated with the IR’s of the four chips so as to generate the required control signals
to properly configure the test logic.
3 A test pattern (for the case only one chip is to be tested) or a series of test patterns (for
the case several chips are to be tested) are shifted into the input data registers through
TDI and then applied to the chip(s) to be tested.
4 The test response is captured into output data registers of the chip(s) under test.
5 The captured response is shifted out through TDO for observation and, at the same
time, a new test pattern can be scanned in through TDI.
6 Steps 3-5 are repeated until all test patterns are shifted in and applied, and all test
responses are captured and shifted out.
Note that appropriate values have to be applied to the TMS terminals of the chips (see the
state diagram of the TAP controller defined in the IEEE 1149.1 standard) to control the test
operations. After the testing procedure (Steps 1-6 shown above) for the chips currently being
tested is finished, the same procedure will be repeated for the remaining chips that are not
tested until all chips are tested.
Test interconnects between chips on board
1 The EXTEST instruction is shifted through TDI into the IR of the chip(s) between
which interconnects are to be tested. For the chips whose interconnects will not be
tested, the BYPASS instruction is shifted into their IR simultaneously.
2 The contents of the instruction registers are updated and decoded by the decoders
associated with the IR’s of the four chips so as to generate the required control signals
to properly configure the test logic.
3 A test pattern (for the case interconnects between only two chips are to be tested) or a
series of test patterns (for the case interconnects between several chips are to be tested)
are shifted into the (output) data register associated with the interconnects of one chip
through TDI and then are applied to and captured at the (input) data register of the
corresponding chip(s) associated with the interconnects. In order to effectively test

VLSI Test Principles and Architectures Ch. 10 – Boundary Scan & Core-Based Testing – P. 2/10
interconnects, specific test patterns such as walking one or walking zero sequences can
be used. The details of these sequences can be found in [1].
4 The captured response is shifted out through TDO for observation and, at the same
time, a new test pattern can be scanned in through TDI.
5 Steps 3-5 are repeated until all test patterns are shifted in and applied, and all test
responses are captured and shifted out.
Again, appropriate values have to be applied to the TMS terminals such that the test
procedure can be executed correctly. Similar test procedures can be applied to the chips to
test other interconnects.
10.2
The following calculation is based on the TAP controller state diagram shown in Figure 10.7. The
number of required test cycles to shift a 4-bit test instruction into the Instruction Register will be
1 (to run-test/idle) +
1 (to Select-DR-Scan) +
1 (to Select-IR-Scan) +
1 (to Capture-IR) +
1 (to Shift-IR)*4 +
1 (to Exit1-IR) +
1 (to Exit2-IR) +
1 (to update-IR) +
1 (to Select-DR-Scan) = 12
10.3
Assume the initial state of TAP is Select-DR-Scan and the number of input wrapper cells equals
that of output wrapper cells. The number of required test cycles to apply test patterns and
propagate test responses is calculated as follows.
The number of required test cycles to apply a test pattern is
1 (to Capture-DR) +
1 (to Shift-DR)*15 +
1 (to Exit1-DR) +
1 (to Update-DR) +
1 (to Select-DR-Scan) = 19
The number of required test cycles to observe test responses is
1 (to Capture-DR) +
1 (to Shift-DR)*15 +
1 (to Exit1-DR) +

VLSI Test Principles and Architectures Ch. 10 – Boundary Scan & Core-Based Testing – P. 3/10
1 (to Update-DR) +
1 (to Select-DR-Scan) = 19
Note that after the first test pattern is applied, applying test patterns and propagating test responses
can be executed simultaneously. Therefore, the number of required test cycles to apply test
patterns and propagate test responses will be
19 (applying the first test pattern) + 19*99 (applying test patterns and propagating test responses)
+ 19 (propagating the last test responses) + 1 (to Select-IR-Scan) + 1 (to Test-Logic-Reset) = 1921.
10.4
Yes. As described in this chapter, the SAMPLE operation can be completed by simply executing
the Capture operation (on the rising edge of TCK in the Capture-DR state). While the PRELOAD
instruction allows test data to be shifted into/out of the selected data register during the Shift-DR
state without causing interference to the normal operation of the internal logic as shown in Figure
10.10. The shifted data is then latched to the parallel output (R2) of the selected data registers (on
the falling edge of TCK in the Update-DR controller state). Since the states used to perform the
corresponding operations for these two instructions are not overlapped (i.e., Capture-DR state for
SAMPLE and Shift-DR as well as Update-DR states for PRELOAD), these two instructions can
be executed in one iteration of the seven states shown in the middle of Figure 10.7.
10.7
The errors in Figure 10.38 are the lack of the TMS control and a latch with negative level-sensitive
nature as shown in following figure. Without fixing these two errors, the Init_Memory signal
would not be activated before the occurrence of a transition in order to initialize the Hyst Mem in
time, which is intended to guarantee that a valid transition can be captured for every test vector as
described in the section pertaining IEEE 1149.6 Std.

VLSI Test Principles and Architectures Ch. 10 – Boundary Scan & Core-Based Testing – P. 4/10
○1 ○1
○2
10.8
Based on the structure of digital driver logic defined in IEEE 1149.6 Std., one can derive the AC
Test Signal in the timing diagram during EXTEST_PULSE instruction as shown in Figure 10.20.
Also the timing diagram during EXTEST_TRAIN instruction can be obtained in the same
manner, as shown in the figure below [IEEE 1149.6-2003]. Clearly one can see that sequential
transitions occur on the AC Test Signal line due to the EXTEST_TRAIN instruction when the TAP
State is in Run-Test/Idle.

VLSI Test Principles and Architectures Ch. 10 – Boundary Scan & Core-Based Testing – P. 5/10
10.9
The gate-level netlist can be obtained by synthesizing the RTL codes (e.g., Verilog) that describe
the functionalities of the wrapper cells using a commercial synthesis tool. Below are two
schematics of the netllist for the two WBC’s.
Gate-level netlist for 10.26(a)
Gate-level netlist for 10.26(e)
A comparison of functionalities, gate counts and control signals of these two cells is given in the
table below.

VLSI Test Principles and Architectures Ch. 10 – Boundary Scan & Core-Based Testing – P. 6/10
functionalities gate counts control signals
10.26(a) Shift and Capture 15
ShiftWR, CaptureWR and
mode
10.26(e)
Shift, Transfer, Update and
ShiftWR, TransferDR,
36
Capture
UpdateWR and CaptureWR
10.10
Figure (a): WBR cell connectivity around a core

VLSI Test Principles and Architectures Ch. 10 – Boundary Scan & Core-Based Testing – P. 7/10
Figure (b): Delay test sequence timing diagram
Figure (a) depicts a simplified example of an arrangement of an OR gate as a core and three
WC_SD2_CIO cells (the structure is shown in Figure 10.28) as WBR. The transfer, shift, and
capture signals are derived from TransferDR, ShiftWR, and CaptureWR.
Consider the scan order through 2 bits in each of the cells for terminals IN0, IN1, and OUT.
The cell provided for terminal OUT is configured to receive the opposite polarity value of the
IO_FACE signal from that applied to the other two cells. Also depicted are the logic values of a
delay test of three vectors applied to the OR gate inside the simplified core.
Figure (b) depicts a timing diagram of the delay test sequence. For ease of explanation, the
rising edges of WRCK are numbered sequentially.
The sequence begins with 6 data bits being shifted into the WBR. Following the Shift
operation, data in dff_1 and dff_2 (see the structure in Figure 10.28) of the wc_in0 wrapper cell are
both 0; dff_1 and dff_2 of the wc_in1 cell are loaded with 1 and 0, respectively; data in dff_1 and
dff_2 of the wc_out wrapper cell are both 0.
With this data pattern, wc_in1 has an initial value of 0 applied, and there is a 1 value ready in
that cell’s dff_1 storage element.
Clock cycle 7 is a Transfer event where wc_in0 and wc_in1 internally exchange data between
their respective dff_1 and dff_2 bits. This causes a rising-edge delay test stimulus being applied to
the IN1 input of the OR gate.
Clock cycle 8 performs both the Transfer and Capture events. If the time interval between
clock events 7 and 8 is according to the delay time specification of the path from IN1 to OUT, then
a first delay test response is captured in dff_2 of wc_out. Simultaneously, a falling-edge delay test
stimulus is applied to the IN1 input of the OR gate. After a settling time, the WBR Test Output TO
reflects the result of the capture.
Clock cycle 9 again performs both the Transfer and Capture events. If the time interval

VLSI Test Principles and Architectures Ch. 10 – Boundary Scan & Core-Based Testing – P. 8/10
between clocks 8 and 9 is according to the delay specification of the OR gate a second delay test
response is captured in dff_2 of wc_out. Simultaneously, the data value that was captured during
clock 8 is transferred to dff_1 of wc_out. After a settling time, the WBR TO reflects the results of
the second capture.
Clocks 10 through 14 are used to shift out the last 5 bits of the WBR where the results of the
first capture come out on clock 10.
Since the architecture of the standardized boundary scan cell does not support the
functionality of interchanging contents in the embedded flip-flops (update and capture flip-flops)
and latency exist between some test operations (e.g., 2 and half cycles between update and
capture), the test procedure for delay faults discussed here cannot be directly applied to a circuit in
compliance with IEEE 1149.1 Std..
10.11
Assume the numbers of input wrapper cells and output wrapper cells are equal. Then the number
of required test cycles can be calculated as follows.
4 (loading instruction) +
(15+1) (shift in the first test pattern to the wrapper chain and apply to the circuit) +
(15+1)*99 (shift in the remaining test patterns to the wrapper chain and apply to the circuit as
well as capture the test response and shift out the test responses) +
15 (shift out the test response associated with the last test pattern) = 1619 (cycles)
10.12
Assumption:
1) The numbers of input wrapper cells and output wrapper cells are equal.
2) 5 among the 10 parallel TAM wires are for TAM in and the others are for TAM out.
3) The test data (including test patterns and responses) as well as test instruction are
transferred via parallel TAM.
Calculation:
Since we assume the test instruction is transferred via parallel TAM (see Assumption 3), only
1 cycle is required for loading the 4-bit instruction. On the other hand, the number of required
cycles to execute scan operation can be calculated as follows. By taking Assumptions 1) and 2)
into consideration, 3 cycles are required to shift in the 15-bit sized input/output wrapper chain.
Thus totally
(3+1) (shift in the first test pattern to the wrapper chain and apply to the circuit) +
(3+1)*99 (shift in the remaining test patterns to the wrapper chain and apply to the circuit as well
as capture and shift out the test responses) +
3 (shift out the test response associated with the last test pattern)

VLSI Test Principles and Architectures Ch. 10 – Boundary Scan & Core-Based Testing – P. 9/10
= 403 cycles are required for scan operations.
As a result, a total of 404 cycles are needed.
Test configuration
W
B
R
FI
FO
W
B
R
TAM in 5 bits
1 to 4 DeMux
W
B
R
W
B
R
FI
FI
Core
Test
Enable
FO
FO
W
B
R
W
B
R
4 to 1 Mux
TAM out 5 bits
WBY
WIR
WSC
Note: some details not
shown in this figure
Note: we also have to add some instructions to decode the proper control signals for the mux,
demux and WBRs selection.
10.13
1. Parallel Mode
IEEE 1500 Std. can provide higher transfer capability than IEEE 1149.1 Std. via parallel
mode, which is one of the remarkable advantages of IEEE 1500 Std. over IEEE 1149.1 Std.
2. Extra Data/Control I/Os
IEEE 1500 Std. assumes that control signals are generated by a mechanism defined by the
user, while for IEEE 1149.1 Std. these control signals are generated by the TAP controller.
Therefore, IEEE 1500 Std. has more optional I/Os and higher flexibility.
3. FSM (TAP Controller)
Control signals of IEEE 1149.1 Std. are generated by a FSM, and thus the latency between
some operations is inevitable, making some delay test unable to be applied. However, for
IEEE 1500 Std. the generation mechanism is dominated by the user. Therefore the latency
between operations can be eliminated.
4. Transfer mode
IEEE 1500 Std. can preserve as many capture values as there are storage elements in the

VLSI Test Principles and Architectures Ch. 10 – Boundary Scan & Core-Based Testing – P. 10/10
shift path. It also can provide sequential stimuli data by the transfer mode, enabling delay
test.
5. Latency between shift, capture, and update operations for IEEE 1149.1 Std. results in long
test time and limits the capability of the support of delay test.
6. Mandatory Instructions:
EXTEST and BYPASS in 1149.1 are similar to WS_EXTEST and WS_BYPASS. However,
a WP_INTEST instruction would be highly beneficial in reducing test time if a large number
of test access lines are available for the WPP.
Reference
[1] A. Hassan, J. Rajski, and V. K. Agarwal, “Testing and Diagnosis of Interconnects Using
Boundary Scan Architecture,” Proc. Int’l Test Conf. pp. 126-137, 1988.