DirectCompute Optimizations and Best Practices - Nvidia

More documents

Recommendations

Info

Coalesced Access: Reading floats t0 t1 t2 t3 t14 t15 128 132 136 140 144 184 188 192 All threads participate t0 t1 t2 t3 t14 t15 128 132 136 140 144 184 188 192 Some Threads Do Not Participate
Uncoalesced Access: Reading floats t0 t1 t2 t3 t14 t15 128 132 136 140 144 Permuted Access by Threads 184 188 192 t0 t1 t2 t3 t13 t14 t15 128 132 136 140 144 184 188 192 Misaligned Starting Address (not a multiple of 64) 11
Page 1 and 2: DirectCompute Optimizations and Bes
Page 3 and 4: Why GPUs • GPUs are throughput or
Page 5 and 6: Advantages of DirectCompute • Dir
Page 7 and 8: Parallel Execution Model Thread Gro
Page 9: Memory Coalescing • A coordinated
Page 13 and 14: Compute 1.2+ Coalesced Access: Read
Page 15 and 16: Thread Group Shared Memory (TGSM)
Page 17 and 18: Shared Memory Bank Addressing • N
Page 19 and 20: What is Occupancy GPUs typical
Page 21 and 22: Maximizing HW Occupancy • Registe
Page 23 and 24: DirectCompute Optimization Example
Page 25 and 26: Parallel Reduction • Tree-based a
Page 27 and 28: Solution: Shader Decomposition •
Page 29 and 30: Reduction #1: Interleaved Addressin
Page 31 and 32: Performance for 4M element reductio
Page 33 and 34: What is Thread Divergence • Diver
Page 35 and 36: Parallel Reduction: Interleaved Add
Page 37 and 38: Thread Group Shared Memory Bank Con
Page 39 and 40: Reduction #3: Sequential Addressing
Page 41 and 42: Idle Threads Problem: for (unsigned
Page 45 and 46: Unrolling the Last Warp • As redu
Page 49 and 50: Reduction #6: Completely Unrolled #
Page 51 and 52: Reduction #7: Multiple Adds / Threa
Page 55 and 56: Time (ms) Performance Comparison 10
Page 58 and 59: Extra Slides
Page 60 and 61:
Memory Coalescing (Matrix Multiply)
Page 62:
Matrix Multiplication (cont.) Optim
show all

DirectCompute Optimizations and Best Practices - Nvidia

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?