DirectCompute Optimizations and Best Practices - Nvidia

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Performance for 4M element reduction Shader 1: interleaved addressing with divergent branching Time (2 22 ints) B<strong>and</strong>width 8.054 ms 2.083 GB/s Step Speedup Cumulative Speedup Shader 2: interleaved addressing with bank conflicts 3.456 ms 4.854 GB/s 2.33x 2.33x
Thread Group Shared Memory Bank Conflicts 32 banks example (each address is 32-bits) Banks are arranged linearly with addresses: Address: Bank: 0 1 2 3 4 ... 31 32 33 34 35 ... 0 1 2 3 4 ... 31 0 1 2 3 ... TGSM addresses that are 32 DWORD apart use the same bank Accessing those addresses from multiple threads will create a bank conflict Declare TGSM 2D arrays as MyArray[Y][X], <strong>and</strong> increment X first, then Y – Essential if X is a multiple of 32! Padding arrays/structures to avoid bank conflicts can help – E.g. MyArray[16][33] instead of [16][32]
Page 1 and 2: DirectCompute Optimizations and Bes
Page 3 and 4: Why GPUs • GPUs are throughput or
Page 5 and 6: Advantages of DirectCompute • Dir
Page 7 and 8: Parallel Execution Model Thread Gro
Page 9 and 10: Memory Coalescing • A coordinated
Page 11 and 12: Uncoalesced Access: Reading floats
Page 13 and 14: Compute 1.2+ Coalesced Access: Read
Page 15 and 16: Thread Group Shared Memory (TGSM)
Page 17 and 18: Shared Memory Bank Addressing • N
Page 19 and 20: What is Occupancy GPUs typical
Page 21 and 22: Maximizing HW Occupancy • Registe
Page 23 and 24: DirectCompute Optimization Example
Page 25 and 26: Parallel Reduction • Tree-based a
Page 27 and 28: Solution: Shader Decomposition •
Page 29 and 30: Reduction #1: Interleaved Addressin
Page 31 and 32: Performance for 4M element reductio
Page 33 and 34: What is Thread Divergence • Diver
Page 35: Parallel Reduction: Interleaved Add
Page 39 and 40: Reduction #3: Sequential Addressing
Page 41 and 42: Idle Threads Problem: for (unsigned
Page 45 and 46: Unrolling the Last Warp • As redu
Page 49 and 50: Reduction #6: Completely Unrolled #
Page 51 and 52: Reduction #7: Multiple Adds / Threa
Page 55 and 56: Time (ms) Performance Comparison 10
Page 58 and 59: Extra Slides
Page 60 and 61: Memory Coalescing (Matrix Multiply)
Page 62: Matrix Multiplication (cont.) Optim

DirectCompute Optimizations and Best Practices - Nvidia

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