Presentation Materials Including Discussion Notes - UCSD VLSI ...
Presentation Materials Including Discussion Notes - UCSD VLSI ...
Presentation Materials Including Discussion Notes - UCSD VLSI ...
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2 nd DAC EDA Roadmap Workshop<br />
June 14, 2010, 9am – 3pm<br />
Anaheim Convention Center, Room 213D<br />
For latest version, contact J. Antonio Carballo (juananto@us.ibm.com) or Andrew Kahng (abk@cs.ucsd.edu)
Goals<br />
• Goal of this workshop<br />
–To further the dialogue between the various communities /<br />
bodies involved in roadmapping design technology, and to bring<br />
together key constituencies (designers, EDA companies,<br />
researchers, and multiple world regions) with a view towards a<br />
more explicit future interlock<br />
• Uniqueness of this workshop<br />
–The only forum for deep discussion around roadmap issues<br />
related to the EDA industry. Leaders from semiconductor<br />
companies, consortia, and academia jointly assess the need for<br />
and state of roadmap efforts, to craft a blank-sheet view of<br />
roadmap activities for the next 15 years<br />
TODAY<br />
Where/How should the EDA industry improve its roadmap(ping)<br />
1
Our Agenda !<br />
Session/title Speaker(s) Time<br />
Introduction and Plenary J.A.Carballo (IBM), A.B. Kahng (<strong>UCSD</strong>) 9AM<br />
Session I: Corporate Roadmap Views<br />
IBM's EDA Roadmap View David Kung (IBM) 9:20<br />
IDM View Shishpal Rawat (Intel) 9:40<br />
EDA Standards @ Si2: 2010 view Sumit Dasgupta (Si2 Roadmap) 10:00<br />
GF EDA Roadmap View Walter Ng (GlobalFoundries) 10:20<br />
EDA 360 Andreas Kuehlmann (Cadence) 10:40<br />
Maximizing performance per Watt Rob Knoth (Magma) 11:00<br />
IP View Yervant Zorian (Virage Logic) 11:20<br />
IDM / Fablite View Nagaraj NS (TI) 11:40<br />
Panel <strong>Discussion</strong> and Working Lunch (sandwich orders in the morning) Noon<br />
Session II: Consortia (and Corporate Stragglers) Views<br />
EU CATRENE / ENIAC roadmap Ahmed Jerraya (CEA-LETI) 1:10<br />
Japan's EDA Roadmap View STRJ (Kahng / Carballo rep) 1:30<br />
ITRS's EDA Roadmap View Kahng / Carballo (<strong>UCSD</strong> / IBM) 1:50<br />
IP View Dipesh Patel (ARM) 2:10<br />
Panel <strong>Discussion</strong> and Next Steps Kahng / Carballo (<strong>UCSD</strong> / IBM) 2:30
Some Questions and Actions from 2009<br />
QUESTIONS<br />
1. What would make an EDA roadmap more useful <br />
– To whom (R&D, marketing, standards bodies, consortia, ...)<br />
2. Which EDA areas lack most in roadmap efforts<br />
– Parallel EDA, SW EDA, analog EDA, ESL <br />
3. Which EDA areas are behind what the roadmaps say <br />
– Does this matter <br />
ACTIONS<br />
4. Need: Process to ensure tight contributors-users interlock<br />
5. Need: Commitment to a yearly report of<br />
i. how EDA roadmap is used<br />
ii. by whom<br />
iii. feedback for improving it next year<br />
• Are existing efforts OK (point to them as “meta-roadmap”) or not<br />
3 (new one needed)
Process for Today<br />
1. Short (10-15 min) viewpoint talks in 20-min slots<br />
– Leaving time for discussion<br />
2. Different from last year: IP, IDM, foundry perspectives<br />
3. Organizers will scribe discussion highlights and follow-up actions<br />
4. Slides and discussion outcomes will be posted on the same website<br />
i. who is responsible for {development, review, integration} of roadmap<br />
ii. in what specific areas (applications, embedded software, AMS, …)<br />
iii. on what timeline (when should we have follow-ups this year)<br />
iv. for what consumers (ITRS Design/SysDrivers chapters, EDAC, …)<br />
5. Misc: lunch signups, etc.<br />
4
TECHNOLOGY GAPS IN EDA ROADMAP<br />
1. End-product roadmaps (what is EDA enabling!) x<br />
Semi companies compete on cost, TTM, quality<br />
2. System-level - virtual platforms, executable specification<br />
TI, Bosch<br />
3. Design space exploration – pathfinding (incl. 3D), IP<br />
selection, what-if analyses (incl. cost)*<br />
4. SW synthesis and verification (concurrency)<br />
5. Post-silicon: perf/power closure, diagnosis, debug * (Test)<br />
6. EDA scaling (cf. evolving computing platforms<br />
(manycore, accelerators, cloud) *<br />
Simply follow Moore’s Law, handle technology<br />
7. Power management (analysis, optimization, power-driven<br />
design) *<br />
Apple, Google, Nokia<br />
8. 3D (end of CMOS, heterogeneity, cost, perf, power)<br />
9. Variability (trends), resilience, BTWC design *<br />
10.Analog / mixed-signal<br />
11.Interoperability<br />
5
NATURE OF EDA<br />
1. Predictable (RAS), incremental design flows<br />
(e.g., functional sim)<br />
2. Wall time (tool, design process)<br />
3. Hierarchy (passing design intent, integration)<br />
4. IP encapsulation, migration, reuse<br />
5. Extracting value from a mature technology node<br />
6. Enabling user development<br />
7. Usability<br />
(product class-specific)<br />
8. Industry efficiency<br />
6
ROADMAP = CHALLENGES + SOLUTIONS + METRICS<br />
1. Standards (e.g., OpenPDK, IP encapsulation)<br />
2. *Move from hardware to system (hw, sw, fw) level*<br />
= Expanding scope of EDA<br />
3. Interoperability<br />
4. *COST – of design, of product, of tool integration<br />
Design for Cost (what-if from spec to arch …)<br />
5. Industry efficiency<br />
6. Usability (e.g., enabling user development)<br />
Waves: long Tcl script foundation flows<br />
7
NOTES<br />
1. Other<br />
i. Business justification for EDA development<br />
ii. Technology vs. design entitlement gap<br />
2. What is the crisis<br />
i. According to what metric<br />
3. Sharing of EDA R&D / product metrics<br />
4. Verticalization of EDA<br />
8
ATTENDEES<br />
1. David Kung, IBM kung@us.ibm.com<br />
2. Shishpal Rawat, Intel shishpal.s.rawat@intel.com<br />
3. Nowjand Attaie, Intel nowjand.attaie@intel.com<br />
4. Chin-Fu Chen, Qualcomm cfchen@qualcomm.com<br />
5. Myungsoo Jang, Samsung msjang@samsung.com<br />
6. Woosick Choi, Hynix woosick.choi@hynix.com<br />
7. Walter Ng, GLOBALFOUNDRIES ngw@globalfoundries.com<br />
8. Nagaraj NS, TI nsnr@ti.com<br />
9. James You, Broadcom jyou@broadcom.com<br />
10. Deepak Sherlekar, Virage Logic deepak.sherlekar@viragelogic.com<br />
11. Yervant Zorian, Virage Logic zorian@viragelogic.com<br />
12. Hisam El-Masry, CMC Microsystems elmasry@cmc.ca<br />
13. Matthew Hogan, Mentor matthew_hogan@mentor.com<br />
14. Roberto Suaya, Mentor roberto_suaya@mentor.com<br />
15. Merlyn Brunken, Mentor merlyn_brunken@mentor.com<br />
16. Jay Adams, Synopsys jka@synopsys.com<br />
17. Narendra Shenoy, Synopsys nshenoy@synopsys.com<br />
18. William Joyner, SRC william.joyner@src.org<br />
19. Sumit Dasgupta, Si2 dasgupta@si2.org<br />
20. Ahmed Jerraya, CEA-LETI ahmed.jerraya@cea.fr<br />
21. W. Rhett Davis, NC State Univ. rhett_davis@ncsu.edu<br />
22. Michael Kochte, Univ. Stuttgart kochte@iti.uni-stuttgart.de<br />
23.<br />
9<br />
Alper Sen, Bogazici Univ. alper.sen@boun.edu.tr