Semi-Digital Interleaved PFC Control with Optimized Light Load ...

Semi-Digital Interleaved PFC Control with
Optimized Light Load Efficiency
T. Grote 1 , H. Figge 1 , N. Fröhleke 1 , W. Beulen 2 , F. Schafmeister 2 , P. Ide 2 , J. Böcker 1
1
University of Paderborn, Institute of Power Electronics and Electric Drives, Germany
2
DELTA Energy Systems GmbH, Soest, Germany
Abstract— A control structure for an interleaved power factor
correction (PFC) rectifier with smart combination of analog and
digital control parts is presented in this paper. Analog technique
is employed to accomplish high control bandwidth while digital
control is used for parts of lower dynamic demands. This results
in low microcontroller costs though the system is kept flexible.
Particularly, the control strategy can be adapted depending on
the operation point. Since the light load performance is in recent
focus of interest, appropriate algorithms to improve light load
efficiency were implemented on a prototype system and are
briefly described in this paper. The effectiveness of the proposed
semi-digital control approach is verified by experimental results.
Keywords: power factor correction rectifier, digital control,
semi-digital control, interleaving, power management,
v_line
additional analog circuits
interleaved clock signal;
PWM; current balancing;
safety shutdown
i_V2
i_V1
d*
current
controller
i*
analog single PFC controller IC
_
i_PFC
+
i*
voltage
controller
_
v_bulk
+
v ref
I. INTRODUCTION
The boost power factor correction (PFC) rectifier is widely
used as front-end stage for AC-DC switched-mode power
supplies (SMPS). In order to split the total current and
moreover to reduce the effective high-frequency ripple of line
and DC link capacitor currents it is advantageous to use two
parallel boost phases in an interleaved (i.e. 180° phaseshifted)
manner [1-5], if the power is in the range of above
1 kW.
Analog control provides high bandwidth. For a multitude
of applications, specific analog controller ICs are available,
which are easy to understand and featuring a variety of
functionalities at relative low costs. Hence, analog controllers
are still dominant in PFC applications. However, in many
cases these standard ICs do not meet adequately the required
specifications. To fulfill those requirements, additional analog
circuitry is needed as shown for example in Fig. 1 with an
interleaved PFC rectifier.
Recent publications [6-12] demonstrate that purely digitally
controlled PFCs are feasible and exhibit a number of benefits
such as flexibility and programmability, decreased number of
active and passive components, and, as a consequence,
improved reliability, negligible and/or compensatable offsets
and thermal drifts. Additionally, digital control offers the
potential of implementing sophisticated adaptive and
nonlinear control methods to improve stationary and dynamic
performance and to implement power management strategies
to improve efficiency. However, the current control loop has
to provide a much higher bandwidth than the voltage control
loop. Therefore, high computing power and costly DSP would
Fig. 1. Control structure for interleaved PFC rectifier realized with a
single PFC controller IC
be needed if going fully digital. Even fully digital control still
needs some analog circuits for time-critical safety shutdown
or shunt signal amplification.
Considering these pros and cons, a semi-digital concept
turns out as an attractive compromise:
• The current controller including time-critical protection
functions retains the conventional analog structure.
• The voltage controller, feed-forward compensation,
multiplier, PWM clock generator and non-time critical
protection functions are implemented on a
microcontroller.
Such a solution is characterized as follows:
• Because the required bandwidth of the voltage control is
usually small, a cost-effective microcontroller is
sufficient.
• High current control bandwidth is ensured by the analog
circuitry.
• There is no need to apply specific analog controller ICs.
• Most innovations of digital control can be realized,
because issues of adaptive and nonlinear control,
programmability etc. focus mainly on voltage control.
• The system can be configured, controlled and monitored
by Power Management Bus (PMBus) [13].
The paper is structured as follows. Section II describes the
mode of operation of interleaved PFC rectifier control. In
Section III the structure of the semi digital control approach is
proposed. The microcontroller implementation of the digital
control parts is presented in Section IV. Experimental results
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obtained on SMPS prototype of 2 kW with interleaved boost
PFC rectifier are given in Section V.
II. INTERLEAVED PFC CONTROL
The application of two interleaved converters features a
number of benefits [1-5] such as increasing power density
without the penalty of reduced efficiency, size reduction of the
boost inductors and the differential-mode EMI filter.
Interleaving can also significantly reduce the switching losses
and the current stress of the DC link capacitor [1].
The control structure of a boost PFC rectifier (cf. Fig. 1)
usually consists of an outer voltage loop, controlling the DC
output voltage, a multiplier to provide sinusoidal current
reference value, and an inner current loop. For interleaved
PFC rectifier an additional current balancing control is
necessary, because natural current sharing among the stages is
non-ideal in many applications.
Up to now, predominantly controller ICs for single PFC are
available. So, these ICs are also used for interleaved PFC
rectifiers. Hence, the current balancing has to be implemented
with additional discrete components. That is why the PWM
unit and some protection functions of the IC (for instance
UCC3818) cannot be used. Fig. 2 shows the scheme for such a
separate PWM with current balancing. The main portion of
the comparator-input ramps consists of the rising transistor
currents. Adding the time controlled PWM sawtooth signal to
the current ramps increases the slopes at the comparator input.
This technique is commonly known as slope compensation
and prevents subharmonic oscillation in peak current
controlled converters. Furthermore, it provides good current
sharing of parallel converters.
III. SEMI-DIGITAL CONTROL
Fig. 3 shows the semi-digital control structure with the
separated analog current controller, analog PWM including
current balancing and the digital voltage controller. The
digital control parts are implemented on a 16 bit
microcontroller. Analog-to-digital converters (ADC) provide
the actual values of the rectified input voltage v line and PFC
clock
controller
+
+
+
d*
+
i_V 1
i_V 2
RS
FF Q
RS
RS
FF Q
RS
Fig. 2. Scheme of interleaved PWM with current balancing
rectifier output voltage v bulk . There is no need of converting
any currents for the control loop. Thus, only relatively slowly
varying signals need to be converted, making costly ADCs
with a high sample rate superfluous.
By means of the control variable v bulk and the nominal
output voltage reference v bulk-ref the offset v err for the voltage
control algorithm is calculated (cf. Fig. 5). Measured v line
values are primarily needed to synthesize the sinusoidal input
current reference i * . Thereto, typically the voltage regulator
*
output
î (proportional to current reference peak value) is
multiplied by v line . In the proposed case an artificial sinusoidal
waveform is used for multiplying, for which reason v line is
needed to detect zero crossing and line frequency.
Furthermore, the line voltage amplitude vˆ line
is used for a
feed-forward compensation to achieve constant input power
under fluctuation of the input voltage. The output value of the
digital control part is the current reference value i * for the
current controller.
In addition the digital part observes the range of v bulk and
v line and can trigger a safety shutdown at overvoltage or
undervoltage conditions.
The output value i * is passed to the analog current
controller (cf. Fig. 4) as pulse-width modulated signal. A
simple RC low-pass filter is used as digital-to-analog
converter (DAC). For current control, a PI type controller with
additional low pass filtering is used, which is implemented
v_line
Inrush
v_bulk
digital
voltage
controller
i*
analog
current
controller
d*
PWM
&
current
balance
i_V 2
i_V 1
i_PFC
Fig. 3. Semi-digital control structure for interleaved PFC rectifier
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PWM
signal
i PFC
i offset
i*(t) d*
Fig. 4. Scheme of the analog current controller
using a single op-amp. Another PWM channel also with RC
low-pass filter is used for offset compensation. The actual
current value i PFC is measured via shunt and after filtering and
adequate scaling passed to the current controller. PWM and
current balancing circuits are kept unchanged and form a
complete analog subsection. Analog comparators are used for
time critical safety shutdown (e.g. pulse by pulse current
limiting).
Some functions like soft-start or inrush current limiting are
only used during start-up but nevertheless require PCB space
if realized by analog components. Those functions are well
suited for sequential microcontroller processing, because they
can be added without any extra costs and without losing any
performance.
The presented semi-digital control is used for an
interleaved PFC rectifier with two phases, but it can easily be
extended for multi-phase interleaved converters without the
need of more computing power.
IV. DIGITAL CONTROL IMPLEMENTATION
The digital control strategy described in the previous
section, as well as additional functions for monitoring, start-up
and power management are implemented using the 16 bit
microcontroller (Microchip dsPIC30F2020). The structure of
digital control is shown in Fig. 5 with particular functions
described below.
A. PWM Clock
The clock signal for the analog PWM module is generated
by the microcontroller PWM unit. Two PWM channels are
used in push-pull mode to generate two 180° interleaved clock
signals with half of the PWM frequency of approx. 130 kHz.
Because the PWM clock signal is generated by
microcontroller, start and stop of the PFC can be controlled
digitally. Furthermore, the switching frequency is kept
adjustable.
B. Soft Start-Up
At start-up the PFC output capacitor voltage has to be
raised from the pre-charged level vˆ line
to the nominal output
voltage v bulk-ref . In order to avoid high current surge, a soft
start-up procedure is implemented. It starts by closing the
inrush relay. As the delay time of the relay is known, it is
forced to close at line voltage zero crossing to avoid a start-up
current peak. The actual soft-start process also starts at zero
crossing with multiplying a constant current reference peak
*
value î by line voltage v line . The result is the sinusoidal
current reference value. It is passed via PWM and DAC to the
analog current controller until the nominal output voltage is
reached. After completing the soft-start procedure the program
enters the repetitive loop with all control functions being
activated.
C. Voltage Control, Multiplier and Feed-Forward
The digital control tasks are triggered by timer interrupt
with cycle times of approx. 150µs. In every cycle, voltage
control, multiplier and feed-forward compensation are
computed.
The voltage controller is a discrete-time PI-T 1
compensator, which requires only little computing time:
ˆ
*
ˆ*
( ) ( ) ( 1) ( 1) ˆ*
i n = b0v
err
n + bv
1 err
n−
+ a1i
n−
+ a2i
( n−2)
. (1)
v_bulk_ref
PWM 1L
clock A
v_bulk
v_line
_
+
v_err
v_line
analysis
voltage
controller
V_line
i*
current
limiting
sine LUT
PWM 1H
PWM 2L
clock B
i offset
digital to analog
conversion
(DAC)
soft-start
i*(n)
PWM 2H
i*(t)
inrush relay
v_cc
monitoring
high/low-line
enable PFC
Temp
microcontroller
Fig. 5. Block diagram of the digital control structure implemented on microcontroller
v_bulk_OK
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The controller output provide the current reference peak
*
value î , which has to be multiplied by line phase to
achieve the sinusoidal reference waveform. The current
reference value is not directly multiplied by the measured
line voltage but by using a look-up table (LUT) containing
the sine data (cf. Fig. 5). A counter is reset every line
voltage zero crossing and gives the instantaneous line
phase which is used to obtain the matching sine table entry.
Using a sine table simplifies adjustment of systematic
phase errors caused by ADC, DAC, computational time,
etc. Another advantage of using an artificial sine wave is
the simplified calculation of the feed-forward
compensation. If the line voltage is directly used for
multiplying, feed-forward compensation has to be
accomplished by dividing by the square value of line
voltage amplitude to achieve constant input power at input
voltage changes. Because of the constant amplitude of an
artificial sine there is no need to square. The equivalent
implemented equation is:
iˆ
( n)
v ( k)
= . (2)
*
* ⋅
sin e
( n)
vˆ
line
i
The amplitude value of input voltage vˆ line
is updated
once in a half-cycle. The counter value k is reset every zero
crossing and represents the index of the sine table entry.
A problem of using a sine table with fixed length is to
guarantee a high power factor under a wide range of line
frequency (47 Hz – 63 Hz). Therefore a phase-locked loop
(PLL) is implemented, which slightly changes the timer
interrupt spacing. However, these timer adjustments affect
the performance of the discrete-time voltage regulator (1).
Thus, three sine tables are used to minimize timer interrupt
variance.
D. Power Management Features
1) Adaptive Current Limiting
In order to avoid overstressing of the devices the current
has to be limited. However, for short-term duration an
overcurrent up to 125 % of I nominal is acceptable (cf. Fig. 5).
Therefore an algorithm is implemented which allows
intermediate overcurrent considering the past loading
conditions of the converter. No overcurrent is allowed
when the power supply is stationary running at full load.
Assuming that the current loop works correctly the
current reference value is used for the algorithm, thus there
is no need to convert the actual current value into the digital
world. Fig. 6 illustrates the current limiting process from
20 % and 80 % initial load.
2) Phase Shedding
One advantage of using interleaved phases is the
potential to adjust the number of energized phases based on
the load conditions. Thus it is possible to enhance the
efficiency at light load conditions [3-4]. Switching between
single phase and interleaved operation occurs with
hysteresis, i.e. one phase is switched off, if output power is
iout / %
150
125
100
80
50
20
limited current
i* (requested current)
lagging curves of
thermal model
i* lim20%
i* lim80%
-5 0 5 10 15 20 25
t/ ms
Fig. 6. Current limiting after load step from 20% and 80% load
below 40 % of the rated power for a defined duration and
switched on again when the output power exceeds 45 %.
While running in single phase mode, the energized phase
alternates between the two phases in order to achieve equal
thermal stress of all PFC components.
3) DC Link Voltage Reduction
In many applications the PFC output capacitor supports
two functions: First filtering the inductor current and
second providing energy in ‘hold up’ case at line power
failure (e.g. for one line period). However, since the stored
energy depends on the output voltage, the output voltage
can be reduced at light load. This measure leads to an
improved efficiency of the PFC stage and the DC-DC stage
at light load. Switching losses of both stages strongly
depend on the DC link voltage (which is semiconductor
blocking voltage) and decrease significantly with reduced
voltage level.
4) Adaptive Switching Frequency
Another method to improve the efficiency is to reduce
switching losses by an adaptive lowering of the switching
frequency. This is feasible because the PFC boost
inductance is nonlinear but depends on the actual current
value. Hence, at lower current and therefore increased
inductance the switching frequency can be reduced, while
the current ripple is still kept under limit. This
circumstance is utilized twice, firstly within every sine
half-wave of line current (Fig. 7) and secondly depending
on the DC output current, which defines the line current
amplitude (i.e. lower switching frequency at lower load).
V. PROTOTYPE AND MEASUREMENT RESULTS
The prototype was build up on the basis of a standard
industrial AC-DC converter that was modified in order to
test the proposed control strategy. Fig. 8 shows this 2 kW
power supply with wide range AC input (90 V – 265 V;
47 Hz – 63 Hz). The AC-DC stage is an interleaved boost
PFC rectifier with 400 V nominal DC output voltage.
978-1-422-2812-0/09/$25.00 ©2009 IEEE 1725

100%
75%
Line Current
(100V/div)
i line
50%
f s
100%
25%
Switching Frequency
75%
(5A/div)
0
50%
0 2 4 6 8 10
t / ms
Fig. 7. Switching frequency dependent on the instantaneous
current value during line half-cycle
The DC-DC stage consists of an interleaved two transistor
forward converter with 48 V DC output. In a first step the
digital control algorithms were implemented on a
Microchip 16 bit-microcontroller, type dsPIC30F2020,
which offers more calculation performance than actually
needed for this application. After identifying the actual
demand of computing power, a 16 bit microcontroller
(PIC24FJ16GA002) with approx. half the calculation
performance could be used without restriction of any kind.
The microcontroller costs could be reduced by more than
50 % with this choice.
By replacing the multitude of analog components by
microcontroller the required PCB space for PFC control is
reduced significantly. The performance of the modified
power converter was verified by extensive experimental
testing. Selective results are presented in the following.
The measured input voltage and current waveforms of
the prototype are shown in Fig. 9. As can be seen, the input
current replicates the line voltage waveform accurately.
Fig. 10 shows the start-up process of the prototype. The
soft-start procedure sets a constant current reference value
*
î , until the output capacitor voltage reaches the reference
output voltage v bulk-ref . The soft-start duration depends on
the pre-charged level vˆ line
and the preset current reference
value.
i*
Fig. 9. Line voltage and current waveform
v bulk_ref
v bulk
v line
i line (5A/div)
Fig. 10. Soft start-up process
i*
(from DAC)
microcontroller
v bulk, AC
(10V/div)
i line
(5A/div)
i*
(from DAC)
Fig. 8. Modified 2 kW AC-DC converter system
Fig. 11. Transient response for load change (250 W – 500 W)
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Fig. 11 shows a 250 W – 500 W load step transient
response. The response time and the voltage overshoot are
in an acceptable range and match the implemented
controller dynamics.
For evaluating the effectiveness of implemented power
management features the efficiency for different load
conditions is measured with and without power
management features activated. The resulting efficiency
improvement for the PFC stage, the DC-DC stage and the
sum of both are given in Fig. 12. Particularly, at light load
the efficiency is improved significantly by implemented
strategies. The efficiency improvement in the DC-DC stage
is based only on lowering the PFC output voltage - and this
turned out to be the most effective measure for the overall
efficiency improvement.
VI. CONCLUSIONS
Digital control offers potential for applying advanced
algorithms to enhance the control performance. However, it
is not essential to implement a full digital control structure
to achieve high flexibility. It has been shown that almost
the same performance can be achieved when only realizing
the low bandwidth voltage control in a digital manner. By
retaining the relative fast control functions in analog
technique, there is no need of high computing power,
which decreases microcontroller costs significantly.
The presented semi-digital control has been applied for
an interleaved PFC rectifier with two phases, but it can
easily be extended for multi-phase interleaved converters
without the need of more computing power.
In particular, with semi-digital control the following
results have been accomplished:
• Adaptive current limiting strategy to permit short-time
overcurrent up to 125%.
• Efficiency improvement up to 4% at light load only by
means of control as phase shedding, lowering of PFC
output voltage and of switching frequency.
• Easy implementation of soft start-up to avoid current
surge
Efficiency Improvement
4,0%
3,5%
3,0%
2,5%
2,0%
1,5%
1,0%
PFC DC-DC Overall
0,5%
0,0%
10 20 30 40 50 60 70 80 90 100
load / %
Fig. 12. Improvement of efficiency by implemented power management features
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