sparc-architecture-2011-1728132

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ii Oracle SPARC Architecture <strong>2011</strong> • Draft D0.9.5d, 18 Jul 2012
Copyright © <strong>2011</strong>, Oracle and/or its affiliates. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Other names may be trademarks of their respective owners. AMD, Opteron, the AMD logo, and the AMD Opteron logo are trademarks or registered trademarks of Advanced Micro Devices. Intel and Intel Xeon are trademarks or registered trademarks of Intel Corporation. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. UNIX is a registered trademark licensed through X/Open Company, Ltd.. Comments and "bug reports” regarding this document are welcome; they should be submitted to email address: David.Weaver@Oracle.com
Page 1: Oracle SPARC Architecture 2011 One
Page 5 and 6: Contents Preface. . . . . . . . . .
Page 7 and 8: 5.5.8 SOFTINT P Register (ASRs 20,
Page 9 and 10: 8.5.13 Floating-Point Lexicographic
Page 11 and 12: 14.4 Translation Storage Buffer (TS
Page 13 and 14: Preface First came the 32-bit SPARC
Page 15 and 16: Corrections and other comments rega
Page 17 and 18: CHAPTER 1 Document Overview This ch
Page 19 and 20: ■ ■ ■ ■ ■ A double period
Page 21 and 22: CHAPTER 2 Definitions This chapter
Page 23 and 24: floating-point unit FPop FPRS FPU F
Page 25 and 26: NPC Next program counter. nucleus s
Page 27 and 28: speculative load store strand subno
Page 29 and 30: CHAPTER 3 Architecture Overview The
Page 31 and 32: 3.1.2.2 Register Windows The Oracle
Page 33 and 34: 3.2.2 Floating-Point Unit (FPU) An
Page 35 and 36: In such split-memory systems, the c
Page 37 and 38: 3.3.6 Conditional Move Conditional
Page 39 and 40: CHAPTER 4 Data Formats The Oracle S
Page 41 and 42: 4.1.1.1 Signed Integer Byte, Halfwo
Page 43 and 44: 4.2 Floating-Point Data Formats Sin
Page 45 and 46: TABLE 4-5 Floating-Point Quad-Preci
Page 47 and 48: CHAPTER 5 Registers The following r
Page 49 and 50: One set of 8 global registers is al
Page 51 and 52: The current window in the windowed
Page 53 and 54:
CWP = 0 (CURRENT WINDOW POINTER) w1
Page 55 and 56:
TABLE 5-2 Floating-Point Registers,
Page 57 and 58:
5.3.2 Double and Quad Floating-Poin
Page 59 and 60:
TABLE 5-4 Floating-Point Condition
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4. The value of fccn is unchanged.
Page 63 and 64:
■ if FSR.tem.ufm =1,theFSR.cexc.u
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Each virtual processor contains its
Page 67 and 68:
The v bits signify whether the ALU
Page 69 and 70:
PC and NPC can be indirectly set by
Page 71 and 72:
RW RW RW SOFTINT P — sm int_level
Page 73 and 74:
At least one STICK register must be
Page 75 and 76:
TABLE 5-13 Compatibility Feature Re
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privileged_opcode exception. In add
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RW RW WSTATE P other normal 5 3 2 0
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TNPC 1 P TNPC 2 P TNPC 3 P : : : TN
Page 83 and 84:
5.7.6 Processor State (PSTATE P ) R
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Address Mask (am). The PSTATE.am bi
Page 87 and 88:
The maximum valid value that the TL
Page 89 and 90:
Since TSTATE itself is software-acc
Page 91 and 92:
CHAPTER 6 Instruction Set Overview
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6.3.1 Memory Access Instructions Lo
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Byte Address 7 0 Halfword Address{0
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Byte Address 7 0 Halfword Address{0
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6.3.2 Memory Synchronization Instru
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TABLE 6-5 Control-Transfer Characte
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6.3.4.7 DCTI Couples E2 A delayed c
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Programming Note 6.3.6.3 SAVED Inst
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In the Oracle SPARC Architecture, t
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CHAPTER ON 7 Instructions Oracle SP
Page 111 and 112:
TABLE 7-2 Oracle SPARC Architecture
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TABLE 7-3 Instruction Set - by Func
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
In the remainder of this chapter, r
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ADD 7.1 Add Instruction op3 Operati
Page 125 and 126:
AES Crypto (4-operand) 7.3 AES Cryp
Page 127 and 128:
AES Crypto (4-operand) Programming
Page 129 and 130:
AES Crypto (3-operand) Exceptions P
Page 131 and 132:
ALLCLEAN 7.6 Mark All Register Wind
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ARRAY 7.8 Three-Dimensional Array A
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ARRAY Z UPPER Y X Z MIDDLE Y X Z LO
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Bicc If a conditional branch is tak
Page 139 and 140:
BPcc 7.11 Branch on Integer Conditi
Page 141 and 142:
BPr 7.12 BranchonIntegerRegisterwit
Page 143 and 144:
CALL 7.13 Call and Link Instruction
Page 145 and 146:
CAMELLIA 4-operand Op Programming N
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CASA / CASXA 7.16 Compare and Swap
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CBcond (Compare and Branch) 7.17 Co
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CBcond (Compare and Branch) Impleme
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CMASK Programming Note It is envisi
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CRC32C Programming Note The code ex
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DES Crypto (4-operand) For each blo
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DES Crypto (2-operand) In the follo
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DONE Exceptions. In privileged mode
Page 163 and 164:
EDGE{L}N 7.24 Edge Handling Instruc
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FABS 7.25 Floating-Point Absolute V
Page 167 and 168:
FALIGNDATAg 7.27 Align Data (using
Page 169 and 170:
FBfcc If a conditional branch is ta
Page 171 and 172:
FBPfcc ■ ■ Unconditional branch
Page 173 and 174:
FCMP, FCMPE 7.31 Floating-Point Com
Page 175 and 176:
FDIV 7.32 Floating-Point Divide Ins
Page 177 and 178:
FHADD 7.34 Floating-point Add and H
Page 179 and 180:
FiTO 7.36 Convert 32-bit Integer to
Page 181 and 182:
FLCMP TABLE 7-10 Effect of Fcc Resu
Page 183 and 184:
FLUSH See implementation-specific d
Page 185 and 186:
FLUSHW 7.39 Flush Register Windows
Page 187 and 188:
FMAf Exceptions. If an FMAf instruc
Page 189 and 190:
FMEAN16 If the FPU is not enabled (
Page 191 and 192:
FMOVcc 7.43 Move Floating-Point Reg
Page 193 and 194:
FMOVcc Encoding of opf_cc Field (al
Page 195 and 196:
FMOVR 7.44 Move Floating-Point Regi
Page 197 and 198:
FMUL (partitioned) 7.45 Partitioned
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FMUL (partitioned) 7.45.3 FMUL8x16A
Page 201 and 202:
FMUL (partitioned) 7.45.7 FMULD8ULx
Page 203 and 204:
FNADD 7.47 Floating-Point Negative
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FNEG 7.48 Floating-Point Negate Ins
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FNMUL 7.50 Floating-Point Negative
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FPACK 7.51 FPACK VIS 1 Instruction
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FPACK 7.51.2 FPACK32 FPACK32 takes
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FPADD 7.52 Partitioned Add The FPAD
Page 215 and 216:
FPADD If the FPU is not enabled (FP
Page 217 and 218:
FPADDS F D [rs1] 63 32 31 0 F D [rs
Page 219 and 220:
FPCMP FIGURE 7-29 and FIGURE 7-30 i
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FPCMPU instructions F D [rs1] 63 56
Page 223 and 224:
FPMERGE 7.57 or PSTATE.pef =0FPMERG
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FPSUB F D [rs1] 63 32 31 0 F D [rs2
Page 227 and 228:
FPSUBS 7.59 Partitioned Subtract wi
Page 229 and 230:
FPSUBS F S [rs1] 31 0 F S [rs2] 31
Page 231 and 232:
F Register 2-operand Logical Ops 7.
Page 233 and 234:
FSLL / FSRL / FSRA 7.63 Partitioned
Page 235 and 236:
FSQRT Instructions 7.64 Floating-Po
Page 237 and 238:
FTO 7.66 Convert Between Floating-P
Page 239 and 240:
FSUB 7.67 Floating-Point Subtract I
Page 241 and 242:
ILLTRAP 7.69 Illegal Instruction Tr
Page 243 and 244:
JMPL 7.71 Jump and Link Instruction
Page 245 and 246:
LDA 7.73 Load Integer from Alternat
Page 247 and 248:
LDBLOCKF 7.74 Block Load VIS 1 The
Page 249 and 250:
LDBLOCKF Implementation Note LDBLOC
Page 251 and 252:
LDF / LDDF / LDQF An attempt to exe
Page 253 and 254:
LDFA / LDDFA / LDQFA An attempt to
Page 255 and 256:
LDFSR (Deprecated) 7.77 Load Floati
Page 257 and 258:
LDSHORTF 7.78 Load Short Floating-P
Page 259 and 260:
LDSTUB 7.79 Load-Store Unsigned Byt
Page 261 and 262:
LDTW (Deprecated) 7.81 Load Integer
Page 263 and 264:
LDTWA (Deprecated) 7.82 Load Intege
Page 265 and 266:
LDTWA (Deprecated) Implementation N
Page 267 and 268:
LDTXA ASIs E2 16 ,E3 16 ,EA 16 , an
Page 269 and 270:
LDXEFSR / LDXFSR Implementation Not
Page 271 and 272:
MD5 7.86 MD5 Hash Operation Crypto
Page 273 and 274:
MEMBAR The cmask field is encoded i
Page 275 and 276:
MONTMUL 7.88 MONTMUL Crypto This in
Page 277 and 278:
MONTMUL Operand Window (CWP value)
Page 279 and 280:
MONTSQR 7.89 MONTSQR Crypto This in
Page 281 and 282:
MONTSQR Operand MONTSQR Operand Loc
Page 283 and 284:
MOVcc 7.90 Move Integer Register on
Page 285 and 286:
MOVcc Description These instruction
Page 287 and 288:
MOVfTOi 7.92 Move Floating-Point Re
Page 289 and 290:
MPMUL 7.94 MPMUL Crypto This instru
Page 291 and 292:
MPMUL load_multiplicand: ldd [%g5 +
Page 293 and 294:
MPMUL stx stx stx stx stx stx stx s
Page 295 and 296:
NOP 7.96 No Operation Instruction o
Page 297 and 298:
OR 7.98 OR Logical Operation Instru
Page 299 and 300:
PAUSE 7.100 Pause Instruction op3 O
Page 301 and 302:
PDISTN 7.102 Pixel Component Distan
Page 303 and 304:
POPC Programming Note POPC is a “
Page 305 and 306:
PREFETCH If i = 0, the effective ad
Page 307 and 308:
PREFETCH NOP while a Strong prefetc
Page 309 and 310:
PREFETCH 7.104.4 Implementation-Dep
Page 311 and 312:
RDasr Description The Read Ancillar
Page 313 and 314:
RDPR 7.106 Read Privileged Register
Page 315 and 316:
RESTORE 7.107 RESTORE Instruction o
Page 317 and 318:
RESTORED 7.108 RESTORED Instruction
Page 319 and 320:
RETRY Programming Note RETRY should
Page 321 and 322:
RETURN Exceptions illegal_instructi
Page 323 and 324:
SAVE If CANSAVE ≠ 0, the SAVE ins
Page 325 and 326:
SDIV, SDIVcc (Deprecated) 7.113 Sig
Page 327 and 328:
SETHI 7.114 SETHI Instruction op2 O
Page 329 and 330:
SHA1, SHA256, SHA512 Programming No
Page 331 and 332:
SLL / SRL / SRA 7.117 Shift Instruc
Page 333 and 334:
SMUL, SMULcc (Deprecated) 7.118 Sig
Page 335 and 336:
STBA / STHA / STWA / STXA 7.120 Sto
Page 337 and 338:
STBLOCKF (deprecated) 7.121 Block S
Page 339 and 340:
STBLOCKF (deprecated) ■ ■ ■
Page 341 and 342:
STF / STDF / STQF / STXFSR An attem
Page 343 and 344:
STFA / STDFA / STQFA Implementation
Page 345 and 346:
STFSR (Deprecated) 7.124 Store Floa
Page 347 and 348:
STPARTIALF 7.125 Store Partial Floa
Page 349 and 350:
STPARTIALF STPARTIALF requires only
Page 351 and 352:
STSHORTF DAE_privilege_violation DA
Page 353 and 354:
STTW (Deprecated) Programming Notes
Page 355 and 356:
STTWA (Deprecated) STTWA can be use
Page 357 and 358:
SUB 7.130 Subtract Instruction op3
Page 359 and 360:
SWAPA (Deprecated) 7.132 Swap Regis
Page 361 and 362:
TADDcc 7.133 Tagged Add Instruction
Page 363 and 364:
Tcc 7.135 Trap on Integer Condition
Page 365 and 366:
Tcc Exceptions illegal_instruction
Page 367 and 368:
TSUBccTV (Deprecated) 7.137 Tagged
Page 369 and 370:
UDIV, UDIVcc (Deprecated) UDIV does
Page 371 and 372:
UMULXHI 7.140 Integer Multiply High
Page 373 and 374:
WRasr Description The WRasr instruc
Page 375 and 376:
WRPR 7.142 Write Privileged Registe
Page 377 and 378:
XMULX[HI] 7.143 XOR Multiply VIS 3
Page 379 and 380:
CHAPTER 8 IEEE Std 754-1985 Require
Page 381 and 382:
8.2.1 Trapped Underflow Definition
Page 383 and 384:
■ QSNaNn is the Signalling NaN op
Page 385 and 386:
For the FSUB instructions, R may be
Page 387 and 388:
TABLE 8-8 Floating-Point Negative M
Page 389 and 390:
TABLE 8-10 Floating-Point Negative
Page 391 and 392:
8.5.12 Floating-Point Compare (FCMP
Page 393 and 394:
TABLE 8-18 Floating-Point to Float-
Page 395 and 396:
CHAPTER 9 Memory The Oracle SPARC A
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Noncacheable accesses (other than b
Page 399 and 400:
■ ■ To provide additional acces
Page 401 and 402:
Processor Issue Reorder Execute Uni
Page 403 and 404:
9.5 The Oracle SPARC Architecture M
Page 405 and 406:
9.5.3 TSO Ordering Rules TABLE 9-2
Page 407 and 408:
MEMBAR serves two distinct function
Page 409 and 410:
IMPL. DEP. #122-V9: The latency bet
Page 411 and 412:
CHAPTER 10 Address Space Identifier
Page 413 and 414:
Attempting to access an address spa
Page 415 and 416:
TABLE 10-1 Oracle SPARC Architectur
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TABLE 10-1 Oracle SPARC Architectur
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TABLE 10-2 Privileged ASI_*AS_IF_US
Page 421 and 422:
TABLE 10-4 ASI Privileged Load Inte
Page 423 and 424:
10.4.11 Partial Store ASIs ASIs C0
Page 425 and 426:
CHAPTER 11 Performance Instrumentat
Page 427 and 428:
For critical performance measuremen
Page 429 and 430:
CHAPTER 12 Traps A trap is a vector
Page 431 and 432:
FIGURE 12-1 shows how a virtual pro
Page 433 and 434:
With a restartable deferred trap th
Page 435 and 436:
12.3.3.4 Trap Handler Actions for D
Page 437 and 438:
12.5.2 Privileged Trap Table Organi
Page 439 and 440:
TABLE 12-4 Exception and Interrupt
Page 441 and 442:
Page 443 and 444:
Page 445 and 446:
TABLE 12-6 describes the virtual pr
Page 447 and 448:
■ normal entry into a trap handle
Page 449 and 450:
■ ■ ■ ■ ■ ■ ■ An inst
Page 451 and 452:
12.8 Register Window Traps Window t
Page 453 and 454:
CHAPTER 13 Interrupt Handling Virtu
Page 455 and 456:
■ ■ ■ CPU mondos Resumable er
Page 457 and 458:
CHAPTER 14 Memory Management An Ora
Page 459 and 460:
63 32-Mbyte Virtual Page Number MMU
Page 461 and 462:
The above paragraphs are summarized
Page 463 and 464:
TABLE 14-2 TSB TTE Bit Description
Page 465 and 466:
14.4 Translation Storage Buffer (TS
Page 467 and 468:
TABLE 14-4 ASI Mapping for Data Acc
Page 469 and 470:
TABLE 14-7 lists the MMU registers
Page 471 and 472:
APPENDIX A Opcode Maps This appendi
Page 473 and 474:
TABLE A-3 op3{5:0} (op =10 2 ) (2 o
Page 475 and 476:
TABLE A-5 opf{8:0} (op =10 2 ,op3 =
Page 477 and 478:
TABLE A-7 cond{3:0} (or for CBcond,
Page 479 and 480:
TABLE A-12 opf{8:0} for VIS opcodes
Page 481 and 482:
TABLE A-14 opf{8:0} for VIS opcodes
Page 483 and 484:
APPENDIX B Note: This chapter is un
Page 485 and 486:
B.4 List of Implementation Dependen
Page 487 and 488:
TABLE B-1 SPARC V9 Implementation D
Page 489 and 490:
Page 491 and 492:
Page 493 and 494:
TABLE B-2 Oracle SPARC Architecture
Page 495 and 496:
Page 497 and 498:
Page 499 and 500:
APPENDIX C Assembly Language Syntax
Page 501 and 502:
%fprs Floating-Point Registers Stat
Page 503 and 504:
eg rs1 - simm13 simm13 (equivalent
Page 505 and 506:
TABLE C-2 Mapping Synthetic to SPAR
Page 507 and 508:
Index A a (annul) instruction field
Page 509 and 510:
ASI_REAL_L, 397 ASI_REAL_LITTLE, 39
Page 511 and 512:
ASR for, 49 carry (c) bit of condit
Page 513 and 514:
data_access_exception), 431 DAE_non
Page 515 and 516:
F F registers, 6, 17, 90, 363, 420
Page 517 and 518:
FMOVqZ instruction, 179 FMOVr instr
Page 519 and 520:
FxTOq instruction, 224, 460 FxTOs i
Page 521 and 522:
logical 1-operand ops on F register
Page 523 and 524:
atomic operation ordering, 391 FLUS
Page 525 and 526:
floating point move instructions, 1
Page 527 and 528:
accessing restricted ASIs, 383 desc
Page 529 and 530:
floating point arithmetic instructi
Page 531 and 532:
STWA instruction, 319 STX instructi
Page 533 and 534:
TSUBcc instruction, 83, 350 TSUBccT
Page 535 and 536:
Index 29
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Index 31
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Index 33
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Index 35
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Index 37
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Index 39
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Index 41
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Index 43
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Index 45
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Index 47
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