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V9 Compatibility Note Forward Compatibility Note Note containing information about possible differences between Oracle SPARC Architecture 2011 and SPARC V9 implementations. Such information is relevant to Oracle SPARC Architecture 2011 implementations and might not apply to other SPARC V9 implementations. Note containing information about how the Oracle SPARC Architecture is expected to evolve in the future. Such notes are not intended as a guarantee that the architecture will evolve as indicated, but as a guide to features that should not be depended upon to remain the same, by software intended to run on both current and future implementations. 1.3 Reporting Errors in this Specification This specification has been reviewed for completeness and accuracy. Nonetheless, as with any document this size, errors and omissions may occur, and reports of such are welcome. Please send “bug reports” and other comments on this document to email address: David.Weaver@Oracle.com 4 Oracle SPARC Architecture 2011 • Draft D0.9.5d, 18 Jul 2012
CHAPTER 2 Definitions This chapter defines concepts and terminology common to all implementations of Oracle SPARC Architecture 2011. address space address space identifier (ASI) aliased application program ASI ASR big-endian byte CCR clean window coherence completed (memory operation) context context ID copyback CPI cross-call A range of 2 64 locations that can be addressed by instruction fetches and load, store, or load-store instructions. See also address space identifier (ASI). An 8-bit value that identifies a particular address space. An ASI is (implicitly or explicitly) associated with every instruction access or data access. See also implicit ASI. Said of each of two virtual or real addresses that refer to the same underlying memory location. A program executed with the virtual processor in nonprivileged mode. Note: Statements made in this specification regarding application programs may not be applicable to programs (for example, debuggers) that have access to privileged virtual processor state (for example, as stored in a memory-image dump). Address space identifier. Ancillary State register. An addressing convention. Within a multiple-byte integer, the byte with the smallest address is the most significant; a byte’s significance decreases as its address increases. Eight consecutive bits of data, aligned on an 8-bit boundary. Abbreviation for Condition Codes Register. A register window in which each of the registers contain 0, a valid address from the current address space, or valid data from the current address space. A set of protocols guaranteeing that all memory accesses are globally visible to all caches on a shared-memory bus. Said of a memory transaction when an idealized memory has executed the transaction with respect to all processors. A load is considered completed when no subsequent memory transaction can affect the value returned by the load. A store is considered completed when no subsequent load can return the value that was overwritten by the store. A set of translations that defines a particular address space. See also Memory Management Unit (MMU). A numeric value that uniquely identifies a particular context. The process of sending a copy of the data from a cache line owned by a physical processor core, in response to a snoop request from another device. Cycles per instruction. The number of clock cycles it takes to execute an instruction. An interprocessor call in a system containting multiple virtual processors. 5
Page 1 and 2: Oracle SPARC Architecture 2011 One
Page 3 and 4: Copyright © 2011, Oracle and/or it
Page 5 and 6: Contents Preface. . . . . . . . . .
Page 7 and 8: 5.5.8 SOFTINT P Register (ASRs 20,
Page 9 and 10: 8.5.13 Floating-Point Lexicographic
Page 11 and 12: 14.4 Translation Storage Buffer (TS
Page 13 and 14: Preface First came the 32-bit SPARC
Page 15 and 16: Corrections and other comments rega
Page 17 and 18: CHAPTER 1 Document Overview This ch
Page 19: ■ ■ ■ ■ ■ A double period
Page 23 and 24: floating-point unit FPop FPRS FPU F
Page 25 and 26: NPC Next program counter. nucleus s
Page 27 and 28: speculative load store strand subno
Page 29 and 30: CHAPTER 3 Architecture Overview The
Page 31 and 32: 3.1.2.2 Register Windows The Oracle
Page 33 and 34: 3.2.2 Floating-Point Unit (FPU) An
Page 35 and 36: In such split-memory systems, the c
Page 37 and 38: 3.3.6 Conditional Move Conditional
Page 39 and 40: CHAPTER 4 Data Formats The Oracle S
Page 41 and 42: 4.1.1.1 Signed Integer Byte, Halfwo
Page 43 and 44: 4.2 Floating-Point Data Formats Sin
Page 45 and 46: TABLE 4-5 Floating-Point Quad-Preci
Page 47 and 48: CHAPTER 5 Registers The following r
Page 49 and 50: One set of 8 global registers is al
Page 51 and 52: The current window in the windowed
Page 53 and 54: CWP = 0 (CURRENT WINDOW POINTER) w1
Page 55 and 56: TABLE 5-2 Floating-Point Registers,
Page 57 and 58: 5.3.2 Double and Quad Floating-Poin
Page 59 and 60: TABLE 5-4 Floating-Point Condition
Page 61 and 62: 4. The value of fccn is unchanged.
Page 63 and 64: ■ if FSR.tem.ufm =1,theFSR.cexc.u
Page 65 and 66: Each virtual processor contains its
Page 67 and 68: The v bits signify whether the ALU
Page 69 and 70: PC and NPC can be indirectly set by
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RW RW RW SOFTINT P — sm int_level
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At least one STICK register must be
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TABLE 5-13 Compatibility Feature Re
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privileged_opcode exception. In add
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RW RW WSTATE P other normal 5 3 2 0
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TNPC 1 P TNPC 2 P TNPC 3 P : : : TN
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5.7.6 Processor State (PSTATE P ) R
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Address Mask (am). The PSTATE.am bi
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The maximum valid value that the TL
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Since TSTATE itself is software-acc
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CHAPTER 6 Instruction Set Overview
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6.3.1 Memory Access Instructions Lo
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Byte Address 7 0 Halfword Address{0
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Byte Address 7 0 Halfword Address{0
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6.3.2 Memory Synchronization Instru
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TABLE 6-5 Control-Transfer Characte
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6.3.4.7 DCTI Couples E2 A delayed c
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Programming Note 6.3.6.3 SAVED Inst
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In the Oracle SPARC Architecture, t
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CHAPTER ON 7 Instructions Oracle SP
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TABLE 7-2 Oracle SPARC Architecture
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TABLE 7-3 Instruction Set - by Func
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Page 119 and 120:
Page 121 and 122:
In the remainder of this chapter, r
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ADD 7.1 Add Instruction op3 Operati
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AES Crypto (4-operand) 7.3 AES Cryp
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AES Crypto (4-operand) Programming
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AES Crypto (3-operand) Exceptions P
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ALLCLEAN 7.6 Mark All Register Wind
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ARRAY 7.8 Three-Dimensional Array A
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ARRAY Z UPPER Y X Z MIDDLE Y X Z LO
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Bicc If a conditional branch is tak
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BPcc 7.11 Branch on Integer Conditi
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BPr 7.12 BranchonIntegerRegisterwit
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CALL 7.13 Call and Link Instruction
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CAMELLIA 4-operand Op Programming N
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CASA / CASXA 7.16 Compare and Swap
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CBcond (Compare and Branch) 7.17 Co
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CBcond (Compare and Branch) Impleme
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CMASK Programming Note It is envisi
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CRC32C Programming Note The code ex
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DES Crypto (4-operand) For each blo
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DES Crypto (2-operand) In the follo
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DONE Exceptions. In privileged mode
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EDGE{L}N 7.24 Edge Handling Instruc
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FABS 7.25 Floating-Point Absolute V
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FALIGNDATAg 7.27 Align Data (using
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FBfcc If a conditional branch is ta
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FBPfcc ■ ■ Unconditional branch
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FCMP, FCMPE 7.31 Floating-Point Com
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FDIV 7.32 Floating-Point Divide Ins
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FHADD 7.34 Floating-point Add and H
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FiTO 7.36 Convert 32-bit Integer to
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FLCMP TABLE 7-10 Effect of Fcc Resu
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FLUSH See implementation-specific d
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FLUSHW 7.39 Flush Register Windows
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FMAf Exceptions. If an FMAf instruc
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FMEAN16 If the FPU is not enabled (
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FMOVcc 7.43 Move Floating-Point Reg
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FMOVcc Encoding of opf_cc Field (al
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FMOVR 7.44 Move Floating-Point Regi
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FMUL (partitioned) 7.45 Partitioned
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FMUL (partitioned) 7.45.3 FMUL8x16A
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FMUL (partitioned) 7.45.7 FMULD8ULx
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FNADD 7.47 Floating-Point Negative
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FNEG 7.48 Floating-Point Negate Ins
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FNMUL 7.50 Floating-Point Negative
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FPACK 7.51 FPACK VIS 1 Instruction
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FPACK 7.51.2 FPACK32 FPACK32 takes
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FPADD 7.52 Partitioned Add The FPAD
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FPADD If the FPU is not enabled (FP
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FPADDS F D [rs1] 63 32 31 0 F D [rs
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FPCMP FIGURE 7-29 and FIGURE 7-30 i
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FPCMPU instructions F D [rs1] 63 56
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FPMERGE 7.57 or PSTATE.pef =0FPMERG
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FPSUB F D [rs1] 63 32 31 0 F D [rs2
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FPSUBS 7.59 Partitioned Subtract wi
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FPSUBS F S [rs1] 31 0 F S [rs2] 31
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F Register 2-operand Logical Ops 7.
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FSLL / FSRL / FSRA 7.63 Partitioned
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FSQRT Instructions 7.64 Floating-Po
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FTO 7.66 Convert Between Floating-P
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FSUB 7.67 Floating-Point Subtract I
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ILLTRAP 7.69 Illegal Instruction Tr
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JMPL 7.71 Jump and Link Instruction
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LDA 7.73 Load Integer from Alternat
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LDBLOCKF 7.74 Block Load VIS 1 The
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LDBLOCKF Implementation Note LDBLOC
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LDF / LDDF / LDQF An attempt to exe
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LDFA / LDDFA / LDQFA An attempt to
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LDFSR (Deprecated) 7.77 Load Floati
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LDSHORTF 7.78 Load Short Floating-P
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LDSTUB 7.79 Load-Store Unsigned Byt
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LDTW (Deprecated) 7.81 Load Integer
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LDTWA (Deprecated) 7.82 Load Intege
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LDTWA (Deprecated) Implementation N
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LDTXA ASIs E2 16 ,E3 16 ,EA 16 , an
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LDXEFSR / LDXFSR Implementation Not
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MD5 7.86 MD5 Hash Operation Crypto
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MEMBAR The cmask field is encoded i
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MONTMUL 7.88 MONTMUL Crypto This in
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MONTMUL Operand Window (CWP value)
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MONTSQR 7.89 MONTSQR Crypto This in
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MONTSQR Operand MONTSQR Operand Loc
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MOVcc 7.90 Move Integer Register on
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MOVcc Description These instruction
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MOVfTOi 7.92 Move Floating-Point Re
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MPMUL 7.94 MPMUL Crypto This instru
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MPMUL load_multiplicand: ldd [%g5 +
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MPMUL stx stx stx stx stx stx stx s
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NOP 7.96 No Operation Instruction o
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OR 7.98 OR Logical Operation Instru
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PAUSE 7.100 Pause Instruction op3 O
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PDISTN 7.102 Pixel Component Distan
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POPC Programming Note POPC is a “
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PREFETCH If i = 0, the effective ad
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PREFETCH NOP while a Strong prefetc
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PREFETCH 7.104.4 Implementation-Dep
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RDasr Description The Read Ancillar
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RDPR 7.106 Read Privileged Register
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RESTORE 7.107 RESTORE Instruction o
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RESTORED 7.108 RESTORED Instruction
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RETRY Programming Note RETRY should
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RETURN Exceptions illegal_instructi
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SAVE If CANSAVE ≠ 0, the SAVE ins
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SDIV, SDIVcc (Deprecated) 7.113 Sig
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SETHI 7.114 SETHI Instruction op2 O
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SHA1, SHA256, SHA512 Programming No
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SLL / SRL / SRA 7.117 Shift Instruc
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SMUL, SMULcc (Deprecated) 7.118 Sig
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STBA / STHA / STWA / STXA 7.120 Sto
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STBLOCKF (deprecated) 7.121 Block S
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STBLOCKF (deprecated) ■ ■ ■
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STF / STDF / STQF / STXFSR An attem
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STFA / STDFA / STQFA Implementation
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STFSR (Deprecated) 7.124 Store Floa
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STPARTIALF 7.125 Store Partial Floa
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STPARTIALF STPARTIALF requires only
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STSHORTF DAE_privilege_violation DA
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STTW (Deprecated) Programming Notes
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STTWA (Deprecated) STTWA can be use
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SUB 7.130 Subtract Instruction op3
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SWAPA (Deprecated) 7.132 Swap Regis
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TADDcc 7.133 Tagged Add Instruction
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Tcc 7.135 Trap on Integer Condition
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Tcc Exceptions illegal_instruction
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TSUBccTV (Deprecated) 7.137 Tagged
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UDIV, UDIVcc (Deprecated) UDIV does
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UMULXHI 7.140 Integer Multiply High
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WRasr Description The WRasr instruc
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WRPR 7.142 Write Privileged Registe
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XMULX[HI] 7.143 XOR Multiply VIS 3
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CHAPTER 8 IEEE Std 754-1985 Require
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8.2.1 Trapped Underflow Definition
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■ QSNaNn is the Signalling NaN op
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For the FSUB instructions, R may be
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TABLE 8-8 Floating-Point Negative M
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TABLE 8-10 Floating-Point Negative
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8.5.12 Floating-Point Compare (FCMP
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TABLE 8-18 Floating-Point to Float-
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CHAPTER 9 Memory The Oracle SPARC A
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Noncacheable accesses (other than b
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■ ■ To provide additional acces
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Processor Issue Reorder Execute Uni
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9.5 The Oracle SPARC Architecture M
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9.5.3 TSO Ordering Rules TABLE 9-2
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MEMBAR serves two distinct function
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IMPL. DEP. #122-V9: The latency bet
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CHAPTER 10 Address Space Identifier
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Attempting to access an address spa
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TABLE 10-1 Oracle SPARC Architectur
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TABLE 10-1 Oracle SPARC Architectur
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TABLE 10-2 Privileged ASI_*AS_IF_US
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TABLE 10-4 ASI Privileged Load Inte
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10.4.11 Partial Store ASIs ASIs C0
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CHAPTER 11 Performance Instrumentat
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For critical performance measuremen
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CHAPTER 12 Traps A trap is a vector
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FIGURE 12-1 shows how a virtual pro
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With a restartable deferred trap th
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12.3.3.4 Trap Handler Actions for D
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12.5.2 Privileged Trap Table Organi
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TABLE 12-4 Exception and Interrupt
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Page 443 and 444:
Page 445 and 446:
TABLE 12-6 describes the virtual pr
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■ normal entry into a trap handle
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■ ■ ■ ■ ■ ■ ■ An inst
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12.8 Register Window Traps Window t
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CHAPTER 13 Interrupt Handling Virtu
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■ ■ ■ CPU mondos Resumable er
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CHAPTER 14 Memory Management An Ora
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63 32-Mbyte Virtual Page Number MMU
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The above paragraphs are summarized
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TABLE 14-2 TSB TTE Bit Description
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14.4 Translation Storage Buffer (TS
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TABLE 14-4 ASI Mapping for Data Acc
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TABLE 14-7 lists the MMU registers
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APPENDIX A Opcode Maps This appendi
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TABLE A-3 op3{5:0} (op =10 2 ) (2 o
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TABLE A-5 opf{8:0} (op =10 2 ,op3 =
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TABLE A-7 cond{3:0} (or for CBcond,
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TABLE A-12 opf{8:0} for VIS opcodes
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TABLE A-14 opf{8:0} for VIS opcodes
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APPENDIX B Note: This chapter is un
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B.4 List of Implementation Dependen
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TABLE B-1 SPARC V9 Implementation D
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Page 491 and 492:
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TABLE B-2 Oracle SPARC Architecture
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APPENDIX C Assembly Language Syntax
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%fprs Floating-Point Registers Stat
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eg rs1 - simm13 simm13 (equivalent
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TABLE C-2 Mapping Synthetic to SPAR
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Index A a (annul) instruction field
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ASI_REAL_L, 397 ASI_REAL_LITTLE, 39
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ASR for, 49 carry (c) bit of condit
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data_access_exception), 431 DAE_non
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F F registers, 6, 17, 90, 363, 420
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FMOVqZ instruction, 179 FMOVr instr
Page 519 and 520:
FxTOq instruction, 224, 460 FxTOs i
Page 521 and 522:
logical 1-operand ops on F register
Page 523 and 524:
atomic operation ordering, 391 FLUS
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floating point move instructions, 1
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accessing restricted ASIs, 383 desc
Page 529 and 530:
floating point arithmetic instructi
Page 531 and 532:
STWA instruction, 319 STX instructi
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TSUBcc instruction, 83, 350 TSUBccT
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Index 29
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Index 31
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Index 33
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Index 35
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Index 37
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Index 39
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Index 41
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Index 43
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