sparc-architecture-2011-1728132

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3.3.5 Floating-Point Operate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.6 Conditional Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.7 Register Window Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.8 SIMD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 Integer Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 Signed Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1.1 Signed Integer Byte, Halfword, and Word. . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1.2 Signed Integer Doubleword (64 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1.3 Signed Integer Extended-Word (64 bits) . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2 Unsigned Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2.1 Unsigned Integer Byte, Halfword, and Word . . . . . . . . . . . . . . . . . . . . 26 4.1.2.2 Unsigned Integer Doubleword (64 bits). . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.2.3 Unsigned Extended Integer (64 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.3 Tagged Word (32 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 Floating-Point Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.1 Floating Point, Single Precision (32 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.2 Floating Point, Double Precision (64 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.3 Floating Point, Quad Precision (128 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.4 Floating-Point Data Alignment in Memory and Registers . . . . . . . . . . . . . . . . . 29 4.3 SIMD Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.1 Uint8 SIMD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.2 Int16 SIMD Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.3 Int32 SIMD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 Reserved Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.2 General-Purpose R Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.1 Global R Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.2 Windowed R Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.3 Special R Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3 Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.1 Floating-Point Register Number Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.2 Double and Quad Floating-Point Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.4 Floating-Point State Register (FSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.4.1 Floating-Point Condition Codes (fcc0, fcc1, fcc2, fcc3) . . . . . . . . . . . . . . . . . . . . 42 5.4.2 Rounding Direction (rd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4.3 Trap Enable Mask (tem) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4.4 Nonstandard Floating-Point (ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4.5 FPU Version (ver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4.6 Floating-Point Trap Type (ftt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4.7 Accrued Exceptions (aexc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.4.8 Current Exception (cexc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.4.9 Floating-Point Exception Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.4.10 FSR Conformance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5 Ancillary State Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5.1 32-bit Multiply/Divide Register (Y) (ASR 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.5.2 Integer Condition Codes Register (CCR) (ASR 2). . . . . . . . . . . . . . . . . . . . . . . . . 50 5.5.2.1 Condition Codes (CCR.xcc and CCR.icc) . . . . . . . . . . . . . . . . . . . . . . . 50 5.5.3 Address Space Identifier (ASI) Register (ASR 3). . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5.4 Tick (TICK) Register (ASR 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.5.5 Program Counters (PC, NPC) (ASR 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.5.6 Floating-Point Registers State (FPRS) Register (ASR 6) . . . . . . . . . . . . . . . . . . . 53 5.5.7 General Status Register (GSR) (ASR 19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ii Oracle SPARC Architecture <strong>2011</strong> • Draft D0.9.5d, 18 Jul 2012
5.5.8 SOFTINT P Register (ASRs 20, 21, 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.5.8.1 SOFTINT_SET P Pseudo-Register (ASR 20) . . . . . . . . . . . . . . . . . . . . . .55 5.5.8.2 SOFTINT_CLR P Pseudo-Register (ASR 21) . . . . . . . . . . . . . . . . . . . . . .56 5.5.9 System Tick (STICK) Register (ASR 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.5.10 System Tick Compare (STICK_CMPR P ) Register (ASR 25) . . . . . . . . . . . . . . . 57 5.5.11 Compatibility Feature Register (CFR) (ASR 26) . . . . . . . . . . . . . . . . . . . . . . . . 58 5.5.12 Pause Count (PAUSE) Register (ASR 27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.6 Register-Window PR State Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 5.6.1 Current Window Pointer (CWP P ) Register (PR 9) . . . . . . . . . . . . . . . . . . . . . . . 61 5.6.2 Savable Windows (CANSAVE P ) Register (PR 10) . . . . . . . . . . . . . . . . . . . . . . . . 61 5.6.3 Restorable Windows (CANRESTORE P ) Register (PR 11) . . . . . . . . . . . . . . . . . 62 5.6.4 Clean Windows (CLEANWIN P ) Register (PR 12) . . . . . . . . . . . . . . . . . . . . . . . . 62 5.6.5 Other Windows (OTHERWIN P ) Register (PR 13) . . . . . . . . . . . . . . . . . . . . . . . . 62 5.6.6 Window State (WSTATE P ) Register (PR 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.6.7 Register Window Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.6.7.1 Register Window State Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.6.7.2 Register Window Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.7 Non-Register-Window PR State Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.7.1 Trap Program Counter (TPC P ) Register (PR 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.7.2 Trap Next PC (TNPC P ) Register (PR 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.7.3 Trap State (TSTATE P ) Register (PR 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.7.4 Trap Type (TT P ) Register (PR 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.7.5 Trap Base Address (TBA P ) Register (PR 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.7.6 Processor State (PSTATE P ) Register (PR 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.7.7 Trap Level Register (TL P ) (PR 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.7.8 Processor Interrupt Level (PIL P ) Register (PR 8) . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.7.9 Global Level Register (GL P ) (PR 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 6.1 Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 6.2 Instruction Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.3 Instruction Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.3.1 Memory Access Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.1.1 Memory Alignment Restrictions . . . . . . . . . . . . . . . . . . . . .77 6.3.1.2 Addressing Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 6.3.1.3 Address Space Identifiers (ASIs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 6.3.1.4 Separate Instruction Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 6.3.2 Memory Synchronization Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.3 Integer Arithmetic and Logical Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.3.1 Setting Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 6.3.3.2 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 6.3.3.3 Set High 22 Bits of Low Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 6.3.3.4 Integer Multiply/Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 6.3.3.5 Tagged Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 6.3.4 Control-Transfer Instructions (CTIs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.4.1 Conditional Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6.3.4.2 Unconditional Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 6.3.4.3 CALL and JMPL Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 6.3.4.4 RETURN Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 6.3.4.5 DONE and RETRY Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 6.3.4.6 Trap Instruction (Tcc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 6.3.4.7 DCTI Couples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 6.3.5 Conditional Move Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.6 Register Window Management Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.6.1 SAVE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.3.6.2 RESTORE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.3.6.3 SAVED Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 • Contents iii
Page 1 and 2: Oracle SPARC Architecture 2011 One
Page 3 and 4: Copyright © 2011, Oracle and/or it
Page 5: Contents Preface. . . . . . . . . .
Page 9 and 10: 8.5.13 Floating-Point Lexicographic
Page 11 and 12: 14.4 Translation Storage Buffer (TS
Page 13 and 14: Preface First came the 32-bit SPARC
Page 15 and 16: Corrections and other comments rega
Page 17 and 18: CHAPTER 1 Document Overview This ch
Page 19 and 20: ■ ■ ■ ■ ■ A double period
Page 21 and 22: CHAPTER 2 Definitions This chapter
Page 23 and 24: floating-point unit FPop FPRS FPU F
Page 25 and 26: NPC Next program counter. nucleus s
Page 27 and 28: speculative load store strand subno
Page 29 and 30: CHAPTER 3 Architecture Overview The
Page 31 and 32: 3.1.2.2 Register Windows The Oracle
Page 33 and 34: 3.2.2 Floating-Point Unit (FPU) An
Page 35 and 36: In such split-memory systems, the c
Page 37 and 38: 3.3.6 Conditional Move Conditional
Page 39 and 40: CHAPTER 4 Data Formats The Oracle S
Page 41 and 42: 4.1.1.1 Signed Integer Byte, Halfwo
Page 43 and 44: 4.2 Floating-Point Data Formats Sin
Page 45 and 46: TABLE 4-5 Floating-Point Quad-Preci
Page 47 and 48: CHAPTER 5 Registers The following r
Page 49 and 50: One set of 8 global registers is al
Page 51 and 52: The current window in the windowed
Page 53 and 54: CWP = 0 (CURRENT WINDOW POINTER) w1
Page 55 and 56: TABLE 5-2 Floating-Point Registers,
Page 57 and 58:
5.3.2 Double and Quad Floating-Poin
Page 59 and 60:
TABLE 5-4 Floating-Point Condition
Page 61 and 62:
4. The value of fccn is unchanged.
Page 63 and 64:
■ if FSR.tem.ufm =1,theFSR.cexc.u
Page 65 and 66:
Each virtual processor contains its
Page 67 and 68:
The v bits signify whether the ALU
Page 69 and 70:
PC and NPC can be indirectly set by
Page 71 and 72:
RW RW RW SOFTINT P — sm int_level
Page 73 and 74:
At least one STICK register must be
Page 75 and 76:
TABLE 5-13 Compatibility Feature Re
Page 77 and 78:
privileged_opcode exception. In add
Page 79 and 80:
RW RW WSTATE P other normal 5 3 2 0
Page 81 and 82:
TNPC 1 P TNPC 2 P TNPC 3 P : : : TN
Page 83 and 84:
5.7.6 Processor State (PSTATE P ) R
Page 85 and 86:
Address Mask (am). The PSTATE.am bi
Page 87 and 88:
The maximum valid value that the TL
Page 89 and 90:
Since TSTATE itself is software-acc
Page 91 and 92:
CHAPTER 6 Instruction Set Overview
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6.3.1 Memory Access Instructions Lo
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Byte Address 7 0 Halfword Address{0
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Byte Address 7 0 Halfword Address{0
Page 99 and 100:
6.3.2 Memory Synchronization Instru
Page 101 and 102:
TABLE 6-5 Control-Transfer Characte
Page 103 and 104:
6.3.4.7 DCTI Couples E2 A delayed c
Page 105 and 106:
Programming Note 6.3.6.3 SAVED Inst
Page 107 and 108:
In the Oracle SPARC Architecture, t
Page 109 and 110:
CHAPTER ON 7 Instructions Oracle SP
Page 111 and 112:
TABLE 7-2 Oracle SPARC Architecture
Page 113 and 114:
TABLE 7-3 Instruction Set - by Func
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
In the remainder of this chapter, r
Page 123 and 124:
ADD 7.1 Add Instruction op3 Operati
Page 125 and 126:
AES Crypto (4-operand) 7.3 AES Cryp
Page 127 and 128:
AES Crypto (4-operand) Programming
Page 129 and 130:
AES Crypto (3-operand) Exceptions P
Page 131 and 132:
ALLCLEAN 7.6 Mark All Register Wind
Page 133 and 134:
ARRAY 7.8 Three-Dimensional Array A
Page 135 and 136:
ARRAY Z UPPER Y X Z MIDDLE Y X Z LO
Page 137 and 138:
Bicc If a conditional branch is tak
Page 139 and 140:
BPcc 7.11 Branch on Integer Conditi
Page 141 and 142:
BPr 7.12 BranchonIntegerRegisterwit
Page 143 and 144:
CALL 7.13 Call and Link Instruction
Page 145 and 146:
CAMELLIA 4-operand Op Programming N
Page 147 and 148:
CASA / CASXA 7.16 Compare and Swap
Page 149 and 150:
CBcond (Compare and Branch) 7.17 Co
Page 151 and 152:
CBcond (Compare and Branch) Impleme
Page 153 and 154:
CMASK Programming Note It is envisi
Page 155 and 156:
CRC32C Programming Note The code ex
Page 157 and 158:
DES Crypto (4-operand) For each blo
Page 159 and 160:
DES Crypto (2-operand) In the follo
Page 161 and 162:
DONE Exceptions. In privileged mode
Page 163 and 164:
EDGE{L}N 7.24 Edge Handling Instruc
Page 165 and 166:
FABS 7.25 Floating-Point Absolute V
Page 167 and 168:
FALIGNDATAg 7.27 Align Data (using
Page 169 and 170:
FBfcc If a conditional branch is ta
Page 171 and 172:
FBPfcc ■ ■ Unconditional branch
Page 173 and 174:
FCMP, FCMPE 7.31 Floating-Point Com
Page 175 and 176:
FDIV 7.32 Floating-Point Divide Ins
Page 177 and 178:
FHADD 7.34 Floating-point Add and H
Page 179 and 180:
FiTO 7.36 Convert 32-bit Integer to
Page 181 and 182:
FLCMP TABLE 7-10 Effect of Fcc Resu
Page 183 and 184:
FLUSH See implementation-specific d
Page 185 and 186:
FLUSHW 7.39 Flush Register Windows
Page 187 and 188:
FMAf Exceptions. If an FMAf instruc
Page 189 and 190:
FMEAN16 If the FPU is not enabled (
Page 191 and 192:
FMOVcc 7.43 Move Floating-Point Reg
Page 193 and 194:
FMOVcc Encoding of opf_cc Field (al
Page 195 and 196:
FMOVR 7.44 Move Floating-Point Regi
Page 197 and 198:
FMUL (partitioned) 7.45 Partitioned
Page 199 and 200:
FMUL (partitioned) 7.45.3 FMUL8x16A
Page 201 and 202:
FMUL (partitioned) 7.45.7 FMULD8ULx
Page 203 and 204:
FNADD 7.47 Floating-Point Negative
Page 205 and 206:
FNEG 7.48 Floating-Point Negate Ins
Page 207 and 208:
FNMUL 7.50 Floating-Point Negative
Page 209 and 210:
FPACK 7.51 FPACK VIS 1 Instruction
Page 211 and 212:
FPACK 7.51.2 FPACK32 FPACK32 takes
Page 213 and 214:
FPADD 7.52 Partitioned Add The FPAD
Page 215 and 216:
FPADD If the FPU is not enabled (FP
Page 217 and 218:
FPADDS F D [rs1] 63 32 31 0 F D [rs
Page 219 and 220:
FPCMP FIGURE 7-29 and FIGURE 7-30 i
Page 221 and 222:
FPCMPU instructions F D [rs1] 63 56
Page 223 and 224:
FPMERGE 7.57 or PSTATE.pef =0FPMERG
Page 225 and 226:
FPSUB F D [rs1] 63 32 31 0 F D [rs2
Page 227 and 228:
FPSUBS 7.59 Partitioned Subtract wi
Page 229 and 230:
FPSUBS F S [rs1] 31 0 F S [rs2] 31
Page 231 and 232:
F Register 2-operand Logical Ops 7.
Page 233 and 234:
FSLL / FSRL / FSRA 7.63 Partitioned
Page 235 and 236:
FSQRT Instructions 7.64 Floating-Po
Page 237 and 238:
FTO 7.66 Convert Between Floating-P
Page 239 and 240:
FSUB 7.67 Floating-Point Subtract I
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ILLTRAP 7.69 Illegal Instruction Tr
Page 243 and 244:
JMPL 7.71 Jump and Link Instruction
Page 245 and 246:
LDA 7.73 Load Integer from Alternat
Page 247 and 248:
LDBLOCKF 7.74 Block Load VIS 1 The
Page 249 and 250:
LDBLOCKF Implementation Note LDBLOC
Page 251 and 252:
LDF / LDDF / LDQF An attempt to exe
Page 253 and 254:
LDFA / LDDFA / LDQFA An attempt to
Page 255 and 256:
LDFSR (Deprecated) 7.77 Load Floati
Page 257 and 258:
LDSHORTF 7.78 Load Short Floating-P
Page 259 and 260:
LDSTUB 7.79 Load-Store Unsigned Byt
Page 261 and 262:
LDTW (Deprecated) 7.81 Load Integer
Page 263 and 264:
LDTWA (Deprecated) 7.82 Load Intege
Page 265 and 266:
LDTWA (Deprecated) Implementation N
Page 267 and 268:
LDTXA ASIs E2 16 ,E3 16 ,EA 16 , an
Page 269 and 270:
LDXEFSR / LDXFSR Implementation Not
Page 271 and 272:
MD5 7.86 MD5 Hash Operation Crypto
Page 273 and 274:
MEMBAR The cmask field is encoded i
Page 275 and 276:
MONTMUL 7.88 MONTMUL Crypto This in
Page 277 and 278:
MONTMUL Operand Window (CWP value)
Page 279 and 280:
MONTSQR 7.89 MONTSQR Crypto This in
Page 281 and 282:
MONTSQR Operand MONTSQR Operand Loc
Page 283 and 284:
MOVcc 7.90 Move Integer Register on
Page 285 and 286:
MOVcc Description These instruction
Page 287 and 288:
MOVfTOi 7.92 Move Floating-Point Re
Page 289 and 290:
MPMUL 7.94 MPMUL Crypto This instru
Page 291 and 292:
MPMUL load_multiplicand: ldd [%g5 +
Page 293 and 294:
MPMUL stx stx stx stx stx stx stx s
Page 295 and 296:
NOP 7.96 No Operation Instruction o
Page 297 and 298:
OR 7.98 OR Logical Operation Instru
Page 299 and 300:
PAUSE 7.100 Pause Instruction op3 O
Page 301 and 302:
PDISTN 7.102 Pixel Component Distan
Page 303 and 304:
POPC Programming Note POPC is a “
Page 305 and 306:
PREFETCH If i = 0, the effective ad
Page 307 and 308:
PREFETCH NOP while a Strong prefetc
Page 309 and 310:
PREFETCH 7.104.4 Implementation-Dep
Page 311 and 312:
RDasr Description The Read Ancillar
Page 313 and 314:
RDPR 7.106 Read Privileged Register
Page 315 and 316:
RESTORE 7.107 RESTORE Instruction o
Page 317 and 318:
RESTORED 7.108 RESTORED Instruction
Page 319 and 320:
RETRY Programming Note RETRY should
Page 321 and 322:
RETURN Exceptions illegal_instructi
Page 323 and 324:
SAVE If CANSAVE ≠ 0, the SAVE ins
Page 325 and 326:
SDIV, SDIVcc (Deprecated) 7.113 Sig
Page 327 and 328:
SETHI 7.114 SETHI Instruction op2 O
Page 329 and 330:
SHA1, SHA256, SHA512 Programming No
Page 331 and 332:
SLL / SRL / SRA 7.117 Shift Instruc
Page 333 and 334:
SMUL, SMULcc (Deprecated) 7.118 Sig
Page 335 and 336:
STBA / STHA / STWA / STXA 7.120 Sto
Page 337 and 338:
STBLOCKF (deprecated) 7.121 Block S
Page 339 and 340:
STBLOCKF (deprecated) ■ ■ ■
Page 341 and 342:
STF / STDF / STQF / STXFSR An attem
Page 343 and 344:
STFA / STDFA / STQFA Implementation
Page 345 and 346:
STFSR (Deprecated) 7.124 Store Floa
Page 347 and 348:
STPARTIALF 7.125 Store Partial Floa
Page 349 and 350:
STPARTIALF STPARTIALF requires only
Page 351 and 352:
STSHORTF DAE_privilege_violation DA
Page 353 and 354:
STTW (Deprecated) Programming Notes
Page 355 and 356:
STTWA (Deprecated) STTWA can be use
Page 357 and 358:
SUB 7.130 Subtract Instruction op3
Page 359 and 360:
SWAPA (Deprecated) 7.132 Swap Regis
Page 361 and 362:
TADDcc 7.133 Tagged Add Instruction
Page 363 and 364:
Tcc 7.135 Trap on Integer Condition
Page 365 and 366:
Tcc Exceptions illegal_instruction
Page 367 and 368:
TSUBccTV (Deprecated) 7.137 Tagged
Page 369 and 370:
UDIV, UDIVcc (Deprecated) UDIV does
Page 371 and 372:
UMULXHI 7.140 Integer Multiply High
Page 373 and 374:
WRasr Description The WRasr instruc
Page 375 and 376:
WRPR 7.142 Write Privileged Registe
Page 377 and 378:
XMULX[HI] 7.143 XOR Multiply VIS 3
Page 379 and 380:
CHAPTER 8 IEEE Std 754-1985 Require
Page 381 and 382:
8.2.1 Trapped Underflow Definition
Page 383 and 384:
■ QSNaNn is the Signalling NaN op
Page 385 and 386:
For the FSUB instructions, R may be
Page 387 and 388:
TABLE 8-8 Floating-Point Negative M
Page 389 and 390:
TABLE 8-10 Floating-Point Negative
Page 391 and 392:
8.5.12 Floating-Point Compare (FCMP
Page 393 and 394:
TABLE 8-18 Floating-Point to Float-
Page 395 and 396:
CHAPTER 9 Memory The Oracle SPARC A
Page 397 and 398:
Noncacheable accesses (other than b
Page 399 and 400:
■ ■ To provide additional acces
Page 401 and 402:
Processor Issue Reorder Execute Uni
Page 403 and 404:
9.5 The Oracle SPARC Architecture M
Page 405 and 406:
9.5.3 TSO Ordering Rules TABLE 9-2
Page 407 and 408:
MEMBAR serves two distinct function
Page 409 and 410:
IMPL. DEP. #122-V9: The latency bet
Page 411 and 412:
CHAPTER 10 Address Space Identifier
Page 413 and 414:
Attempting to access an address spa
Page 415 and 416:
TABLE 10-1 Oracle SPARC Architectur
Page 417 and 418:
TABLE 10-1 Oracle SPARC Architectur
Page 419 and 420:
TABLE 10-2 Privileged ASI_*AS_IF_US
Page 421 and 422:
TABLE 10-4 ASI Privileged Load Inte
Page 423 and 424:
10.4.11 Partial Store ASIs ASIs C0
Page 425 and 426:
CHAPTER 11 Performance Instrumentat
Page 427 and 428:
For critical performance measuremen
Page 429 and 430:
CHAPTER 12 Traps A trap is a vector
Page 431 and 432:
FIGURE 12-1 shows how a virtual pro
Page 433 and 434:
With a restartable deferred trap th
Page 435 and 436:
12.3.3.4 Trap Handler Actions for D
Page 437 and 438:
12.5.2 Privileged Trap Table Organi
Page 439 and 440:
TABLE 12-4 Exception and Interrupt
Page 441 and 442:
Page 443 and 444:
Page 445 and 446:
TABLE 12-6 describes the virtual pr
Page 447 and 448:
■ normal entry into a trap handle
Page 449 and 450:
■ ■ ■ ■ ■ ■ ■ An inst
Page 451 and 452:
12.8 Register Window Traps Window t
Page 453 and 454:
CHAPTER 13 Interrupt Handling Virtu
Page 455 and 456:
■ ■ ■ CPU mondos Resumable er
Page 457 and 458:
CHAPTER 14 Memory Management An Ora
Page 459 and 460:
63 32-Mbyte Virtual Page Number MMU
Page 461 and 462:
The above paragraphs are summarized
Page 463 and 464:
TABLE 14-2 TSB TTE Bit Description
Page 465 and 466:
14.4 Translation Storage Buffer (TS
Page 467 and 468:
TABLE 14-4 ASI Mapping for Data Acc
Page 469 and 470:
TABLE 14-7 lists the MMU registers
Page 471 and 472:
APPENDIX A Opcode Maps This appendi
Page 473 and 474:
TABLE A-3 op3{5:0} (op =10 2 ) (2 o
Page 475 and 476:
TABLE A-5 opf{8:0} (op =10 2 ,op3 =
Page 477 and 478:
TABLE A-7 cond{3:0} (or for CBcond,
Page 479 and 480:
TABLE A-12 opf{8:0} for VIS opcodes
Page 481 and 482:
TABLE A-14 opf{8:0} for VIS opcodes
Page 483 and 484:
APPENDIX B Note: This chapter is un
Page 485 and 486:
B.4 List of Implementation Dependen
Page 487 and 488:
TABLE B-1 SPARC V9 Implementation D
Page 489 and 490:
Page 491 and 492:
Page 493 and 494:
TABLE B-2 Oracle SPARC Architecture
Page 495 and 496:
Page 497 and 498:
Page 499 and 500:
APPENDIX C Assembly Language Syntax
Page 501 and 502:
%fprs Floating-Point Registers Stat
Page 503 and 504:
eg rs1 - simm13 simm13 (equivalent
Page 505 and 506:
TABLE C-2 Mapping Synthetic to SPAR
Page 507 and 508:
Index A a (annul) instruction field
Page 509 and 510:
ASI_REAL_L, 397 ASI_REAL_LITTLE, 39
Page 511 and 512:
ASR for, 49 carry (c) bit of condit
Page 513 and 514:
data_access_exception), 431 DAE_non
Page 515 and 516:
F F registers, 6, 17, 90, 363, 420
Page 517 and 518:
FMOVqZ instruction, 179 FMOVr instr
Page 519 and 520:
FxTOq instruction, 224, 460 FxTOs i
Page 521 and 522:
logical 1-operand ops on F register
Page 523 and 524:
atomic operation ordering, 391 FLUS
Page 525 and 526:
floating point move instructions, 1
Page 527 and 528:
accessing restricted ASIs, 383 desc
Page 529 and 530:
floating point arithmetic instructi
Page 531 and 532:
STWA instruction, 319 STX instructi
Page 533 and 534:
TSUBcc instruction, 83, 350 TSUBccT
Page 535 and 536:
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Index 31
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Index 33
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Index 35
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Index 37
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Index 39
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Index 41
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Index 43
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Index 45
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Index 47
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