sparc-architecture-2011-1728132

The instruction following a delayed control-transfer instruction is called a delay instruction. Setting
the annul bit in a conditional delayed control-transfer instruction causes the delay instruction to be
annulled (that is, to have no effect) if and only if the branch is not taken. Setting the annul bit in an
unconditional delayed control-transfer instruction (“branch always”) causes the delay instruction to
be always annulled.
Note
The SPARC V8 architecture specified that the delay instruction
was always fetched, even if annulled, and that an annulled
instruction could not cause any traps. The SPARC V9
architecture does not require the delay instruction to be fetched
if it is annulled.
Branch and CALL instructions use PC-relative displacements. The jump and link (JMPL) and return
(RETURN) instructions use a register-indirect target address. They compute their target addresses
either as the sum of two R registers or as the sum of an R register and a 13-bit signed immediate
value. The “branch on condition codes without prediction” instruction provides a displacement of ±8
Mbytes; the “branch on condition codes with prediction” instruction provides a displacement of ±1
Mbyte; the “branch on register contents” instruction provides a displacement of ±128 Kbytes; and the
CALL instruction’s 30-bit word displacement allows a control transfer to any address within ± 2
gigabytes (± 2 31 bytes).
Note
The return from privileged trap instructions (DONE and
RETRY) get their target address from the appropriate TPC or
TNPC register.
3.3.4 State Register Access
3.3.4.1 Ancillary State Registers
The read and write ancillary state register instructions read and write the contents of ancillary state
registers visible to nonprivileged software (Y, CCR, ASI, PC, TICK, and FPRS) and some registers
visible only to privileged software (SOFTINT and STICK_CMPR).
IMPL. DEP. #8-V8-Cs20: Ancillary state registers (ASRs) in the range 0–27 that are not defined in
Oracle SPARC Architecture 2011 are reserved for future architectural use.
IMPL. DEP. #9-V8-Cs20: The privilege level required to execute each of the implementationdependent
read/write ancillary state register instructions (for ASRs 28–31) is implementation
dependent.
3.3.4.2 PR State Registers
The read and write privileged register instructions (RDPR and WRPR) read and write the contents of
state registers visible only to privileged software (TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL,
PIL, CWP, CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, and WSTATE).
3.3.5 Floating-Point Operate
Floating-point operate (FPop) instructions perform all floating-point calculations; they are register-toregister
instructions that operate on the floating-point registers. FPops compute a result that is a
function of one , two, or three source operands. The groups of instructions that are considered FPops
are listed in Floating-Point Operate (FPop) Instructions on page 90.
20 Oracle SPARC Architecture 2011 • Draft D0.9.5d, 18 Jul 2012