a new European training program for deep submicron CMOS design

IDESA: a new European training program for deep submicron CMOS design
Wieslaw Kuzmicz 1
1. Inst. of Microelectronics and Optoelectronics, Warsaw University of Technology,
Koszykowa 75, 00-662 Warszawa, Poland; wbk@imio.pw.edu.pl
ABSTRACT
The goal of IDESA – a new European training program – is to
bridge the gap between the industrial design flows for nanometer
CMOS ICs and the design knowledge and skills at European
universities. Two main components of IDESA are: a series of
intensive hands-on training courses and a collection of advanced
seminars to be recorded and distributed on DVD-ROMs. IDESA is
supported by the EC in the 7 th Framework Program.
1. INTRODUCTION
Ability to design complex electronic systems in the form of
„system-on-chip” (SoC) VLSI circuits is crucial for
competitiveness of European industries. The semiconductor
industry introduces new generation of CMOS technology
approximately every two years. Unfortunately, most
European universities are lagging behind the fast evolution
of process technology. Whereas industry is now
manufacturing integrated circuits in 90 nm, 65 nm and even
45 nm technologies, most universities in their teaching and
research are still at the level of 350 nm down to 180 nm and
130 nm technologies and design flows appropriate for them.
One of the reasons of this gap is economical: the cost of
processed silicon per unit area increases quickly with
increasing process complexity. This is not a problem in the
case of large industrial designs, because the device count
per unit area increases faster, and as a result the cost of a
single transistor goes down, not up. Therefore, SoCs
designed in more advanced technologies may in large
volume manufacturing be not only faster, but also less
expensive. This is not the case with university designs.
Whether educational or research oriented, university
designs are orders of magnitude smaller than large
industrial SoC designs. Since there is a minimum silicon
area that must be paid for when a prototype circuit is
ordered, universities may be forced to pay a lot for
processed silicon, which is often partly unused. This
problem has been noticed several years ago by
EUROPRACTICE, when first deep submicron processes
became available, and it was addressed by introducing the
Mini@sic [1] action, where a number of university designs
share a silicon module of minimum size accepted by the
foundry. The Mini@sic action (together with general
reduction of prices) helped to make silicon implementation
and prototyping more affordable. Unfortunately, the
number of university designs submitted for prototyping in
deep submicron technologies, although increasing, is still
relatively low.
The problem is in increasing complexity of the design
flow and many new design problems that must be overcome
by the designers. For advanced technologies (90 nm and
beyond) a lot of new issues relating to performance and
yield are becoming very important and they affect the
design and implementation flow in major ways. These
issues include such problems as variability, leakage, low
supply voltage, complexity of design rules etc.
The industry response includes new design
methodologies and EDA tools that have been introduced to
address these issues. Unfortunately, the universities do not
have the experience and neither incentives nor resources to
independently follow these trends. Some universities even
feel forced to drop silicon implementation oriented courses
and focus on software and FPGA-based system design only.
In view of insufficient number of skilled VLSI designers on
the European job market this is a major loss for the
European industry.
The goal of the IDESA action is to bridge the gap
between the industrial design flows, methodologies and
tools that have already reached maturity for the 90 nm
technology node and that are being quickly extended to the
65 nm and 45 nm nodes and beyond, and the design
knowledge, competences and skills at European
universities. IDESA is a European-scale action supported
by the EC in the 7th Framework Program that will help to
disseminate quickly the necessary knowledge and skills.
2. IDESA ACTIVITIES AND PARTNERS
There are two main components of IDESA: intensive
training courses and development of a set of advanced
seminars. The target audience in both cases is academic
teaching staff, including PhD students. IDESA is based on
the “train the trainers” concept. While the courses will
focus on 90 nm CMOS processes as the mainstream,
mature deep submicron technology available to universities
today, and related design flows and tools, advanced
seminars will present and discuss emerging problems in
more advanced processes, in order to facilitate transition to
65 nm, 45 nm and beyond.
The teaching materials accompanying the courses will
be made available to participants of the courses for
unrestricted use in university curricula, lectures and
exercises. However, commercial use of the materials will
be prohibited. The same rule will apply to advanced
seminars. They will be in public domain, for free reuse in
university training, but not for commercial use of any kind.
In the beginning of 2009 an IDESA workshop is
planned, as a fringe event of a major European conference.
The workshop will serve two purposes: dissemination of
information about IDESA events in 2009, and exchange of
experiences and best practice case studies in training. The
venue and date is not known yet.
The courses as well as the seminars will be developed by
IDESA partners and invited experts from other universities,
the semincoductor industry and leading EDA companies.
The project is coordinated by IMEC, Leuven, Belgium, and
the project consortium includes:
• École Polytechnique Fédérale de Lausanne, Switzerland,
• Technische Universiteit Delft, the Netherlands,
• Rutherford Appleton Laboratory, Chilton, UK,
• Slovak Technical University, Bratislava, Slovakia,
• Warsaw University of Technology, Poland,

• Katholieke Universiteit Leuven, Belgium,
• CEA LETI, Grenoble, France.
3. INTENSIVE TRAINING COURSES
IDESA will organize several 4- or 5-day courses on
advanced IC implementation flow, targeting professors,
post-docs and PhD students. All courses will include
lectures and hands-on training sessions. Participation in the
courses will be free of charge, except small fee (typically
50 € per day) covering costs of training material, coffee
breaks and other expenses of local organizers. The
participants will be, however, responsible for their travel
and lodging expenses. The idea is to make the courses
affordable for university staff in all European countries.
Therefore, the courses will be repeated in many regions of
Europe in order to minimize travel costs.
Four courses are planned:
A. Advanced analog implementation flow
This 5-day course will start with a short overview of the
90 nm IC process flow, it will cover device modelling
issues, hand calculation versus simulation accuracy,
transistor level and behavioral level design, analog cell
trimming using digital functions, mixed mode simulation,
mismatch and yield modelling and analysis, and analog
modelling and circuit optimisation.
B. Advanced RF implementation flow
This 5-day RF implementation flow course will start
with a short overview of the RF 90 nm IC process flow, it
will cover device modelling issues, microwave passive
component design and simulation, testing and microwave
measurements, mismatch modelling and simulation, mixedmode
SoC design and simulation, analog and RF cell
trimming using digital functions, 90 nm design verification,
circuit packaging and ESD-protection.
C. Advanced digital physical implementation flow
This 5-day course will start by introducing the
challenges for 90 nm SoC design and the design
environment. The course will proceed with digital
synthesis, leakage-aware design, design planning and
floorplanning, library analysis and management. It will
focus upon low power design flow covering techniques to
minimise dynamic and static power consumption, multiple
clock tree synthesis, test and multimode and multicorner
optimisation. IR-drop analysis, dynamic power analysis
sign-off and design finishing and layout verification will be
covered. Extensive hands-on labs are part of the course.
D. Design for manufacturing flow
This 4-day course will introduce the advanced IC
manufacturing flow, and will focus upon defectivity, postlayout
manufacturability issues such as optical proximity
correction (OPC) and will include litho simulations and
process window issues. After these process oriented topics,
the course will address design and layout for litho
manufacturability, with proper attention for the back-end
dual damascene copper interconnect issues. Hands-on
sessions on DFM solutions and yield analysis, design-fortest
and yield management will be included.
4. ADVANCED SEMINARS
The portfolio of seminars will include about 30 seminars,
from 1 to 3 hours each, covering several major domains:
• variability and reliability effects,
• design countermeasures (related to variability, leakage
etc.),
• leakage, low power and low voltage issues,
• advanced device issues.
Some of the seminars will include exercise material to
allow the students to achieve deeper understanding of the
topic.
An innovative aspect here is that these seminars will be
recorded and distributed to interested universities using
state-of-the-art multimedia technologies.
5. PRACTICAL INFORMATION
IDESA Web site [2] is the main source of information
about the project. It allows also to register for the courses.
The first courses have already been announced. They will
take place in May (course D in Leuven and course B in
Delft), June (course A in Lausanne) and August (course C
in Leuven). The Web site will also publish the list of
recorded seminars when they become available for
distribution.
6. CONCLUSIONS
It is crucial for competitiveness of European industries to
maintain competences in VLSI and SoC design, including
design in the most advanced deep submicron technologies.
The IDESA action will help to keep and expand VLSI and
SoC design courses (including physical implementation) in
the curricula of European universities and follow industrial
trends.
ACKNOWLEDGMENTS
Collaboration of all project partners, and in particular Bart De
Mey from IMEC, is gratefully acknowledged. IDESA is funded by
the EC 7 th Framework Program, Grant Agreement No. 215180.
REFERENCES
[1] Mini@sic: information available at http://www.europracticeic.com/prototyping_minisic.php
[2] IDESA Web site: http://www.idesa-training.org/