Online proceedings - EDA Publishing Association

International Workshop on
THERMal INvestigations of ICs and Systems
7-9 OCTOBER 2009, LEUVEN, BELGIUM
THERMINIC
2009
http://cmp.imag.fr
Sponsored by :

COLLECTION OF PAPERS PRESENTED AT THE
15 th International Workshop on
THERMal INvestigation of ICs
and Systems
Leuven, Belgium
7-9 October 2009
Sponsored by:
The Institute of Electrical & Electronics
Engineers, Inc.
IEEE Components, Packaging and
Manufacturing Technology Society

7-9 October 2009, Leuven, Belgium
©EDA Publishing Association /THERMINIC2009 ISBN: 978-2-35500-010-2
IEEE Catalog Number: CFP09TII
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• Cambridge Scientific Abstracts
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• EU Funded Driver Project Open Archives
Additional copies of this PROCEEDINGS or copies of previous years may be purchased from:
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Fax: +33 4 76 47 38 14 –
Order forms available at: http://cmp.imag.fr/conferences
Visit EDA Publishing Association http://www.eda-publishing.org Since 2005 proceedings are available on-line.
©EDA Publishing/THERMINIC 2009
II ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
WORKSHOP COMMITTEE:
General Chair:
Vice General Chair:
Programme Chair:
B. Courtois, CMP Grenoble, France
M. Rencz, BUTE, Budapest, Hungary
T. Baelmans, KU Leuven, Belgium
Local Organizing Committee: B. Vandevelde, IMEC, Belgium
T. Persoons, KU Leuven, Belgium
PROGRAMME COMMITTEE:
Y.C. Gerstenmaier, Siemens AG, Germany
I. Barsony, KFKI-ATKI, Hungary
H. Chiueh, National Chiao Tung U., Taiwan
A. Daniel, Intel, USA
G. De Mey, Ghent U., Belgium
R. Egawa, Tohoku U., Japan
W. Faris, IIUM, Malaysia
S. Garimella, Purdue U., West Lafayette, USA
Y. Gianchandani, U. of Michigan, USA
A. Glezer, The Georgia Inst. of Techno., USA
B. Michel, IBM Zurich, Rueschlikon, Switzerland
V. Natarajan, Intel India, Bangalore, India
A.o Rubio, UPC, Spain
M-N. Sabry, U. Française d’Égypte, Egypt
A. Shakouri, U. of California, USA
E. Suhir, U.C Santa Cruz, USA
G. Wachutka, TU München, Germany
F. Udrea, U. of Cambridge, UK
A. Poppe, BUTE, Budapest, Hungary
B. Guenin, Sun Microsystems, USA
K. Chakrabarty, Duke, USA
D. Blackburn, NIST, USA
A. Aranyosi, Electronic Cooling Solutions Inc.
T. Zahner, OSRAM, Germany
A. Napieralski, TU Lodz, Poland
P. Raad, South. Methodist U., USA
J. Janssen, NXP Semiconductors, Nijmegen,
The Netherlands
L. Codecasa, Polit. di Milano, Italy
Y. Scudeller, E.Polytech. U. Nantes, France
H. Pape, Infineon Techn., Germany
V. Tsoi, Huawei Techno, Kista, Sweden
T. Baba, Nat. Metrology Institute Tsukuba,
Japan
F. Christiaens, Alcatel Bell, Belgium
J. Parry, Flomerics, Hampton Court, UK
M. Shin, Myong Ji U., Korea
P. Rodgers, The Petroleum Inst., UAE
A. Tay, NUS, Singapore
W. Claeys, U. Bordeaux, France
N. Taketoshi, AUST, Ivbaraki, Japan
K. Yazawa, Sony, Tokyo, Japan
A-C. Pliska, CSEM, Neuchâtel, Switzerland
©EDA Publishing/THERMINIC 2009
III ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
©EDA Publishing/THERMINIC 2009 IV ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
PREFACE
THERMINIC Workshops are a series of events to discuss the essential thermal questions of microelectronic
microstructures and electronic parts in general. These questions are becoming more and more crucial with the increasing
element density of circuits packaged together and with the move to nanotechnology. Thermal management is expected to
become an increasingly dominating factor of the cost of the total system. All these trends are calling for thermal
simulation, monitoring and cooling. New developments such as the moving parts of microsystems raise new thermal
problems to be solved in the near future necessitating the regular discussion of the experts in these fields. In addition, new
materials have to be created to assure the manageability of the increased thermal stress and to answer the challenges of the
nano-era.
Previous THERMINIC Workshops have been held in Grenoble (1995), Budapest (1996), Cannes (1997 and 1998), Rome
(1999), Budapest (2000), Paris (2001) Madrid (2002), Aix-en-Provence (2003) Sophia Antipolis (2004), Belgirate (2005)
in Nice (2006) Budapest (2007) and in Rome (2008).
THERMINIC 2009 programme includes 2 invited talks 34 oral in 9 sessions and 10 poster presentations including 2
special sessions on Nanopack and 1 invited talk.
Out of the submissions accepted by the Programme Committee, this volume -- which is the informal proceedings of the
Workshop -- contains the paper versions of one invited speaker presentation, 34 oral presentations and 9 poster
presentations.
We would like to express our sincere appreciation to the authors for their high quality contributions, their cooperation and
efforts. In addition, we would like to thank the members of the Workshop Programme Committee for carrying out the
paper selection work with care and competence.
Bernard Courtois
General Chair
Márta Rencz
Vice General Chair
Martine. Baelmans
Programme Chair
©EDA Publishing/THERMINIC 2009 V
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
©EDA Publishing/THERMINIC 2009 VI
ISBN: 978-2-35500-010-2

Table of Contents
Sachin Sachin S. Sapatnekar S. Sapatnekar
Wednesday University University of 7 Minnesota, of Minnesota,
October 2009
USA USA
Invited speaker: Sachin S. Sapatnekar, University of Minnesota, USA
Temperature as a First-Class Citizen in Chip Design................................................................................ 1
Sachin S. Sapatnekar
Abstract- Abstract-
Session With 1.1 Thermal new With technology new technology
modelling: trends, trends, arising arising
System through through
levela
a
confluence confluence of factors of factors such as such Moore's as Moore's law scaling law scaling and 3D and 3D
integration, integration, the role the of role thermal of thermal design design is inexorably is inexorably shifting shifting from from
package-centric Toward package-centric a issues Rational issues towards towards Modeling on-chip on-chip optimizations. of optimizations. Convection.............................................................................................. This talk This talk
2
overviews M. overviews N. Sabry the roots the of roots this of change, this change, the circuit the circuit effects effects of elevated of elevated
temperatures, temperatures, and on-chip and on-chip optimizations optimizations for effective for effective thermal thermal
management. management.
Equivalent Electrothermal Circuit Model for Vertical-Cavity Surface-Emitting
Lasers on Silicon Optical Bench........................................................................................................................ 8
C. C. Chen, C. Singh, Y. C. Chen, Hsu-Liang Hsiao, Chia-Yu Lee, Y. T. Cheng, Mount-Learn Wu
Text unavailable Text unavailable at the time at the of time printing. of printing.
Geothermal Cooling Solution Research For Outdoor Cabinet.................................................... 13
Yuping Hong, Yuening Li, Jian Shi
A New Methodology for Early Stage Thermal Analysis of Complex Electronic
Systems........................................................................................................................................................................... 17
O. Martins, N. Peltier, S. Guédon, S. Kaiser, Y. Marechal, Y. Avenas
Session 1.2 Thermal modelling and simulation: IC level
Validation Studies of DELPHI-type Boundary - Condition-Independent Compact
Thermal Model for an Opto-Electronic Package.................................................................................. 23
Arun P. Raghupathy, Attila Aranyosi, William Malt
Spatial and temporal temperature variations in CMOS designs.................................................... 31
J.H.J.Janssen, H.J.M.Veendrick
Numerical Simulation of Complex Submicron Devices with Experimentally
Determined Power Maps........................................................................................................................................ 36
Peter E. Raad, Mihai G. Burzo, Pavel L. Komarov
Design Modeling and Simulation of Electrothermally Actuated Microgyroscope
Fabricated using the MetalMUMPs.................................................................................................................. 40
Rana I. Shakoor, Shafaat A. Bazaz, M. M. Hasan
Session 1.3 Thermal simulation: 3D chip architectures
7-9 October 7-9 October 2009, 2009, Leuven, Leuven, Belgium Belgium
Temperature as as a First-Class a Citizen Citizen in Chip in Chip Design Design
Fine Grain Thermal Modeling of 3D Stacked Structures.................................................................. 45
H. Oprins, M. Cupak, G. Van der Plas, P. Marchal, B. Vandevelde, A. Srinivasan, E. Cheng
Emulation-Based Transient Thermal Modeling of 2D/3D Systems-on-Chip with Active
Cooling........................................................................................................................................................................... 50
David Atienza
Thermal Analysis of Hot Spots in Advanced 3DStacked Structures........................................... 56
C. Torregiani, B. Vandevelde, H. Oprins, E. Beyne, I. De Wolf
©EDA ©EDA Publishing/THERMINIC Publishing/THERMINIC 2009 2009 VII 1 1
ISBN: ISBN: 978-2-35500-010-2
978-2-35500-010-2

Poster session: Introduction*
7-9 October 7-9 October 2009, 2009, Leuven, Leuven, Belgium Belgium
Temperature as as a First-Class a Citizen Citizen in Chip in Chip Design Design
Thermal Issues of Solar Irradiation Sensor............................................................................................ Sachin Sachin S. Sapatnekar S. Sapatnekar
61
B. Plesz, Á. Földváry, E. Bándy
University University of Minnesota, of Minnesota,
USA USA
Thermal Simulation and Package Investigation of Wireless Gas Sensors Microsystems... 66
Andrea Paoli, Lucia Seminara, Daniele D. Caviglia, Alessandro Garibbo, Maurizio Valle
Electro-thermal simulation: a new Subsystem in Mentor Graphics IC Design Flow......... 70
K.O. Abstract- Abstract-
Petrosjanc, With new With
N.I. Ryabov, technology new technology
I.A. trends, trends,
Kharitonov, arising arising
P.A. through through
Kozynkoa
a
confluence confluence of factors of factors such as such Moore's as Moore's law scaling law scaling and 3D and 3D
integration, integration, the role the of role thermal of thermal design design is inexorably is inexorably shifting shifting from from
package-centric
Thermoelectric package-centric issues issues towards
Energy towards on-chip
Scavenging on-chip optimizations. optimizations. from
This
Waste
talk This talk Heat of Power Amplifier Transistors..... 75
overviews Kyoung overviews Joon the roots Kim, the of roots Marc this of Hodes change, this change, the circuit the circuit effects effects of elevated of elevated
temperatures, temperatures, and on-chip and on-chip optimizations optimizations for effective for effective thermal thermal
management. management.
Practical Realization of PTAT Sensor for ASIC Overheat Protection ........................................ 80
M. Szermer, M. Janicki, Z. Kulesza, A. Napieralski
Thermo-Mechanical Text unavailable Text unavailable at the time at the Reliability of time printing. of printing. Loop In Device Modeling................................................................ 84
T. Bieniek, G. Janczyk, P. Grabiec, J. Szynka
A Temperature-Dependent POWER MOSFET Mode1 for Switching Application........................... 87
H. DIA, J.B. Sauveplane, P. Tounsi, J-M. Dorkel
Crack Tip Localization of Sub-critical Crack Growth by Means of IR-Imaging
and Pulse Excitation............................................................................................................................................... 91
D. May, B. Wunderle, R. Schacht, B. Michel
Thermal matching of a thermoelectric energy harvester with the environment
and its application in wearable self-powered wireless medical sensors............................. 95
V. Leonov, P. Fiorini, T. Torfs, R. J. M. Vullers, C. Van Hoof
Thursday 8 October 2009
Invited speaker: Suresh V. Garimella Purdue University, West Lafayette, USA
Boiling Heat Transfer and Flow Regimes in Microchannels – a Comprehensive
Understanding......................................................................................................................................................... 101
Suresh V. Garimella, Tannaz Harirchian
Session 2.1 Coupled modelling: electro/thermo/mechanical
Impact of Moisture Absorption on Warpage of Large BGA packages during
a lead-free reflow process.............................................................................................................................. 113
B. Vandevelde, R. Deweerdt, F. Duflos, M. Gonzalez, D. Vanderstraeten, Eddy Blansaer, Guy Brizar, Renaud Gillon
Evaluation of Materials for High Temperature IC Packaging...................................................... 117
Robert Klieber, Renee Lerch
Electro-thermal modeling of different LEP-thickness white OLEDs....................................... 121
Ernő Kollár, Gusztáv Hantos
Electro-Thermal Simulation of Multi-channel Power Devices on PCB with SPICE............ 124
Torsten Hauck, Wim Teulings, Evgenii Rudnyi
©EDA ©EDA Publishing/THERMINIC Publishing/THERMINIC 2009 2009 VIII 1 1
ISBN: ISBN: 978-2-35500-010-2
978-2-35500-010-2

Session 2.2 Thermal measurements and analysis
7-9 October 7-9 October 2009, 2009, Leuven, Leuven, Belgium Belgium
Temperature as as a First-Class a Citizen Citizen in Chip in Chip Design Design
Pixel-by-Pixel Calibration of a CCD Sachin Camera Sachin S. Sapatnekar Based S. Sapatnekar Thermoreflectance Thermography
System with Nanometer Resolution............................................................................................................ University University of Minnesota, of Minnesota,
130
USA
Mihai G. Burzo, Pavel L. Komarov, Peter E. Raad USA
Practical Study of Temperature Distribution in a Thermal Test Integrated Circuit.... 136
M. Janicki, M. Szermer, S. Klab, Z. Kulesza, A. Napieralski
Abstract- Abstract-
CMOS Temperature With new With technology new technology
Sensors trends, trends,
Based arising arising
on through through
Thermal a a
Diffusion................................................................. 140
confluence confluence
Caspar
of
van
factors of factors
Vroonhoven,
such as such as Moore's law scaling and 3D
integration, the role of thermal Mahdi
Moore's
Kashmiri,
law scaling
design is inexorably Kofi Makinwa
and 3D
integration, the role of thermal design is inexorably shifting shifting from from
package-centric package-centric issues issues towards towards on-chip on-chip optimizations. optimizations. This talk This talk
overviews High-Level overviews the roots the Thermal of roots this of change, this Profiling change, the circuit the circuit effects of Mobile effects of elevated of Applications...................................................................... elevated
144
temperatures, Marius temperatures, Marcu and on-chip and on-chip optimizations optimizations for effective for effective thermal thermal
management. management.
Session 2.3 Advanced cooling techniques I
Text unavailable Text unavailable at the time at the of time printing. of printing.
Hotspot-adapted Cold Plates to Maximize System Efficiency...................................................... 150
Thomas Brunschwiler, Hugo Rothuizen, Stephan Paredes, and B. Michel, Evan Colgan, Pepe Bezama
Optimal Channel Width Distribution of Single-Phase Microchannel Heat Sinks.............. 157
T. Van Oevelen, F. Rogiers, M. Baelmans
Heat transfer enhancement due to pulsating flow in a microchannel heat sink........... 163
T. Persoons, T. Saenen, R. Donose, M. Baelmans
Hot Spot Targeting with a Liquid Impinging Jet Array Waterblock........................................... 168
D. Nikolić, M. Hutchison, P.T. Sapin, A.J. Robinson
Session 2.4 Advanced cooling techniques II
Towards a Dynamic System Model for a Two-Phase Cooling Loop Using Microchannels....174
T. Saenen, T. Delesie, T. Persoons, M. Baelmans
Heat transfer and film thickness measurements in a closed loop spray cooling
system with R134a.................................................................................................................................................... 180
Eduardo Martínez-Galván, Juan Carlos Ramos, Raúl Antón, Björn Palm
Thermal Management of a 3D Chip Stack using a Liquid Interface to a Synthetic
Jet Cooled Spreader.............................................................................................................................................. 186
Krishna Kota, Pablo Hidalgo, Yogendra Joshi, Ari Glezer
©EDA ©EDA Publishing/THERMINIC Publishing/THERMINIC 2009 2009 IX 1 1
ISBN: ISBN: 978-2-35500-010-2
978-2-35500-010-2

7-9 October 7-9 October 2009, 2009, Leuven, Leuven, Belgium Belgium
Temperature as as a First-Class a Citizen Citizen in Chip in Chip Design Design
Friday 9 October 2009
Sachin Sachin S. Sapatnekar S. Sapatnekar
Session 3.1 Special session: Nanopack I University University of Minnesota, of Minnesota,
USA USA
Presentation and status of the NANOPACK project.............................................................................. 192
A. Ziaei, S. Demoustier
Electro-Thermal Modeling of Nano-Scale Devices............................................................................ 195
D. Abstract- Vasileska, Abstract- With K. Raleva, new With technology new S. M. technology Goodnick trends, trends, arising arising through through a a
confluence confluence of factors of factors such as such Moore's as Moore's law scaling law scaling and 3D and 3D
integration, Effects integration, of the role Quantum the of role thermal of thermal Corrections design design is inexorably is inexorably and shifting Isotope shifting from Scattering from on Silicon Thermal
package-centric package-centric issues towards on-chip optimizations. This talk
Properties.................................................................................................................................................................... issues towards on-chip optimizations. This talk
197
overviews overviews the roots of this change, the circuit effects of elevated
Javier temperatures, V. Goicochea,
the roots of
and Marcela
this change,
on-chip Madrid,
the circuit
optimizations Cristina
effects
for Amon
of elevated
temperatures, and on-chip optimizations for effective effective thermal thermal
management. management.
Directional Thermal Conductivity of a Thin Si Suspended Membrane with Stretched
Ge Quantum Dots..................................................................................................................................................... 203
Jean-Numa Text Gillet, unavailable Bahram at Djafari-Rouhani, the time of printing. Yan Pennec
Text unavailable at the time of printing.
Invited speaker: Vladimir Székely BUTE, Hungary
Thermal Transient Measurements: the State of the Art................................................................. 209
Vladimir Székely
Session 3.2 Special session: Nanopack II (Thermal interface materials)
Characterization of Metal Micro-Textured Thermal Interface Materials........................ 210
Roger Kempers, Anthony Robinson, Alan Lyons
Carbon Nanotube Enhanced Thermally Conductive Phase Change Material
For Heat Dissipation............................................................................................................................................... 216
Xinhe Tang, Ernst Hammel, Werner Reiter
Method for In-Situ Reliability Testing of TIM Samples..................................................................... 219
Andras Vass-Varnai, Zoltan Sarkany, Marta Rencz
Progress in Thermal Characterisation Methods and Thermal Interface Technology
within the “Nanopack” Project..........................................................................................................................224
B. Wunderle, M. Abo Ras, M. Klein, R. Mrossko, G. Engelmann, D. May, O. Wittler, R. Schacht, L. Dietrich,
H. Oppermann, B. Michel
Autor Index....................................................................................................................................................................... 233
©EDA ©EDA Publishing/THERMINIC Publishing/THERMINIC 2009 2009 1X 1
ISBN: ISBN: 978-2-35500-010-2
978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Temperature as a First-Class Citizen in Chip Design
Sachin S. Sapatnekar
University of Minnesota,
USA
Abstract- With new technology trends, arising through a
confluence of factors such as Moore's law scaling and 3D
integration, the role of thermal design is inexorably shifting from
package-centric issues towards on-chip optimizations. This talk
overviews the roots of this change, the circuit effects of elevated
temperatures, and on-chip optimizations for effective thermal
management.
Text unavailable at the time of printing.
©EDA Publishing/THERMINIC 2009 1
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Toward a Rational Modeling of Convection
M. N. Sabry
French University in Egypt, Shourouk, EGYPT
Present address: Mansoura University, Mansoura, EGYPT,
Abstract - The thermal design of huge systems, huge in terms of
number of components not their size, enforces the usage of
dedicated SW packages in which each component needs to be
modeled adequately. Detailed 3D modeling is not possible at early
design phases. An adequate compact thermal model (i.e. one with
very few degrees of freedom) of each component should be used
instead. It must be cast in a form that makes it usable in SW
packages, to model the behavior of each component regardless of
surrounding objects. This fact has long been recognized for
thermal conduction problems, which was solved using the socalled
Boundary Condition Independent (BCI) models. For
convection, the model universally admitted is that of the Heat
Transfer Coefficient (HTC), which is obviously not BCI. It can
always be used for small systems using a spread sheet that will
have to be manually readapted for each new system topology. For
large systems, automated BCI model generation is mandatory,
which is the objective of this work. In this work, a new approach
is proposed that generalizes achievements in building BCI
compact models for thermal conduction to thermal convection. It
offers many advantages over classical HTC models, including in
particular its ability to handle conjugate heat transfer problems in
a much more accurate, although a bit more involved, way. The
level of complexity remains orders of magnitude less than full 3D
analysis, which makes the proposed approach adapted for
preliminary design phases.
I. INTRODUCTION
Heat Transfer Coefficient (HTC) by convection has been used
since more than a century with success by engineers worldwide
to address practical problems and get rapidly an estimate
allowing them to take adequate engineering decisions. The
alternative would have been either to do costly experiments or
time consuming detailed calculations which are either
unavailable or undesirable at early design phases. They can be
unavailable if for instance the supplier does not wish to reveal
details under intellectual property rights. They are undesirable
because of the large amount of data and CPU time that have to
be supplied, while design main features are not yet set. The
success of HTC modeling approach is in part due to the
backing of a rigorous similarity theorem extending the validity
of a relatively small set of experimental results to a
significantly wider range of applications.
When designing systems containing a huge number of
components, dedicated SW packages should be used. This will
require a model describing overall component behavior in a
simple way, i.e. with very few degrees of freedom, which will
be called here a compact model. A mandatory property of such
models is to describe component physical behavior, i.e. its
intrinsic flux-potential relation, regardless of neighboring
objects nature. This property has long been recognized for
thermal conduction, under the name of Boundary Conditions
Independence (BCI). Models not satisfying this condition are
useless in large system simulation unless we provide a whole
set of models, one for each possible combination, which is
obviously not adequate. In hand, or spread sheet assisted,
calculations of rather small systems, thermal engineers have
sufficient experience to build adequate models for each
topology. These models will have to be revised for different
topologies (see below) which is obviously not adequate for
automated calculations of large systems.
In the next section it will be shown why the concept of HTC
fails to satisfy the BCI condition and what are the
consequences. In fact, the apparent simplicity of HTC is both
one of the main reasons of its success as well as its
weaknesses. Discrepancies of the order of a factor of 4 or more
were reported between different experimental results by
different research teams for the same geometry and under
seemingly the same conditions. Discrepancies are so frequent
and so important that they cannot be simply explained by noncareful
experimental measurements of all teams other than my
own team! What if there was a fundamental reason behind
them What if the concept of HTC was too simplistic to be an
adequate model even for rough calculations of a precision of
say 50-100%
In this work, a suggested generalization of the BCI approach
used earlier for thermal conduction to thermal convection
problems will also be presented, starting from basic principles
through a careful analysis of assumptions needed to reach the
well known equation named ‘Newton’s law of cooling’
(although Newton can claim innocence because he never
postulated it!):
Q = h A (T w – T f ) (1.1)
where Q is the heat transfer rate, T w and T f are respectively
‘representative’ wall and fluid temperatures, A is the area
across which heat flows and finally h is our HTC.
II. GENERAL FEATURES IMPLIED BY PHYSICS
The starting point would be the governing partial differential
equations. Only forced convection with uniform physical
properties will be considered in order to keep the problem
linear. Since the objective is fundamental, to understand why a
given modeling approach is better than the other, and since
convection is a sufficiently complicated physical phenomenon,
©EDA Publishing/THERMINIC 2009 2
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7-9 October 2009, Leuven, Belgium
the inclusion of nonlinear effects would be inappropriate at that
level. In a domain , bounded by the closed surface , the
following equation holds at steady state:
with node i[1, N] is denoted i . Its extent, which can be an
area or a volume, will be denoted S i .
The following modified Green’s function G has been proposed
2
c v T
T q v
(2.1)
earlier which satisfies:
where v is a given velocity vector field, c and are
respectively fluid density, heat capacity and thermal
conductivity. Finally q v is the rate of volumetric heat
generation. In case we transform this equation into a
dimensionless one, we get, keeping the same symbols for
dimensionless v T and q v as their dimensional counterparts:
2
Pe v T
T q v
(2.2)
where Pe is the Peclet number Pe = v D/ (where v is a
characteristic fluid velocity, D a characteristic length and
thermal diffusivity).
Let us analyze implications of (2.2) in its own on the sought for
compact model. Boundary conditions will be postponed to a
subsequent step in order to concentrate on what is general,
embodied by (2.2) as compared to what is problem dependent,
which is specified by the particular set of boundary conditions.
First of all, linearity of (2.2) implies linearity of the sought for
compact model. The HTC model (1.1) is linear, but it is only a
very particular form of a linear relation between the flux (Q)
and the potential difference (T). There are many other linear
forms like the matrix form or the integro-differential form:
qi
j
hij
T
j Tref
(2.3)
T
a Q d
bQ dx
cQdx
(2.4)
In (2.3), q i and T j refer respectively to the heat flux density and
the temperature at different points, while T ref is any suitable
reference temperature. In (2.4), x is a relevant space coordinate,
while a, b, and c can be either constants or space dependent
functions. Any of these forms are linear. We still have to
choose a form that respects problem physics while keeping the
level of complexity relatively low, to let the compact model be
practical. Note that the operator acting on the unknown T
contains an odd order derivative (the LHS) which means it is
NOT a self similar operator. Hence, the temperature field
cannot manifest the same dependence on upstream and
downstream conditions (w.r.t. to the direction of v). It is wellknown
that the higher is Pe the less would downstream
conditions be able to affect heat transfer. For vanishingly small
Pe, we recover the conduction case where both upstream and
downstream conditions have the same effect on heat transfer.
III. DERIVING THE MOST GENERAL FORM
The shape of the general linear relation between flux and
potential will be derived here without specifying boundary
conditions in order to obtain a general BCI model. Boundary
conditions will be introduced later in the analysis. Let us define
a node as being a surface or a volume across which heat flows
into or out from the system. The sub-domain of , associated
Pe v G
2
r,
r'
Gr,
r'
r
r'
in (3.1)
together with the following set of boundary conditions on the
auxiliary function G (not T) on :
1
S1
r 1
n G
Pen
vG
0 r 1
(3.2)
where 1 is the sub-domain associated with node 1, which will
be called henceforth the reference node, while S 1 is its extent.
The function G can be analytically obtained only in very
simple cases. But this is not an obstacle, as it may also be
obtained numerically in all cases. In fact, what matters is that it
exists! Multiplying (2.2) by G and (3.1) by T, subtracting and
integrating over the whole problem domain with respect to r
we get after some algebra:
T
r'
Tref
Gr,
r'
q
v rdr
Gr,
r'
q
s r
in which q s
T ref Tdr A
1 is the reference temperature.
1
dr
(3.3)
n T
is the dimensionless heat flux density and
Equation (3.3) can be simplified further by recognizing that
surface heat flux density q s or volume internal heat generation
q v are only nonzero over domain nodes, hence will both be
denoted by the unified symbol q i for any node i. Let us denote
by r i values of r i . Equation (3.3) becomes:
N
ri
Tref
j
Gr
ri
T T
1
, q dr
i
j
j
i[1, N] (3.4)
This equation relates node temperatures T i = T(r i ) – T ref with
node heat power densities q i (per unit area q s or per unit volume
q v , whichever is relevant) on all problem nodes. It incorporates
the intrinsic object behavior based on governing partial
differential equation (2.2) but NOT externally applied
boundary conditions on T i or q i , which were not specified to
obtain it. It holds for any set of boundary conditions Dirichlet,
Neumann or Robin. It contains thus all problem physics. There
can be other techniques to express the general solution of (2.2)
(‘general’ in the sense of ‘regardless of the particular set of
boundary conditions’) without passing explicitly or implicitly
by the Green’s function. However, since the solution is unique,
other approaches should yield an expression perfectly
equivalent to (3.4). As no ‘physical’ simplifying assumption
has yet been introduced (apart from that of forced convection
with uniform physical properties) (3.4) is the most general
form of the steady functional relation between heat power q i
(by unit volume q v or by unit area q s ) and T i . The only
approximation needed is that of obtaining G, which can readily
be done either numerically or experimentally.
In case we had only two nodes (for instance wall and fluid at
infinity) one of them can be the reference, the other will be the
space dependent difference T (r). If in addition we had a
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7-9 October 2009, Leuven, Belgium
uniform heat flux q i (r) = q, the heat flux density can be taken
M
1 u u
T ri
Tref
u0
Ti
i ri
out of the integral in (3.4). The integral of the known modified
(4.1)
Green’s function G will give a known space function that will
M
be expressed as 1/H(r):
1 u u
q ri
u0
q i i ri
(4.2)
q = H (r) T (r) (3.5) where M is the number of modes retained (this number need
This looks like the Newton’s law of cooling (1.1), but now we not be the same on all nodes, but we will assume it constant for
know the assumptions. Only 2 nodes and uniform heat flux. In
u
simplicity), i is the element of order u of the known function
the other extreme of an imposed uniform temperature
u
difference T, with still only 2 nodes, equation (3.4) becomes a series (Fourier, Legendre …) for the node i and finally T i and
Helmholtz integral equation of the first kind in q i (r). It does not u
qi
are expansion coefficients. Hence, temperature and heat
matter at all how we can solve it at this level (we can always do
flux density fields are replaced by two vectors of size NxM
that numerically at least), all what matters that is solvable and
each (M series elements on each of the N nodes). Let us denote
will give an expression of the form:
these vectors by T and q. Substituting (4.1) and (4.2) in (3.4),
q (r) = H' (r) T (3.6)
Evidently, H and H' are not the same. Both were obtained via
an assumption that depends on the wall thermal conductivity
(respectively much lower or much higher than that of the
fluid). This assumption depends on the nature of surrounding
objects (the wall), which makes the HTC model boundary
conditions dependent, an undesirable property as explained
above. It would also work only for 2-node objects which is too
restrictive.
What have we gained by passing through the most general
form (3.4) before getting the ‘over’ simplified expression (3.5)
or (3.6) Mainly, that we can now make a less crude
assumption transforming (3.4) into a slightly more complicated
form than (1.1) but significantly closer to reality. This will be
done in the next section, but before doing so, let us comment
on the following property of (3.4). Temperatures T i at any point
in each node depend on q at all points in all nodes. In other
physical words, the local value of the thermal boundary layer,
hence the local thermal ressistance depends on all the past
history of heat transfer in the upstream section. Likewise, from
the Helmholtz integral equation, q at any point depends on T at
all points. In (3.4) profile information of both T i and q i are
captured, but not in (3.5, 6). They DO influence each other as
shows (3.4).
IV. PRACTICAL SIMPLE FORMS
In practice, people will not use sophisticated Green's notion to
obtain "engineering" models. However, a direct analog of the
Green's function is the Matrix, to which the Green's function
can be reduced to in any numerical approximation. But before
we sketch a method to construct this matrix, we have to find a
simple way to express profile information on each node. There
are usually two approaches. The first is the so called nodal
approach, in which both temperature and heat power density
are approximated by an interpolation function using
temperature values at many points inside the node. The second
approach is the ‘modal’ approach, in which the temperature, as
well as heat power density, along each node are approximated
by a series expansion over a given well-known functional
series, preferably orthogonal (Fourier, Legendre, …). The
second approach will be selected, giving:
multiplying by
T
R
u
i and integrating over each node gives:
q
where matrix R contains the elements
R
uv
u v
ij
G r
i j
j , ri
i j dr
j dri
(4.3)
uv
R ij , which are given by:
(4.4)
Elements of R are of dimension 1/HTC. In case R was
diagonal, we get the Newton’s law of cooling. It can only be
true if heat transferred at a point depends on the local
temperature difference, regardless of upstream or downstream
conditions. This is in flagrant contradiction with boundary
layer theory as will be developed in next section. This
approach represents a generalization of the "adiabatic heat
transfer coefficient" suggested earlier [3] as well as the flexible
profile approach also suggested earlier [7] for conduction.
Available HTC data can be reused to get at least few of the
elements in the sought for R matrix or its inverse the H matrix.
In fact, the order zero element in any functional series is
0
0 0
usually the uniform one: i const.
. Hence, T i and q i are
respectively the uniform parts of temperature and heat power
densities. This means that in case we had a uniform
temperature profile Ti u 0 for u 0.
(or a uniform heat flux
profile q u i 0 for u 0.
), then it is expected to find the well
known uniform T (or uniform Q) HTC in R (or its inverse H).
V. WHY IS HTC INADEQUATE
a. HTC cannot model multiple heat sources
Let us first introduce the concept of a “node”. It is defined as a
region in space (a surface or a volume) which participates in
heat transfer, by receiving a certain heat power Q [in W] that
depends on its own temperature T as well as that of other
neighboring nodes. Of course the region may have a
distribution of temperatures (also called a profile); but this
issues will be postponed to the next subsection. In case we
only have two nodes, labeled 1 and 2, then we may write the
so called Newton’s law of cooling:
Q 1 = h 1 S 1 (T 2 – T 1 ) (5.1)
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(where Q i is heat power entering node i), together with the
first law:
Q 1 + Q 2 = 0 (5.2)
Where S i is the ‘extent’ of the node i (its area or volume) and
h i is the HTC based on the ‘extent’ S i . Using (5.1) and (2) it is
evident that:
Q 2 = h 2 S 2 (T 1 – T 2 ); h 1 S 1 = h 2 S 2 = H (5.3)
Both h 1 and h 2 derive from the same quantity H, which are
simply expressed with different reference extents. We will call
H the ‘extensive’ HTC.
The heat transfer coefficient HTC is a scalar quantity that can
only relate 2 values:
- One and only one heat power Q (in W), flowing from
node 1 to node 2
- One and only one temperature difference T
between the two nodes.
In reality, there are many industrial applications where
multiple heat sources and sinks exist and interact, for instance
air flow over a PCB with many chips each dissipating a variable
amount of heat, or a room with many windows and
appliances, etc.
This has been pointed out long time ago through the concept
of adiabatic heat transfer coefficient [3].
Assuming we have N nodes, then the only way we can
describe a linear relation between Q i and T i (i [1, N]) is a
matrix of values H ij :
Q i = j H ij T j (5.4)
In the special case of heat transfer between two nodes only this
reduces to:
Q
Q
1
2
H
H
H T
H T
1
2
(5.5)
which is simply another way to write equations (5.1) and (5.2).
But using the matrix notation gives us a framework to extend
the classical HTC for the case of multiple heat sources. Note
that the sum of all elements in any column as well as the sum
of all elements in a column should both be zero by virtue of
the first law and second laws respectively [5]. Hence, in a 2x2
matrix, we only have one independent parameter H, which
means we could have simply used (1). But in a system with N
heat sources we have to use matrix notation, having the order
N – 1 at most.
B. HTC cannot incorporate distributive or profile
information
In standard heat transfer textbooks, one may find many widely
accepted correlations for HTC for different configurations.
7-9 October 2009, Leuven, Belgium
Even if we confine ourselves to a given standard 2-node case,
for instance forced convection in a straight circular tube, than
we still do not have only one correlation, but many! We have
the uniform heat flux and uniform temperature cases to begin
with. Both are unrealistic cases, because walls across which
heat is transferred do have a finite thermal resistance. Actual
distribution (i.e. profile) of either heat or temperature at the
solid liquid interface would depend on the ratio of solid to
liquid thermal conductivities as well as wall thickness to tube
diameter, etc. In fact, all real cases are conjugate heat transfer
problems. Building mega correlations incorporating both fluid
and solid walls properties would lead to a complexity that is
practically impossible to handle. For instance, what if the walls
were made of two or more layers
The only practical solution is to build a convenient model for
each domain alone (one for the fluid, one for each solid layer
…) that depends on domain intrinsic behavior and NOT on
externally applied boundary conditions: The so-called
Boundary Condition Independent (BCI) model [6]. It has long
been recognized for conduction problems that models failing
to meet the BCI condition are of quite limited utility, since
would have to rebuild a new model for each new usage case.
It remains to generalize this observation for convection. The
attribute ‘uniform Q’ or ‘uniform T ’ that we have to specify
for any HTC correlation means that HTC definitely fails to
meet the BCI condition.
One may argue that profile dependence is not very important:
For laminar flow in circular ducts, Nu goes from 3.66 for
uniform T to 4.36 for uniform Q. The counter arguments are,
first, there is no formal proof that the difference remains
limited in all possible geometric configurations. Second, there
is at least one case where profile dependence is known to be
high, which is dependence on inlet temperature profile. The
latter case is also called the ‘developing profile’.
We do have a whole set of correlations for the above
mentioned case. They predict development lengths (also
called entrance length L e ) assuming that inlet temperature
profile is flat. The HTC in the development zone can be quite
different than that of the fully developed zone. The point is
the following:
Can we rely on existing L e correlations to predict behavior in
short tubes
The answer is unfortunately no!
In fact, the actual development zone extent can vary a lot
depending on the actual inlet T profile, which is certainly not
the one used to obtain the correlation! It can go from zero, if
the inlet profile was the same as that of the fully developed
zone, to much more than the ‘standard’ L e (based on flat
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7-9 October 2009, Leuven, Belgium
profile), if the inlet profile was reversed w.r.t. to the
developed zone profile.
Q w = m c (T out – T in )
Q w = H (T w – T b )
(5.8)
(5.9)
There can be different tracks to incorporate profile
dependence in H in order to let it be BCI (see section 3). One
of them is the flexible profile approach [7]. But in all cases, this
self-contained H that would be capable of adjusting itself to
meet each usage case cannot be composed of a single
number, but rather a whole set of numbers, which can be
arranged in a matrix that encompasses matrix H ij mentioned
Where Q w is the heat power added at the wall, m is the mass
flow rate while T out , T in , T w and T b are respectively outlet,
inlet, wall and bulk temperatures. How many temperatures,
and hence how many nodes do we need to consider The
minimum is 3 because bulk temperature can be considered as
a weighted average of inlet and outlet temperatures:
earlier.
T b = T out + (1 – ) T in (5.10)
B. HTC is symmetric, while convection is not
Convection is by nature a non symmetric phenomenon
because upstream and downstream conditions have different
effects on heat transfer. This can be seen from the governing
energy equation, which reads for steady flow with uniform
physical properties:
2
c v T
T
(5.6)
where v is a given velocity vector field (we only consider
forced convection), c and are respectively fluid density,
heat capacity and thermal conductivity. Finally q v is the rate of
volumetric heat generation. In case we transform this
equation into a dimensionless one, we get, keeping the same
symbols for dimensionless v T and q v as their dimensional
counterparts:
2
q v
q v
Pe v T
T
(5.7)
where Pe is the Peclet number Pe = v D/ (where v is a
characteristic fluid velocity, D a characteristic length and
thermal diffusivity). The operator acting on the unknown T
contains an odd order derivative (the LHS) which means it is
NOT a self similar operator. Hence, the temperature field
cannot manifest the same dependence on upstream and
downstream conditions (w.r.t. to the direction of v). It is wellknown
that the higher is Pe the less would downstream
conditions be able to affect heat transfer. For vanishingly
small Pe, we recover the conduction case where both
upstream and downstream conditions have the same effect on
heat transfer.
Modeling this non symmetric phenomenon with H is
inadequate because H is the inverse of a resistance, which is a
perfectly symmetric element. Let us look at the implications
by considering the simplest ever problem of a straight circular
duct heated at its walls according to any known profile. The
complete model should involve a conservation equation (the
first law) and a constitutive equation (the one involving HTC)
like for instance:
where, for simplicity, is considered as a known coefficient
(0, 1). If we wish to confine ourselves to resistive networks
(as suggests the usage of H), then we can have up to 3
resistors relating the three nodes: R w_in , R w_out and R in_out .
Values of these resistors are:
R in_out = 1 / (m c)
R w_out = 1 / ( H)
R w_in = 1 / ((1 – H)
(5.11.a)
(5.11.b)
(5.11.c)
Now, if heat is added at the walls, then T out > T in , hence the
model above predicts that heat should flow from outlet to
inlet with an amount that is proportional to the mass flow
rate! This unphysical behavior is due to the choice of a
resistive based model, which does not comply with the
problem nature. In case we use the matrix representation,
then this matrix should be non-symmetric. More will be given
on the form of this proposed matrix in section 3. Please note
that this matrix should contain, among other parameters, the
parameter Pe, in a form that transforms the matrix into
symmetric if Pe was vanishingly small (i.e. a pure conductive,
hence a pure resistive, i.e. a perfectly symmetric case).
C. HTC cannot model transient effects
The HTC largely depends on the boundary layer thickness,
which for transient problems is time dependent. A sudden
heating of the walls, of an otherwise isothermal flow, creates
a time dependent thermal boundary layer of initial thickness 0
all over the duct. The HTC is thus virtually infinite at start of
heating. It will gradually damp to the steady state values with
a time constant that depends mainly on fluid (and wall!)
thermal capacity.
Some researchers have proposed to use the quasi-static
approximation, i.e. an instantaneous H(t) based on available
steady state correlations in which we would insert
©EDA Publishing/THERMINIC 2009 6
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instantaneous temperature T(t). The author does not believe
this is a track to follow [8]. In fact temperature effects on the
values of HTC in any correlation are exerted only through
physical properties. In case fluid properties were temperature
independent, the HTC would be time independent and hence
would not capture the time constant needed to build the
thermal boundary layer. Besides, any solution that does not
incorporate the boundary layer thermal capacitance is vowed
to failure in correctly modeling transient heat transfer.
We have to model transient heat transfer by convection using
a mathematical model that can be for instance of the
following form:
Q = H (T) + C th d(T)/dt (5.12)
where C th is a new coefficient, acting like a thermal
capacitance, taking and c into consideration (H considers
only thermal conductivity ).
Of course we will still have to upgrade the coefficient C th the
same way we need to upgrade H, i.e. include profile sensitivity
and multiple heat sources transforming it thus to a matrix.
Let me suggest a new dimensionless number, the analog of
Nusselt number Nu, for C th :
C th /( c D) (5.13)
This new dimensionless number needs to be first adopted, and
then extensive experiments (physical or numerical) must be
performed to characterize it.
VI.
Conclusion
The heat transfer coefficient HTC can be quite misleading in
case it is used for a case that is different from the one used to
extract it. Even if the geometry was perfectly the same as that
used for extracting HTC, results may still be quite different
depending on wall and inlet profiles. This may explain why
published correlations for the same geometry may show large
discrepancies. For the same reason, using HTC in a conjugate
problem may give results that are quite different from reality.
The HTC only relates heat transfer between two bodies.
Because it is a single scalar number, there is no way it can
model multi-body problems with variable heat load on each
body.
HTC is a static parameter that can by no means model
transient effects, without adding more parameters.
Last but not least, due to its symmetric character, which
contradicts the asymmetric nature of convection, it cannot be
used in standard system simulators. Conferring it to hand
calculations is a serious disadvantage.
All these problems seem to be solvable in case we replace the
single HTC scalar number by a matrix of numbers relating
7-9 October 2009, Leuven, Belgium
many “temperatures” with many “heat powers”. In case
transient effects were to be considered, a second matrix
should be added relating time rate of change of temperatures
with heat powers.
Which “temperatures” and which “heat powers” are we
willing to correlate The simplest answer would be “average
values”. In this case the matrix degenerates into a scalar
number, which is our good old HTC. But this description is too
simplistic to model many real life problems as shown in this
paper. There are at least two different approaches to define
the required set of temperatures and heat powers, the socalled
“nodal” and “modal” approaches. The latter seems to
be preferable, but the community may find other more
suitable approaches. The approach to follow should be
accepted by the community in order to standardize exchange
of heat transfer data. The community is invited to commonly
prepare a white paper on modeling convection [4].
REFERENCES
[1] C. Lasance, “Sense and nonsense of heat transfer correlations
applied to electronics cooling”, Proceedings of the 6th International
Conference on Thermal, Mechanical and Multi-Physics Simulation and
Experiments in Micro-Electronics and Micro-Systems, 2005. EuroSimE 2005,
pp 8-16
[2] R. Moffat, “Do’s and Don’ts in Thermal Management”, 2 nd
International Conference on Thermal Issues in Emerging Technologies, Theory
and Applications, ThETA2/144, Cairo, December 2008, pp.125 – 132.
[3] R.J. Moffat, & A.M. Anderson, Applying Heat Transfer
Coefficient Data to Electronics Cooling, Journal of Heat Transfer, Vol. 112,
pp. 882-890, 1990.
[4] http://www.thetaconf.org/Theta08/blog.htm
[5] M. N. Sabry, Compact Thermal Models for Electronic Systems, IEEE –
CPT, Part A, Vol. 26, pp. 179-185, 2002.
[6] C. Lasance; D. Den Hertog and P. Stehouwer, “Creation and
Evaluation of Compact Models for Thermal Characterisation Using Dedicated
Optimisation Software”, 15 th Annual IEEE Semiconductor Thermal
Measurement and Management Symposium, SEMI-THERM, p.1, 1999
[7] M.N. Sabry, High Order Compact Thermal Models,
Transactions of IEEE / Components, Packaging and Manufacturing
Technology, Vol. 28, No.4, pp 623-629, 2005
[8] Compact Thermal Models For Internal Convection; Sabry, M.-N.;
2005; Transactions of IEEE / Components, Packagging and Mnufacturing
Technology, Vol. 28, No.4, pp 623-629
©EDA Publishing/THERMINIC 2009 7
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7-9 October 2009, Leuven, Belgium
Equivalent Electrothermal Circuit Model for
Vertical-Cavity Surface-Emitting Lasers on Silicon
Optical Bench
C. C. Chen 1 , C. Singh 1 , Y. C. Chen 1 , Hsu-Liang Hsiao 2 , Chia-Yu Lee 2 , Y. T. Cheng 1 , and Mount-Learn Wu 2
1 National Chiao Tung University, Dept. of Electronics Engineering, Hsinchu 300, Taiwan, R.O.C.,
2 National Central University, Institute of Optical Sciences, Jhongli 32001, Taiwan, R.O.C.
Abstract-This paper physically and conceptually provides a
general electrothermal network π-model. Basing on the
proposed network π-model, an equivalent electrothermal circuit
model (ETCM) and the associated thermal behavior analysis are
also demonstrated for the SiOB with VCSELs in terms of
characteristics of device materials and geometries. The
introduced complicated structure of VCSELs constructed in
simulators can be greatly simplified by using the equivalent
ETCM to predict the probable thermal flow paths, and
eventually can achieve the goal of CPU time-saving without
having complex mesh studying or scaling. In the case,
comparison results between measured data, simulation and the
equivalent ETCM calculation show an excellent temperature
matching within ±2°C as well as achieving 90% CPU
time-saving.
Keywords: equivalent electrothermal circuit model, general
electrothermal network π-model, SiOB, VCSELs.
this paper, by analog with a common π-circuit model, we
physically and conceptually introduced a general
electrothermal network π-model, shown in Fig. 1. Meanwhile,
an equivalent ETCM established according to the network
π-model is also presented for the thermal behavior analysis of
silicon optical bench (SiOB) with vertical-cavity
surface-emitting lasers (VCSELs) as shown in Fig. 2 for
160Gbp/s high speed interconnected optical data
communication application.
Since late 1980’s, it has been proposed to utilize silicon
substrate as a cost effective functional carrier to integrate
optical and microelectronic components. The implementation
I. INTRODUCTION
Inevitable non-uniform thermal effect due to increasing
power dissipation within intensive operating chips has been
one of significant hindrances for the developments of next
generation high performance microsystem [1-3], that would
promote the design consideration of associated configurations
and arrangements of device packaging and cooling system,
and limitation of maximum power in IC design stage [2].
Therefore, there has been a drastic proliferation of strategy
and technique concerned with the predictions of thermal
effect on microsystem performance and reliability in terms of
circuit design. So far, the establishment of equivalent
electrothermal circuit model (ETCM) is the most efficient
thermal analysis scheme which can be easily incorporated
with CAD tool for optimal system-IC designs to avoid
unexpected functionality degradation or even device failure
due to excess thermal accumulation. In comparison with
other analysis methods for the predictions of non-uniform
thermal effect, such as numerical solutions based on
Laplace’s equation [2], finite-element analysis (FEA), or
boundary element method (BEM) for simulators [5-7],…etc.,
ETCM can effectively avoid the issues of data unwieldiness
and time-consuming due to complicated boundary conditions
resulted by system configuration. Nevertheless, the proposed
ETCM analysis is still case-dependent which requires detail
system configurable for model development. Therefore, in
Fig. 1. Scheme of the general electrothermal network π-model. By
analysis with the common π-circuit model, there are three main blocks,
heating source, propagated resistance, and common base resistance, are
adopted to present the thermal source, thermal flow path, and the common
base, respectively.
SiOB
4700µm
Contact Pad
Ground
BCB
Thermal Via
625µm
VCSELs
Fig. 2. Scheme of the Vertical-Cavity Surface-Emitting Lasers
(VCSELs) on Silicon Optical Bench (SiOB). It is obviously that there
should be complicated thermal behavior inside the SiOB due to its large
volume and aspect ratio. The insertion of upper-right corner shows
complicated structure of the VCSELs, the adjacent contact pads, and the
thermal via in detail.
©EDA Publishing/THERMINIC 2009 8
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7-9 October 2009, Leuven, Belgium
of the silicon bench can greatly reduce package size and
interconnection length within components, which result in
reduction of parasitic capacitance and inductance in the
package suitable for high-speed applications. Meanwhile, the
SiOB provides exclusive advantages of high precisely optical
alignment for low insertion loss coupling from optical
components to fiber core, good thermal mismatch, excellent
thermal conductivity, and better resistor fabrication for
impedance matching of signal transmission. On the other
hand, SiOB still has its intrinsic shortcoming. Silicon
substrate is lossy material in the RF/microwave/millimeter
wave regimes. Electrical signals transmitted between on-chip
circuitries can easily leak into silicon substrate and be coupled
to generate substrate noise. Electrical losses of the signals
due to induced eddy current in the substrate also degrade the
quality of the performance of passive components in the
driving circuitry. In order to resolve this issue, a layer of 3µm
BCB (benzo-cyclo-butene) is utilized for passive fabrication
where the loss can be greatly reduced. Owing to high thermal
resistance characteristic of BCB, laser diode directly mounted
on the top of it would have inevitable working temperature
raise that could affect the laser performance.
Therefore, in this paper, the equivalent ETCM of SiOB
mounted with 160Gbp/s VCSELs will be developed by
considering the characteristics of device materials and
geometries. The presented model can not only reasonably
simplify the complicated configuration but also provide an
indication for system optimization.
II.
MODEL ANALYSIS
According to the essential meanings and emphases of
common π-circuit model, three main blocks, labeled heating
source, propagated resistance, and common base resistance,
are employed in the general electrothermal network π-model,
shown in Fig. 1, representing the thermal source, thermal flow
path, and the common base of thermal conducting system,
respectively. As mentioned by A. M. Darwish et al. that it is
appropriate to assign adiabatic surface between each heating
source and the next [2], the adopted dash-lines in the network
π-model represent an adiabatic surface enclosed each
presented blocks where the effective contact area can be
eventually well defined. Meanwhile, the impedance
parameters Z i , where i present 1, 2, 3, and 4, can be defined as
the thermal resistance of heating source itself, source-source,
nature or forced air convection, thermal capacitance, and
other specified boundary conditions, and so on. Boundary A
and B can be the ground level of the thermal flows, other
heating components of thermal conducting system with
specified thermal conditions, or interconnections between
different systems. It should be specially emphasized that
icons of the source of thermal flow and the block of heating
source represent the thermal generation and flow and main
heated component, respectively.
Fig. 3(a) and (b) show the modified electrothermal
π-network model and the associated equivalent ETCM of the
VCSELs on SiOB, respectively, where Z 1 and Z 2 , Z 3 , and Z 4
are thermal resistance of a VCSEL (R VCSEL ) itself, an infinite
thermal resistance due to the negligence of nature air
convention here, and thermal capacitance of SiOB (C SiOB ),
respectively. Boundary A and B are the adjacent R VCSEL of the
operating VCSEL and ground level for entire thermal
conducting system, respectively. It is noted that two
parameters, the source of thermal flow and Z 1 , are the
components of the heating source in the modified network
π-model since the VCSELs are main thermal flow generators
and also the heated components themselves in our case.
Additionally, the blocks of propagated resistances and
common base resistances are represented by parallel
connection of thermal resistance of gold (R Gold ), air (R Air ), and
BCB (R BCB ) and SiOB (R SiOB ), respectively.
Four switches adopted in the structure mean the VCSEL
can be single operated. According to Fourier’s conduction
law, R VCSEL , R Gold , R Air , and R BCB can be easily calculated as R i
=t i /k i A i , where i, t, k, and A are adopted material, thickness,
thermal conductivity, and contact area of the materials,
respectively. Then, C SiOB is equal to Q/∆T where Q and ∆T
represent dissipated power and temperature difference,
respectively. Parameter R SiOB , however, has complicated
thermal behavior due to its large volume and aspect ratio. It
can be calculated as follows [2]:
[ f ( g[ 2s]
1)
]
1 ⎛ V + ⎞ 1 ⎛ h( 2.
3t)
⎞
R SiOB
= ln⎜
+ ⎜ ⎟
[ ( [ ])] ⎟
ln , (1)
2π Wk ⎝ V f g L ⎠ 4π sk ⎝ h(s) ⎠
where
(a)
(b)
Fig. 3. (a)Scheme of the modified general electrothermal network π-model.
The source of thermal flow and Z 1 are the components of the heating source
due to the VCSELs are main heating generators themselves in our case.
(b)The equivalent electrothermal circuit model of the VCSELs on the SiOB,
where Z 1 and Z 2, Z 3, and Z 4 are thermal resistance of VCSEL (R VCSEL), an
infinite thermal resistance due to without nature air convention here, and
thermal capacitance of SiOB (C SiOB), respectively.
©EDA Publishing/THERMINIC 2009 9
ISBN: 978-2-35500-010-2

x −1
V(x) = , f(y) =
x + 1
y + 1 ⎛W
⎞
, g(z) = ⎜ ⎟ ,
y −1
⎝ z ⎠
2
7-9 October 2009, Leuven, Belgium
and
h(w) =
1+
g(
1+
g(
2w)
+ 1
2w)
−1
The parameters W, k, t, and s are wide, thermal conductivity,
thickness of SiOB, and the spacing between contact pads,
respectively. For the purpose of conveniently and fairly
comparison, Table 1 shows the dimension parameters and
thermal conductivities of each adopted material using in the
model calculation and simulation. After obtaining all of the
thermal resistances and capacitance in the thermal conducting
system, the paths of thermal flow and hottest temperature on
device can, therefore, be uniquely and rapidly determined
based on the equivalent ETCM.
III.
SEMICONDUCTOR FABRICATION
For the completeness and fair comparison between
theoretically and experimentally discussion, the entire
fabrication procedures of SiOB and transmitter assembly,
including the manufacturing of 45°micro-reflectors,
V-groove arrays, high frequency transmission lines that
(a)
connected with 4-channel VCSEL array and bonding pads are
demonstrated and shown in Fig. 4. It should be emphasized
that the 45°micro-reflectors and V-groove arrays did not be
employed in the simulation and model analysis due to they are
not main components of paths of thermal flow and
furthermore for the first structure simplification.
Additionally, since the fiber assembly of proposed modules
used for the optical interconnection is passively aligned, the
V-groove array is designed to assemble the multimode fiber
(MMF) array. The SiOB is monolithically fabricated with a
45° micro-reflector and the V-groove array. In order to etch
the bench that can incorporate the optic fiber with the V-
groove and provide the reflection surface for optical coupling
between fiber and VCSEL, simultaneously. A two-step
anisotropic wet etching is developed using KOH solution.
SiO 2 film is deposited on a (100) silicon substrate and used as
a hard mask for anisotropic wet etching. Dedicated patterns
for etching trenches are formed using photo-lithography and
dry etching on the SiO 2 film to define patterns. The
anisotropic wet etching using KOH solution mixed with IPA
is applied to form the 45° micro-reflector and the V-groove
array. After that, the photolithography is adopted again to
fabricate transmission lines. Ti/Au (500/9500 Å) layers are
deposited on the SiO 2 layer by E-Gun Evaporator.
Table. 1. The dimension parameters and thermal conductivities of each
adopted material
IV.
Thickness Thermal Conductivity
Layer Material
(µm)
(pW/µm-K)
SiOB Silicon 625 1.48 × 10 8
BCB BCB 3 2.90 × 10 5
Thermal via Gold 3 3.18 × 10 8
Contact pad Gold 10 3.18 × 10 8
VCSEL Copper 100 3.98 × 10 8
Ground Gold 10 3.18 × 10 8
(b)
Fig. 4. (a) Fabrication of SiOB and (b) Fabrication of High Frequency 4
Channel ×2.5 GHz Transmission Lines
Transmission lines (TMLs) are then formed using lift-off
process. For flip-chip bonding VCSEL onto the as-fabricated
TMLs, Au-Sn patterns of 1µm are defined by
photolithography and thermal evaporator deposition. Finally,
Once the 4-channel VCSEL array is flip-chip bonded onto the
Au/Sn pads, the SiOB transmission module is fabricated with
a position accuracy of 1µm.
EXPERIMENTAL VALIDATION
Four VCSELs are mounted on a SiOB with thickness of
625 micrometer and covered by air without having artificial
convection. The bottom of the SiOB is an isothermal surface
setting with 75 o C to mimic the operation environment of a
typical optical transceiver system. All other surfaces are
adiabatic where no heat flux is allowed. Meanwhile, the
equivalent ETCM also indicates that the contributions of
thermal resistances of air and SiOB could be safely ignored
©EDA Publishing/THERMINIC 2009 10
ISBN: 978-2-35500-010-2

due to a large thermal resistance in the part of parallel
connection and a small resistance value in the part of serial
connection, respectively. Thus, the materials of air and SiOB
could be reasonably removed both in the model calculation
and the CoventorWare simulation [7] so that more than 80%
reduction of required mesh was achieved as well as the
requirements of CPU and DRAM operation in this case. Fig.
5 (a) shows the probable paths of thermal flow predicted by
the equivalent ETCM after removing the air and SiOB in the
thermal conducting system. Since VCSEL and thermal via
have comparable thermal conductivity (see Table. 1) and the
thickness of the operating VCSEL and the adjacent one can
have two-order magnitude larger than that of thermal via, the
thermal via would become the main path of the thermal flow
as the expectation in this work.
Furthermore, the paths of the thermal flow depicted in Fig.
5 (b) extracted from the simplified thermal conducting system
constructed in the simulation verify the validation of the
equivalent ETCM by showing the possible paths of thermal
flows on the principal components. The simulation results
can not only obviously present the main paths of thermal flow
as the prediction of the equivalent ETCM, but also indicate
the hottest point that in the outermost corner of the operating
VCSEL where the most far from the possible paths of the
thermal flow. It is important to find out the hottest point in a
thermal conducting system due to possible unexpected
functionality degradation or even device failure due to a great
quantity of thermal accumulation will easily happen at the
point. In fact, according to the indications of derived
equivalent ETCM, the value of the hottest point could always
easily happen at the joints of the heating source and source of
thermal flow and the hottest temperature should relate with
the characteristics of material and geometry of Z 1 and
7-9 October 2009, Leuven, Belgium
the conditions of boundary A. For the purpose of furthermore
validation of mentioned characteristics of the hottest point,
Fig. 6 shows the scheme of the simplified thermal conducting
system with single operating VCSEL established by the
equivalent ETCM. The model calculation of the temperatures
of node points A, B, and C depicted in Fig. 6 are 80.2, 79.2,
and 75°C, respectively. The results reveal that the hottest
temperature is at node A and the main path of thermal flow is
from node B to C as the prediction of the equivalent ETCM
and having excellent match with simulation demonstration in
Fig.5 (b). Therefore, it is worthy for system-IC designers and
engineers to analyze the worsen cases at those joints and
study the thermal behaviors of Z 1 and boundary A seriously by
means of the network model or equivalent ETCM.
Fig. 7 shows the IR microscope detected temperature
distribution of SiOB heated by the operated VCSEL. The
bottom of SiOB is constrained with a bias temperature
A
B
Fig. 6. The scheme of the simplified thermal conducting system with single
operating VCSEL established by the equivalent ETCM. The model
calculation of the temperatures of node points A, B, and C are 80.2, 79.2,
and 75°C.
C
(a)
(b)
Hottest point
Fig. 5. (a) The simplified thermal conducting system established by the
indication of the equivalent ETCM. The material of air and SiOB were
removed in the system to reduce the required meshes as well as the CPU
time. (b) The thermal flow on principal components extracted from
CoventorWare simulation provides a verification of the equivalent ETCM.
Hottest point was also labeled in the simulation result and indicated the point
of possible unexpected functionality degradation or even device failure due
to a great quantity of thermal accumulation.
Fig. 7. The measured temperature distribution of SiOB heated by the
operating VCSEL using IR microscope. Only a laser diode is operated by
probe B with 8mA input current and 2V bias voltage.
©EDA Publishing/THERMINIC 2009 11
ISBN: 978-2-35500-010-2

of 75 o C for fair comparison. Only a laser diode is operated by
probe B with 8mA input current and 2V bias voltage. The
measured thermal distributions verified the validation of the
simulation and model prediction shown in Fig. 5 and 6. Fig. 8
shows the comparison between the measurement, equivalent
ETCM, and CoventorWare simulation results with and
without air and SiOB, respectively. Excellent temperature
matching within ±2°C indicates the validation and prediction
of the equivalent ETCM and the practicality of the simplified
structure in which we can have 90% CPU operation time
saving due to 80% mesh number reduction. Besides, the
slight temperature mismatch could be caused by the thermal
impedance mismatch between the interfaces and the phonon
vibration in high temperature.
Fig. 8. Comparison between the presented model, measurement data, and
simulated results with and without air, BCB and SiOB, respectively.
Excellent temperature matching within ±2°C indicates the validation and
prediction of the equivalent ETCM and the practicality of the simplified
structure in which we can have 90% CPU operation time saving due to 80%
mesh number reduction.
7-9 October 2009, Leuven, Belgium
V. CONCLUSION
The paper physically and conceptually presents a general
electrothermal network π-model in system level. A associated
equivalent electrothermal circuit model can be readily used
for device optimization and CAD programming in terms of
the demanding geometrical structure and characteristics of
materials. The equivalent ETCM can also open a way for
structure simplification and system optimization with high
accuracy and achieve the goal of CPU time-saving in FEA
simulation without complex and contrived mesh studying or
scaling. Furthermore, the equivalent ETCM can predict the
hottest point in the system to avoid the device failure or
break-down.
VI.
ACKNOWLEDGMENT
This work was supported by the 97-EC-17-A-07-S1-001
project at Optical Sciences Center, National Central
University.
REFERENCES
[1] F. Tamigi, N. Nenadović, V. d’Alessandro, L. K. Nanver, N. Rinaldi,
and J. W. Slotboom, “Modeling of thermal resistance dependenceon
design parameters in silicon-on-glass bipolar transistors,” in Proc.
IEEE 24th International Conference on Microelectronics, vol. 1,
pp.257-260, Niš, Serbia-Montenegro, May 2004.
[2] A. M. Darwish, A. J. Bayba, and H. A. Hung, “Accurate
determination of thermal resistance of FETs,” IEEE Transactions on
Microwave Theory and Techniques, vol. 53, January 2005.
[3] A. H. Ajami, K. Banerjee, M. Pedram, “Modeling and analysis of
nonuniform substrate temperature effects on global ULSI
interconnects,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol. 24, pp.849-861, June 2005.
[4] B. Goplen and S. Sapatnekar, “Thermal Via Placement in 3D ICs,”
Proceedings of the 2005 international symposium on Physical design,
pp.167-174, April 2005.
[5] K. Vanmeensel, A. Laptev, J. Hennicke, J. Vleugels, and O. V. der
Biest, “Modeling of the temperature distribution during field assisted
sintering,” Acta Materialia, vol. 53, pp.4379-4388, August 2005.
[6] A. J. Kemp, G. J. Valentine, J.-M. Hopkins, J. E. Hastie, S. A. Smith,
S. Calvez, M. D. Dawson, and D. Burns, “Thermal Management in
Vertical-External-Cavity-Surface-Emitting Lasers: Finite-Element
Analysis of a Heatspreader Approach,” IEEE Journal of Quantum
Electronics, vol. 41, pp.148-155, February 2005.
[7] CoventorWare 2008, http://www.coventor.com/, version 2008.
©EDA Publishing/THERMINIC 2009 12
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Geothermal Cooling Solution Research
For Outdoor Cabinet
Yuping Hong, Yuening Li, Jian Shi
Huawei Technologies Co., Ltd.,Shenzhen,P.R.China
Tel: +86-755-89652254
E-mail: hongyp@huawei.com
Abstract- This paper introduces an ongoing research on
geothermal cooling solution (GCS) for outdoor cabinets that are
used to contain telecom equipment such as FTTX network,
mobile network and etc. The principle of GCS is that the heat
generated inside cabinet from telecom facilities is transferred to
water by an air-water heat exchanger, and then water dissipates
the heat to shallow underground soil by water-soil heat
exchanger. A prototype of this GCS is built and tested in
Shenzhen, China. Test result shows that the prototype meets the
cooling requirement with at least 3 times cooling efficiency
higher than that of traditional cooling solution. It is conclude
that GCS is effective and valuable for practical application, and
need further more investigation.
Fig 1 Typical daily temperature curve of the atmosphere air and soil at
difference depth (Shenzhen, China)
Key word: geothermal cooling solution, outdoor cabinet
I. INTRODUCTION
With the fast development of broadband network,
outdoor cabinets which contain telecom equipment like
FTTX network are deployed more widely. Cooling plays an
important role in design of these cabinets to maintain cabinet
internal temperature at proper level; otherwise the equipment
may fail to work. Traditional cooling technologies such as
air-air heat exchanger, air conditioning utilize atmosphere as
heat sink, which are limited for size, energy cost and acoustic
noise. Advanced cooling solution with compact size, high
energy efficiency and low noise, which meets environmental
protection strategies as well, is preferred by the telecom
operators.
As we know, air temperature changes with season and time.
In hot season, it is critical for traditional air cooling
technologies to function due to high temperature of
atmosphere. However soil temperature is more stable, the
temperature impact of the air to the soil becomes weak with
the increase of soil depth. Figure 1 shows that at the depth of
5m, the soil temperature is nearly stable in the whole year.
The temperature curve in figure 1 is calculated with the
theoretic formula from Reference [1]. Figure 2 shows that at
about 0.8m depth, little will change with soil temperature in
one day time, the temperature data is derived from Reference
[2]. Soil temperature is higher than air temperature in winter
and lower in summer. As summer is the worst case for
telecom facilities cooling, soil provides an ideal “heat sink”
for outdoor cabinet. In this paper, geothermal cooling is
defined as cooling with soil.
Fig 2 Typical temperature curve of soil in one sunny day (Shenzhen, China) [1]
Recently, geothermal cooling is attracting a lot of
attentions from telecom operators and equipment
manufacturers. KPN reported research on cooling mobile
shelter with vertical soil heat exchanger (VSHE), the VSHE is
a kind of borehole cooling, and the drilling depth reaches 75m
[3]. Huawei and Telecom Italia reported a joint research on
cooling solution utilizing underground heat pipe. Test result
shows that the cooling efficiency is much higher than that of
traditional cooling solution [4]
This paper introduces an ongoing research about new GCS
for outdoor cabinet. The principle of this GCS is that the heat
generated inside cabinet is transferred to water by an air water
heat exchanger, and water dissipates the heat to shallow
underground soil by water soil heat exchanger. The original
proposal of this GCS is derived from traditional ground
source heat pump (GSHP) technology, which is widely used
in air conditioning system for buildings. The target of this
research is to find a feasible, low cost and high reliable
geothermal cooling solution for easy engineering design and
practical application.
©EDA Publishing/THERMINIC 2009 13
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II.
GCS DESIGN AND FIELD TEST
7-9 October 2009, Leuven, Belgium
The GCS system mainly include following parts: airwater
heat exchanger, water pump, flow meter and watersoil
heat exchanger. The air-water heat exchanger is a
tube-fin structure with fan help to circulate air between heat
exchanger and equipment. It has two advantages compare
with air-air heat exchanger or air conditioning. First, it is
more compact and save space for the cabinet; second, it is
good for noise insulation because the total unit is sealed in the
cabinet, no outside vent is needed which will cause noise
leakage. The water-soil exchanger is made of PE material
tube which is anti-corrosive and high reliable and widely
used in GSHP. The tube will be buried together with other
electric cables used for the telecom equipment in shallow soil,
which is important ways to control the total installation cost.
The Water-soil exchanger has no pollution to environment as
it is a closed loop system. Compared with traditional GSHP,
GCS is much simpler as no compressor unit is applied. And
the shallowly buried water soil tubes are easier to install
compared with borehole. Borehole needs special drilling
machine and takes more time and money.
As the figure 3 shows, GCS have three main coupled heat
transfer process. The first process is that air circulates through
equipment chassis, cabinet and air-water heat exchanger of
the GCS. Heat is transferred to water in the pipeline in this
process. The second process is that water circulates through
pump, flow meter, water-soil heat exchanger and air-water
heat exchanger. Heat is transferred to soil in this process. The
third process is soil dissipates heat to more distant soil and
environmental air. This third process is more complicated
because of transient changing climate and high thermal
inertia property of soil.
The GCS prototype is built and tested in Shenzhen.
Shenzhen locate in south China where annual average
temperature is 23℃, the highest temperature reach 37℃ in
summer and last long time. It may represent severe working
condition in the world, the testing can then be apply to many
area like Europe, north Asia and etc.
Figure 3 show detail the layout of the equipment inside the
cabinet, GCS and the main temperature test point. The GCS is
installed into a real typical outdoor telecom cabinet. The size
of outdoor cabinet is 1550(L) x550(W) x1500(H) mm. GCS is
set up in left side, while telecom equipment chassis is placed
in the middle. The equipment chassis dissipates 750W, which
is typical value in real case. Cooling requirement is to
maintain maximum air temperature inside the cabinet below
70℃ with least noise and energy cost by cooling system. The
Water-soil heat exchanger is made up of three layers tubes
buried underground. The outer diameter of the tube is 20mm
and inner diameter is 15.4mm. Depth of three layers is 1.2m,
1.8m and 2.4m. Tube length in every layer is about 20m.
Fig 3 Profile of outdoor cabinet with GCS
Thermocouples are placed at following points: two points
for inlet and outlet water of water-soil exchanger or air-water
exchanger, four points for inlet and outlet air temperature of
outdoor cabinets, two points for chassis inlet and outlet air.
Eight points for soil temperature in different depth (0.3m,
0.6m, 0.9m, 1.2m, 1.5m, 1.8m, 2.1m, 2.4m), two points for
ambient air temperature. Test data are recorded by Data
Acquisition System.
Ⅲ. TEST RESULT AND DATA ANALYSIS
Test starts with soil temperature investigation. During the
test, the telecom equipment is not powered on. Figure 4
shows the soil temperature variation for eight days. The
temperature of soil under 1.2m is almost stable and change
little with air temperature. In 8 days, air temperature
21℃
varies
from to 40 , while soil temperature at 0.6m depth
varies only from 26 to 29 and only 1.2m
depth. These temperature data will be used as reference
temperature point in followed analysis. Figure 5 provides the
comparison of daily mean soil temperature among the
different layers and variation in ten days. Soil temperature
decreases along with depths. There is about
℃
temperature difference between 1.2m and 2.1m. The variation
rate of daily mean soil temperature under 1.2m depth is lower
than 0.045 /day
1℃
0.8~1℃
©EDA Publishing/THERMINIC 2009 14
ISBN: 978-2-35500-010-2
℃ ℃ changes
at
℃ .

7-9 October 2009, Leuven, Belgium
soil is lower than 0.04℃/day. This variation rate is almost the
same with that of original soil, which explains that the heat
introduced to the soil is conducted to surrounded soil, not be
transferred by the surface air.
Fig4. Temperature curve of soil in different depths and atmosphere
Fig 6 Chassis outlet temperature inside outdoor
Fig5. Daily mean soil temperatures in different depths
Figure 6 shows the cooling performance comparison with
and without GCS. When the GCS is applied, it decreases the
cabinet maximum air temperature by 25℃. Noise level of
cabinet with GCS is less than 35dBA, which is lower than that
of air-air heat exchanger (normally 55~65dBA). The low
noise performance meets the health requirement for
residential area, this requirement is extreme strict in Europe
countary. Power consumption of fan and pump is about 6w
and 16w respectively, resulting in COP=34 for the cooling
system, which is much higher than that of traditional cooling
method such as air-air heat exchanger (normally 10~15) and
air conditioning (normally 3~4).
Figure 7 shows transient temperature curve of ambient and
cabinet. In the first ten days of test, the air temperature inside
cabinet rises up slowly, it is caused by thermal inertia of the
soil. After then, the air temperature inside cabinet runs into
periodical temperature circle synchronized with ambient air.
The cabinet has two parallel heat dissipation paths, one path is
via cabinet’s wall, and another is via GCS. The fluctuation of
air temperature explains that the cabinet wall heat dissipation
still affect the performance the system. Also, the four weeks’
test result show that air temperature inside cabinet is under 60
℃, 10℃ below the limitation value. The cooling performance
meets the design target.
Figure 8 shows transient daily mean soil temperature. Soil
temperature increases 3~4℃ after four weeks test (not include
0.6m and 0.9m depth, which is influenced by ambient). Soil
temperature is almost stable from date 07/02 to date 07/08.
The variation rate of daily mean temperature of 2.1m depth
Fig7 Transient temperature curve of GCS and cabinet
Fig8 Transient curve of daily mean soil temperature
The heat transfer value by soil is calculated by equation(1):
p
( T −T
)
Q = C ρ V
(1)
inlet
outlet
C
p
: Thermal capacity of water, J/kg . k;
ρ : Density of water, kg/m^3
V : Average flow rate inside water-soil exchanger, m/s
T
inlet
and T
outlet
: Inlet and outlet of water temperature of
water-soil exchanger ,℃
Figure 9 and figure 10 show the variation about heat
dissipation value of soil during one day and one month. It
changes with air temperature and solar radiation intensity.
During the hottest the time of the day, the cooling
performance by the cabinet wall is weaken, the GCS dissipate
©EDA Publishing/THERMINIC 2009 15
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
about 600W, up to 80% of the total heat. During other time of d i : Inner diameter of tube, m;
the day, the GCS dissipate 50%~60% of the heat, other heat
is dissipate to the decreased ambient air by the cabinet wall,
also the soil get time to recover. Above conclusion is proved
as well in result of long time test showed in figure 10.
Heat dissipated by soil will be reduced in winter as ambient
air temperature decreases to low level. The soil temperature
gets more time to recover back. In ultra low temperature
environment, the soil can also heat up the cabinet to proper
temperature; this will save a lot of heating energy. The test is
continued to verify it.
d o : Outer diameter of tube, m
Nu: Nuselt number;
λ p : Thermal conductivity of tube’s wall, w/mk
λ: Thermal conductivity of water, w/mk
For this GCS prototype, calculation result shows that R 1 is
close to 0.04 ℃/(Wm) and R 2 is close to 0.1℃/(Wm). Because
soil is high thermally inertial, figure 11 shows that R soil increases
gradually and becomes stable in a range finally. This value can
be use for fast engineering design. As R soil is the key design
parameter, it relate with many factor like property of the soil,
layout and size of tube, buried depth and etc., more research
should be carried out in the future work.
Fig 9 Transient curve of heat dissipated by soil in one day
Fig11 Transient thermal resistance curve of R soil
IV.
CONCLUSION
Fig 10 Transient curve of heat dissipated by soil for long time
It is necessary to set up an effective model for fast evaluation
of GCS cooling performance. As water-soil heat transfer process
is the most important part, this work start with the research
on R soil
. R
soil
is the thermal transfer resistance per unit length
of the tube:
R = L( T − T ) / Q − R − R (2)
soil ave soil
( )
R 1 πd i
h i
h Nuλ
/
1 2
= 1 (3)
= (4)
i
d i
R2 = ln( do / di ) / 2πλ
pL
Where,
L: Length of water-soil exchanger, m
Q: Heat dissipated by soil, W
R 1 : Thermal resistance from fluid to tube’s wall per unit
length (℃/Wm)
R 2 : Thermal resistance of tube’s wall per unit length
(℃/Wm)
T ave : Average temperature of fluid inside tube
T soil : Original soil temperature
A new geothermal cooling solution with good performance,
low noise and high energy efficiency for telecom outdoor
cabinet has been presented. The basic heat transfer behaviour of
the entire system (cabinet and GCS) is analyzed with transient
temperature data. With effective performance and low cost, this
GCS is more competitive compared with traditional cooling
solutions. It is necessary to carry out further research for design
and application.
REFERENCES
[1] Guizhi G., etc, “Simple calculation for GSHP heat-exchanger”,
Energy Conservation, 274(2005), pp.22-24.
[2] Li Xingrong, Zhang Xiaoli, Liang Biling,Yang Lin, “Diurnal
variation of Soil temperature and its vertical profiled in summer in
shenzhen city,” ScienceTechnologyandEngineering, vol.8,
pp5996-6000, 2009.
[3] “Soil cooling system for small site (KPN),|” ETNO annual report
2008, 7-3, pp.37.
[4] Hong Yuping, Ji Shengqin, Zhai Liqian, Chen Qiao, Claudio Bianco,
“Cooling System of Outdoor Cabinet using Underground Heat Pipe”
11-1978-1-4244-2056-8/08 2008 IEEE Intelec, 13-1.
©EDA Publishing/THERMINIC 2009 16
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
A New Methodology for Early Stage Thermal
Analysis of Complex Electronic Systems
O. Martins 1 , N. Peltier 2 , S. Guédon 2 , S. Kaiser 2 , Y. Marechal 1 and Y. Avenas 1
1
G2ELAB, UMR 5269 INPG-UJF-CNRS, BP 46, 38402 Saint Martin d’Hères Cedex, France
2
DOCEA Power, 166B, rue du Rocher du Lorzier, 38430 Moirans, France
Phone: +33 4 76 82 64 38 - Email: Olivier.Martins@g2elab.grenoble-inp.fr
Abstract-This paper presents a new methodology called Flex-
CTM for Flexible Compact Thermal Modeling to build and to
interface compact thermal models at different modeling levels.
Each part of an electronic system is prepared to be Bou ndary
Condition independent (BCI) such as to be plugged to other
parts. Each part model is reduced to save memory and time
consuming at the simulation stage. The resulting pluggable and
reduced thermal model is called a micro-model. Therefore, a
fast-to-simulate macro-model of a full microelectronic system
can be obtained by assembling micro-models.
The Flex-CTM is found to have numerous advantages over
both current resistive models (junction-to-case and junction-toboard)
and Dynamic Compact Thermal Models. The first
advantage of the methodology is that multi-source and dynamic
simulations of an electronic system can be performed at any
design level. The second one is the control of the accuracy. The
third advantage is the Boundary Condition Independence
property that allows architecture exploration. Finally and the
most important, micro and macro-models can be shared by
teams to be reused and completed.
Keywords - Compact Thermal Modeling, model coupling,
Boundary Condition Independence, multi-level modeling.
I. INTRODUCTION
In microelectronics, device designers are increasingly
miniaturizing the electronic components, to design smaller
products and to add more features. This miniaturization is at
the origin of a strong rise of the power density. In addition,
the power density rise with the temperature elevation lead to
strong electro-thermal phenomenon that can damage
electronic components.
Hot spots on the components cause thermal and
mechanical stresses which affect circuit reliability.
Furthermore, thermal gradients within the die, due to local
hot spots, involve delay errors in logical gates and thereby
limit expected performances. As discussed before, the
temperature rise leads to an overconsumption that reduces
the autonomy of nomad systems. Moreover, high
temperatures decrease the life time of a system. Combined
with a strong electro-thermal loop phenomenon, the
component can be damaged by thermal runaway.
In order to limit these risks, electronic engineers have to
perform transient thermal simulations at an early stage of the
design flow, and at several granularity levels (die, package,
board). Many teams in a single company are in charge of
building their own thermal model (package model, die
model, board model...). The different modelling scales do
not allow to obtain a single fine multi-level model. The
Flex-CTM methodology, allows to share each specific
thermal model in such a way that each separated thermal
model is fine and can be evaluated by setting its own
environment and other model dependency to perform more
realistic simulations.
To speed up the thermal characterization process, the
models must be compact and accurate to run fast simulation
allowing a maximum bias of 5%. To summarize the need, a
model must meet the following four criteria. First, the
models have to be dynamic to allow transient simulations.
Second, multiple power sources can be applied to fit with
real case exploration (e.g., architectural level, many dies in a
package, many packages on a board, ...). Third, to save
simulation time, the models must have a reduced number of
unknowns. Fourth, to be pluggable and reusable in different
use cases, the models have to be Boundary Condition
Independent (BCI).
The paper is divided into 5 parts. First, a short
background of existing thermal models is presented.
Second, the Flex-CTM methodology is introduced
explaining the build of elementary pluggable compact
thermal models. Third, the modeling and the simulation of
the whole system is explained. Fourth, a synthesis describes
the interest of the methodology. Finally, the speed and
accuracy performances of the methodology are evaluated for
a typical co-simulation case.
II.
BACKGROUND
Several models already exist to simulate the thermal
behavior of an electronic system. First, numerical methods
(for example, the Finite Element Method) split a volume into
elementary units. According to the JEDEC convention, the
numerical thermal model is also called detailed model. This
kind of model is difficult to build if the geometries are
complex because the build of a well adapted mesh becomes
arduous. Moreover, these numerical models become huge
and slow to simulate.
Pioneering DELPHI methodology has been introduced to
generate smaller models, in terms of number of unknowns
[1]. This is a fitting method that creates Compact Thermal
Models (CTM). A CTM is made of a network of resistors
between key points of a package (a junction and outers).
Other fitting methodologies have been introduced to add
capacitive terms in the DELPHI compact models [2], like the
©EDA Publishing/THERMINIC 2009 17
ISBN: 978-2-35500-010-2

External
Nodes (ne)
European project PROFIT [3] and [4]. The building of these
models takes a lot of time because many simulations of the
detailed model must be performed in transient domain,
varying heat transfer coefficients applied on exchange
surfaces. In addition, the junction modeling in DELPHI-like
models is quite rough because it is considered as a single
uniform heat dissipation source.
Recently, HotSpot analytical models [5], have been
introduced to enhance the thermal model capabilities. The
static and dynamic behaviors are addressed by a resistive and
capacitive network between blocks at different scale levels.
These models are mostly specific for the die. The package
and board models are quite coarse and valid for specific heat
flux distribution.
None of the existing methods meet the whole
specifications quoted previously (Introduction section §4).
In the following section, the Flex-CTM methodology is
introduced to build pluggable Flex-CTM (Flexible Compact
Thermal Models). The Flex-CTM are exclusively
conductive models; the convection and the radiation are
considered as first order phenomena. A Flex-CTM is a
thermal resistance and capacitance network between nodes
and can be assimilated to an electrical RC network by
thermoelectric analogy.
III. BUILD OF PLUGGABLE COMPACT THERMAL MODELS
Usually, thermal models are built by different actors at
different integration levels and the classical methodology
does not allow to easily reuse and couple these models. The
Flex-CTM methodology begins with the creation of a micromodel
for each part of the whole system. A micro-model is
a BCI compact thermal model with external connections for
power sources, imposed temperatures, convection, and other
conductive models. This section explains how to build a
micro-model.
Model splitting is the first stage of the methodology
which breaks up the global geometrical electronic system
into elementary homogeneous material parts. For instance, a
BGA package (Figure 1) is split into four descriptions (die,
substrate, encapsulant and bondwires). The interfaces of the
elementary parts are classified into two groups: power
sources (interface P) and exchange interface with the
environment (interface E).
Substrate
Encapsulant
7-9 October 2009, Leuven, Belgium
accurate models of every part can be built in such way the
discretization of the domain is adapted to a single material.
The Finite Element Method (FEM) is chosen to retrieve the
physical transfer functions at any meshing node. The
transfer functions between nodes are written as a thermal
admittance system. This system conjugates the thermal
conductance sub-system G and the thermal susceptance subsystem
C. The matrices G and C are square, symmetric and
strictly definite positive. Equation (1) shows the
computation of each element of the matrices G and C where
k is the thermal conductivity of the material (in W.m -1 .K -1 ), ρ
is its density (in kg.m -3 ) and C p is its specific heat (in J.kg -
1 .K -1 ). Ω is the volume of the FEM meshing element. α k is
the form function according to the Galerkin method.
G(
i,
j)
=
C(
i,
j)
=
∫∫∫
∫∫∫
k.
div(
α ). div(
α ) dΩ
ρ C . α . α dΩ
p
Moreover, the extraction process gives the geometrical
properties of all the meshing nodes.
Third, the node selection step prepares the numerical
model before being reduced. To perform it, a subset of
external nodes which will be kept after reduction, has to be
defined. The number of external nodes must be lower than
the original one to obtain a small model after reduction.
However, their number and their position have to ensure the
most faithful transfer of the heat flux through the interface.
So, the user has to define sub-sampled interfaces which are
used in place of the original ones. The ne’ nodes on this new
interface are used to apply environmental and to measure the
temperature at several points of the system. The user
controls the trade-off between accuracy and the size of the
reduced model for his study case, modifying the number of
external nodes ne'. The replacement of the original interface
by the sub-sampled one is performed through a coupling
method. This coupling tool is detailed in the following
section (“Whole System Modeling and Simulation”). The
resulting model is the numerical model in which original
interfaces (P and E) are substituted by sub-sampled
interfaces (P’ and E’), see Figure 2.
Original FEM
Model
i
i
j
j
(1)
Internal
Nodes (ni)
Coupling
Die
Bondwires
Figure 1: Geometrical and Physical Description of each part of a BGA
Package
Second, the extraction process begins with the build of a
numerical model of each part of the whole system, without
any boundary condition. The model splitting step enables to
mesh finely each model, without taking into account the
geometrical constraints of the environment. Thus, more
Figure 2: Node Selection
Nodes of the
Sub-sampled
Interface (ne')
Fourth, the reduction process enables to decrease the
dimension of a system, preserving its first order moments.
The matrices G and C are ordered to place the nodes of
respectively P' and E' at the ne' first columns. A Model
Order Reduction (MOR) technique, based on projections on
the Krylov subspace has been used to reduce the dimension
[6], [7], [8].
©EDA Publishing/THERMINIC 2009 18
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7-9 October 2009, Leuven, Belgium
The discreet expression of the detailed model in time system is built.
domain has a static member and a dynamic member (2).
IV. WHOLE SYSTEM MODELING AND SIMULATION
G x + C x = B p
(2)
Where G is the thermal conductance subsystem, x the
vector of the unknown temperatures, C the subsystem of
thermal capacitances, B the input-output driver matrix, and p
the vector of the discreet inputs-outputs.
G and C are sparse and symmetric definite positive m x n
as dimension. The vector p and x are dense vector of size m
x ne.
To reduce the dimension of the system (2) the moment
matching procedure will be applied in the frequency domain
using the Laplace transformation.
T
Y(
ω)
= B ( G+
jωC)
B
thenY(
ω)
= B ( I + jωA)
R
andT(
ω)
= Y
T
−1
( ω)
p
if
R = G
−1
B and A = G
Where Y is the thermal admittance of the system, and T
the vector of the unknown temperatures in the frequency
domain.
The matrix B must be chosen to perform the average of
temperatures and the average of power sources according to
the P interface, elsewhere it is the identity. Therefore,
Arnoldi algorithm is computed on A and R to extract the
orthogonal bases U that spans the Krylov subspace.
−1
( −n'
+ 1)
{ R,
A R,...
A R}
−1
C
(3)
Kn' ( A,
R)
= col − span ,
(4)
Once U is calculated for a first number of moments (n' =
ne+ni'), ni' starting at 10, the reduction is done by projecting
G, C and B onto the base.
This section deals with the coupling of micro-models to
build a complete model of an electronic system. These
micro-models are coupled together through their respective
E’ interface nodes. The interfaces of the models to connect
are not supposed to have the same geometrical configuration.
Therefore, the models cannot be coupled by just linking the
interface nodes one by one. In the followings, the coupling
method that allows to connect two micro-models is
described.
Two micro-models (G 1 , C 1 ) and (G 2 , C 2 ) are assembled in
a non-coupled system equation (7). Where G k (k = 1 or 2) is
the conduction matrix and C k is the diffusion matrix of the
micro-model k. T k is the vector of temperature at each node
of the micro-model k. F k is the load vector at each node of
the micro-model k.
⎡C1
⎢
⎣ 0
0 ⎤⎡T
1
⎤ ⎡G
⎥⎢
⎥ + ⎢
C2
⎦⎣T
2 ⎦ ⎣ 0
1
0 ⎤⎡T1
⎤ ⎡F1
⎤
⎥⎢
⎥ = ⎢ ⎥
G2
⎦⎣T2
⎦ ⎣F2
⎦
The distribution of the nodes of the two uncoupled micromodels
is described Figure 3. The “e” index is for the
external node block, and the “i” index is for the internal node
block. The structure of the nodes of the two models is
modified in order to isolate the external nodes of the model
2, see (8).
T 1i T 1e T 2e T 2i
(7)
G' n' = U T GU
C' n' = U T CU
B' n' = U T B
The MOR technique is enhanced by adding a postprocessing
that controls the accuracy of the reduction. To
control the accuracy, the matrix Y' of the transfer functions
of admittances is calculated (6) in the frequency domain.
Note that Y' is very fast to compute.
(5)
Model 1 Model 2
Figure 3: Nodes Distribution of two Uncoupled Models
T '
1
= T
1e
T '
2
∪T
= T
1i
2e
∪T
The objective of the coupling process is to create links
(G 12 , G 21 , C 12 , C 21 ) between two models as shown in
equation (9).
2i
(8)
where
' T
Y '( ω)
= B ( I + jωA
) R
R'
= G
' −1
'
'
'
B and A = G
'
' −1
C
'
(6)
⎡C
⎢
⎣C
11
21
C
C
12
22
⎤ ⎡T
'
⎥ ⎢
⎦ ⎣T
'
1
2
⎤ ⎡G
⎥ + ⎢
⎦ ⎣G
11
21
G
G
12
22
⎤ ⎡T
'
⎥ ⎢
⎦ ⎣T
'
1
2
⎤ ⎡F'
⎥ = ⎢
⎦ ⎣F'
1
2
⎤
⎥
⎦
(9)
While the mean of the Y' (6) values are changing,(3), (4)
then (5) are calculated increasing ni'. This loop allows to
ensure to extract the optimum first order moments that match
the Krylov subspace. The reduced model has ne' external
nodes and N' unknowns where N' is approximately 10% of
N.
At this stage, a micro-model of each part of the whole
with
G
C
11
11
= G ∪ G
= C ∪ C
2i
2i
F' = F ∪ F F'
= F
1
1
1
1
2i
G
C
22
22
2
= G
= C
2e
2e
2e
(10)
Where G 2i (resp. C 2i , F 2i ) is the internal node sub-block of
©EDA Publishing/THERMINIC 2009 19
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G 2 (resp. C 2 , F 2 ) and G 2e (resp. C 2e , F 2e ) is the external node
sub-block of G 2 (resp. C 2 , F 2 ).
The link is realized by the method of Lagrange multipliers
[9]. It transforms a minimization problem under constraints
in a minimization problem without constraint. The Lagrange
multipliers allow to solve the heat equation (7), ensuring the
continuity of temperature at the interfaces of the two models
(11).
T
' = X T
'
2
2
1
T ' = X T '
1
(11)
Where X is the cross coupling between the nodes of the
two model interfaces.
This mathematical method applied to the thermal model
coupling issue is described in [10]. The looking for the
singular points of the Lagrangian gives the following matrix
system:
⎡C
11
⎢
⎢C21
⎢−
X
⎢
⎢⎣
0
C
12
22
C
I
0
− X
I
0
0
T
0⎤
⎡T
' 1⎤
⎡G
11 G
⎥⎢
⎥ ⎢
0⎥
⎢T
'
2⎥
+ ⎢G21
G
0⎥
⎢λ
⎥ ⎢
1 0 0
⎥⎢
⎥ ⎢
0⎥⎦
⎢⎣
λ2
⎥⎦
⎢⎣
− X I
12
22
T
0 − X ⎤⎡T
' 1⎤
⎡F'
1⎤
⎥⎢
⎥ ⎢ ⎥
0 I ⎥⎢
T ' 2⎥
= ⎢
F'
2⎥
⎥ (12)
0 0 ⎢λ
1⎥
⎢ 0 ⎥
⎥⎢
⎥ ⎢ ⎥
0 0 ⎥⎦
⎣λ
2⎦
⎣ 0 ⎦
Eliminating λ 1 , λ 2 and T’ 2 in (12), leads to a new equation
system (13) which describes the thermal behavior in
transient state of the two coupled models.
~
C T ~ ~
' 1 + GT ' 1 = F
(13)
where
~
T
T
C = C11
+ X C21
+ C12
X + X C22
X
~
T
T
G = G11
+ X G21
+ G12
X + X G22
X (14)
~
T
F = F'
+ X F'
1
2
In this methodology, the coupling matrix X is an
application of the nodes of interface 2 to interface 1. For
each node Node2 j to be replaced in interface 2, the
surrounding 4 nodes in interface 1 are identified (see Figure
4).
T2
T j
(x,y)
T1
7-9 October 2009, Leuven, Belgium
1+
x 1+
y
1−
x 1+
y
α1(
x,
y)
=
α 2 ( x,
y)
=
2 2
2 2
1−
x 1−
y
1+
x 1−
y
α3(
x,
y)
=
α 4 ( x,
y)
=
2 2
2 2
(15)
Then, the temperature T j of the node Node2 j is computed
through equation (16).
T j
( x,
y)
= α1(
x,
y).
T1+
α 2 ( x,
y).
T 2 +
α ( x,
y).
T3
+ α ( x,
y).
T 4
3
4
(16)
The equation (16) expresses the temperature T j as the
linear combination Λ j of the second interface temperatures.
T
j
= Λ j.T ' 1
(17)
Finally, the coupling matrix X between the two models is
built by all the line matrices Λ j (18).
[ Λ Λ
] T
X = (18)
1 1 Λ ne' 2
Where ne' 2 is the number of external nodes in the model 2.
X is a rectangular matrix of size ne' 2 x (n 1 +ni 2 ), where n 1 is
the number of nodes of the model 1 and ni 2 is the number of
internal nodes of the model 2.
The Flex-CTM resulting from the coupling process is a
RC network which can be solved with a Spice like transient
simulator. Fixed potentials are applied on the model, to
impose temperatures Ti on several external nodes of the
Flex-CTM. Then, convection resistors R conv (19) are plugged
on the convection surface nodes nodes to impose heat
transfer coefficients on surfaces of the system.
R conv
= 1
hS
(19)
Where h is the heat transfer coefficient applied on the
surface S of the model. Then, the power sources Q are
applied on P’ interface nodes and the Flex-CTM can be
simulated in a transient scenario (see Figure 5).
T3
T4
Nodes of the interface 1
Node Node2 j
Figure 4: Neighbor Nodes Configuration for a Hexahedral Mesh of the
Interface 1
Thus, the neighbor nodes of Node2 j are weighted,
computing the form factors at the coordinates of the node
Node2 j . Equation (15) shows the general form factors for a
hexahedral mesh of first order.
Power
Sources Q
Imposed
Temperatures Ti
Flex-CTM
Figure 5: Simulation Condition Application
Convection
Resistors R conv
V. INTEREST OF THE FLEX-CTM METHODOLOGY
The building process of the Flex-CTM methodology is
illustrated Figure 9. The models generated by the method
present numerous advantages over the existing thermal
models.
Flex-CTM models meet the specifications because they
©EDA Publishing/THERMINIC 2009 20
ISBN: 978-2-35500-010-2

T junction
Tinterface model 1
are small, they can be reused and shared between the
different design teams.
Precisely, the methodology homogenizes the models at
different integration levels to facilitate the share of the
models. In that way, a designer builds finely its own model
of interest using other available micro-models of materials
and environments.
Moreover, the Flex-CTM models contain few information
of the original system. The geometrical and physical
properties of the system are included implicitly in the model.
Therefore, the models can preserve a confidentiality of the
system properties.
Finally, the Flex-CTM have the “Flexible” property.
Meaning that each micro-model of the Flex-CTM can be
modified independently and replaced by another one.
VI. EVALUATION OF THE PERFORMANCES OF THE
FLEX-CTM METHODOLOGY
The methodology is evaluated with a simple co-simulation
test case. The studied system is a die in a Ceramic Pin Grid
Array (CPGA) package, plugged on a Printed Circuit Board
(PCB). The typical use is an integrator who wants to
characterize a board for a given component. The integrator
may have obtained the die and package information in
datasheets or even their micro-models. The geometry of the
IC package is described Figure 6.
Lid
Step 2 Step 2
Step 1 Die Step 1
Substrate
Pins
PCB
Figure 6: CPGA Geometrical Description
To evaluate the influence of the board on which the
component will be plugged, the component is connected to
two different boards (Figure 7).
a)
b)
Figure 7: Studied Printed Circuit Boards
a) 1s0p
b) 2s2p
7-9 October 2009, Leuven, Belgium
The model has been built with the typical values of the
material thermal properties which can be found in the
literature [11].
The air layer surrounding the die is assumed to be
insulating due to its very weak thermal conductivity. So, in
this case a unique die-to-package heat flow path through the
bottom face of the die is considered. The CPGA is
simulated applying a uniform power source of 1W on the
junction surface.
A reference measure of the average temperature on the
Die junction is obtained by simulating a FEM model of the
full circuit. This measure is a reference to evaluate the
methodology in terms of accuracy, model size and
simulation time.
The first step of the Flex-CTM methodology splits the
CPGA geometry into 4 descriptions according to the
physical properties (see Figure 8).
Die
Pins
Figure 8: Model Splitting
CPGA Package
PCB
The junction interface is on the top of the die and the
model contains 3 coupling interfaces. The first one links the
die to the package substrate, the second one links the
package substrate to the pins and the last one links the pins
to the PCB. The 4 (Die, Package, Pins, PCB) FEM models
of the system are extracted in their respective numerical
systems G 1,2,3,4 and C 1,2,3,4 with their related node properties.
Concerning the heat transfer coefficients, they are identified
using a commercial CFD tool. Then they are embedded in
the CPGA Package and in the board models. The nodes
belonging to the interfaces of the models are kept during the
reduction process. TABLE I summarizes the number of
nodes of each part at different steps of the methodology. The
number in brackets indicates the number of external nodes
kept of each micro-model.
1. System Splitting 2. Model Extraction 3. Node Selection
6. Simulation with Specific
Condition Setting
Mean tem peratures
25
5. Model Coupling 4. Model Reduction
T [deg]
20
15
T interface model 2
10
tim e [s]
5
0
10 -6 10 -4 10 -2 10 0 10 2 10 4
Lagrange Multipliers
Figure 9: Building Process of the Flex-CTM Methodology
G,C
matrices
©EDA Publishing/THERMINIC 2009 21
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TABLE I
MODEL PARTS CHARACTERISTICS
Part FEM Model Sub sampled Model Reduced Model
Die 70k (2600) 65k (227) 335 (227)
Package 147k (12k) 136k (356) 643 (356)
Pins 69k (3400) 66k (200) 208 (200)
PCB 1s0p 178k (900) 177k (100) 978 (100)
PCB 2s2p 178k (900) 177k (100) 822 (100)
Once the micro-models are available, they are coupled
together through their corresponding coupling interfaces
(E’). An assembly (die-package-pins) resulting of the
coupling of the die, package and pins models is obtained.
Then, to study the influence of the board, each PCB micromodel
is connected successively to the assembly. So, two
Flex-CTM of the whole system are built, one for each board.
Finally, a power step source of 1 W is uniformly
distributed on the Junction interface P'. Reference
simulations of the global FEM model are computed for each
board and the corresponding Flex-CTMs are simulated under
the same simulation conditions (Figure 10).
Figure 10: Original Model and Flex-CTM Temperatures
The comparisons in terms of accuracy, model size and
simulation time between the original CPGA and the Flex-
CTM are summarized in TABLE II. The first Flex-CTM
needs about 4 hours to be built. The second needs only one
half hour because the assembly die-package-pins is reused.
TABLE II
ORIGINAL AND FLEX-CTM MODELS PERFORMANCES
Model Size Simulation Time
FEM Assembly 1s0p 530k 24 hours
Flex-CTM 1s0p 1583 12 seconds
FEM Assembly 2s2p 530k 24 hours
Flex-CTM 2s2p 1427 12 seconds
Maximal Absolute
Error
0.57°C
0.52°C
VII. CONCLUSIONS AND FUTURE WORK
The Flex-CTM methodology meets the needs of electronic
engineers to perform a fast temperature analysis of a
complex electronic system at different integration levels.
Flex-CTM are BCI, so they can be reused whatever the
environment is. Many power sources can be applied on
7-9 October 2009, Leuven, Belgium
junction nodes allowing hot spot detection on a die.
Moreover, Flex-CTM have a few node number, which
allows multiple exploration or electro-thermal simulation in
a short window of time. Finally, the methodology allows
system designers to share their work at different integration
levels.
The methodology has been evaluated with a simple testcase
at the package modeling level. The results show that
Flex-CTM meet the specifications required, specifically in
terms of accuracy and simulation time saving.
The next step is now to enhance the methodology with an
automated selection of the number and the position of nodes
at the interfaces. This progress will ensure a higher accuracy
and an optimal size of the Flex-CTM.
Besides, several test cases covering multi-level design
aspects are to be run in order to go on further the validation
and to better characterize the methodology.
Finally, a multi-source co-simulation test case will be
studied to fit with a more realistic system.
REFERENCES
[1] H. Vinke and C. Lasance, "Compact Models for Accurate Thermal
Characterization of Electronic Parts", IEEE Transactions on
Components, Packaging and Manufacturing Technology – Part A,
Vol. 20, NO. 4, December 1997
[2] F. Chrisitiaens, B. Vandevelde, E. Beyne, R. Mertens and J.
Berghmans, "A Generic Methodology for Deriving Compact
Dynamic Thermal Models, Applied to the PSGA Package", IEEE
Transactions on Components, Packaging and Manufacturing
Technology – Part A, Vol. 21, NO. 4, December 1998
[3] C. Lasance, "The European Project PROFIT: Prediction of
Temperature Gradients Influencing the Quality of Electronic
Products", Proceedings of the SEMITHERM XVII, pp. 120 – 125,
2001
[4] C. Lasance, "Highlights from the European Thermal Project
PROFIT", Journal of Electronic Packaging, Vol 126, pp 565 – 570,
December 2004
[5] W. Huang, K. Sankaranarayanan R.J. Ribando, M.R. Stan and K.
Skadron, "An Improved Block-Based Thermal Model in HotSpot
4.0 with Granularity Considerations", Proceedings of the Workshop
on Duplicating, Deconstructing, and Debunking (WDDD), in
conjonction with the 34 th International Symposium on Computer
Architecture (ISCA), 2007.
[6] Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon
X.D.Tan, and Jun Yang, "Efficient Thermal Simulation for
RunTime Temperature Tracking and Management", Proceedings of
the 2005 International Conference on Computer Design (ICCD'05).
[7] D. Celo, X. Guo, P. K. Gunupudi, R. Khazaka, D.J. Walkey, T.
Smy and M.S. Nakhla, "The Creation of Compact Thermal Models
of Electronic Components Using Model Reduction," IEEE
Transactions on Advanced Packaging, Vol. 28, NO. 2, May 2005.
[8] L. Codecasa, D. D'Amore and P. Maffezzoni, "An Arnoldi Based
Thermal Network Reduction Method for Electro-Thermal
Analysis", IEEE Transactions on Components and Packaging
Technologies, Vol. 26, No. 1, March 2003.
[9] G. Strang, "Introduction to Applied Mathematics", Wellesley
Cambridge. Press USA, 1986.
[10] T. Bechtold, E. B. Rudnyi, M. Graf, A. Hierlemann, J.G. Korvink,
"Connecting Heat Transfer Macromodels for MEMS Array
Structures", Journal of Mechanics and Microengineering, 15(6), pp
1205 – 1214, 2005
[11] MatWeb, division of Automation Creations, Inc
http://www.matweb.com
©EDA Publishing/THERMINIC 2009 22
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7-9 October 2009, Leuven, Belgium
Validation Studies of DELPHI-type Boundary-
Condition-Independent Compact Thermal Model for
an Opto-Electronic Package
Arun P. Raghupathy, Attila Aranyosi, William Maltz
Electronic Cooling Solutions, Inc.
Santa Clara, CA 95051
Urmila Ghia and Karman Ghia
Computational Fluid Dynamics Research Laboratory
University of Cincinnati, Cincinnati, OH 45220
A Boundary-Condition-Independent (BCI) Compact
Thermal Model (CTM) was generated for an opto-electronic
transceiver package called SFP (Small Form-factor Pluggable
device). The SFP has four internal power dissipating sources
and the BCI CTM for the SFP was developed using the
DELPHI methodology. This paper presents a detailed
validation of the BCI CTM of the SFP in real-time applications
using Flotherm, a Computational Fluid Dynamics (CFD)-based
thermal analysis software package. The results show excellent
agreement between the results predicted by the SFP CTM with
the data from the detailed model and from the experiments.
The SFP CTM predicts the junction temperature of the four
power dissipating components and the heat flows through the
sides with relative error less than 10%. In addition to accurate
thermal characterization of the SFP, the SFP CTM facilitates a
large order reduction (105 to 1) in the CFD-based
computations. Advantages and limitations on using the
DELPHI methodology for generation of CTM for the SFP are
also discussed.
method cannot be used for packages with multiple heat
sources where the package surface does not adhere to the
similarity condition. But as discussed in an earlier work
[10], the DELPHI method can be used for modeling
packages such as the SFP. Many approaches [11-16] have
been suggested for modeling of components with multiple
heat sources. But most of these methods cannot be used to
readily represent the SFP in a commercial CFD-software
because of the presence of four heat sources and the
presence of radiation heat transfer within the package. A
detailed introduction to the functions of the SFP and the
need for its compact thermal model has been discussed in
[10]. The study also presented a BCI CTM for the SFP
(referred to as SFP CTM henceforth) that was developed
using the DELPHI (DEvelopment of Libraries of PHysical
models for an Integrated design) methodology.
I. INTRODUCTION
The Small Form-factor Pluggable device (SFP) [1], shown
in Fig. 1, is an optical transceiver used in telecommunication
and data-communication equipment such as
routers and switches. The package has a detailed
construction, and typically has four heat-generating sources
as shown in Fig.2: Laser Diode (LD), Trans-impedance
Amplifier (TIA), Laser Diode Driver (LDD) and Transceiver
IC (Post Amp IC). Because of the presence of a laser diode,
the component is thermally sensitive to its environment.
Accurate CFD-based thermal analysis is necessary in order
to design systems that use these optical transceivers. To
capture the complete thermal characteristics accurately,
detailed modeling of the SFP with hundreds of thousands of
grid points are used. Therefore, it becomes impossible to
have detailed SFP models within systems that use multiple
SFPs. This creates a need to represent the SFP by a
simplified model. The DELPHI (DEvelopment of Libraries
of PHysical models for an Integrated design) project [2-8]
was started to primarily address similar issues of single-heat
source IC packages and to provide better thermal
characterization. It has been used for multiple (two) heat
sources by Assoud [9]. As discussed by Lasance [8], the
Data out
Data in
Fig.1. Small Form Factor Pluggable Optical Transceiver
Laser
Diode
Photo
Diode (TIA)
LDD
PA IC
Fig.2. Layout of a SFP
©EDA Publishing/THERMINIC 2009 23
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II.
DEVELOPMENT OF CTM FOR SFP
The CTM for the SFP was generated using the DELPHI
methodology using Matlab 7 codes [18]. In house codes
were developed for solving the conservation equations of the
network topology and for interfacing with the optimization
algorithm [21][22]. The codes were validated with
experimental data from Aranyosi et al. [19][20]. Network
topology was not constructed by reducing a fully connected
network as suggested in [2]; rather, it was built from the
bottom up by constructing simple networks and increasing
their complexity. Many network topologies were analyzed
and the resulting network topology used for representing the
SFP is shown in Fig. 3. In this figure, nodes 1, 2, 3 and 4
represent the four power dissipating components. The sides
are represented by nodes 6, 7, 8 and 9. Node 5 represents a
floating node used for redirecting heat flow. The front and
back sides are insulated and are not represented by nodes.
Node No.
1
6
3 4
8 5 9
7
Node Name
1 Laser Diode
Trans-impedance
2 Amplifier
3 Post Amp IC
4 Laser Driver
5 Floating Node
6 Top Side
7 Bottom Side
8 Left Side
9 Right Side
Fig.3. Network topology for the SFP CTM
2
7-9 October 2009, Leuven, Belgium
not an issue [8], it is important to understand the
performance of the SFP CTM for thermal analysis in realtime
situations. Therefore, the CTM is validated within
Flotherm, a CFD-based design and analysis tool [17] for
study of heat transfer in electronic packages.
III.
VALIDATION OF CTM FOR SFP
The CTM for the SFP is validated with results from the
detailed model for three environments representative of its
wide application in the field; natural convection, natural
convection with heatsink and forced convection.
A. Case 1- Natural Convection
Since the SFP dissipates low power (0.54 W), they are
used in some systems without any forced cooling. In these
systems, the SFPs are strategically placed so that they can be
cooled by natural convection. The SFP CTM is first
validated in a natural convection environment because the
grid density requirement for a natural convection simulation
is more stringent than one for the forced convection case.
This is due to the small scales involved. Therefore, the first
case is the simulation of a natural convection environment.
For this simulation, the SFP is placed inside a vertical
computational duct such that the left side of the detailed SFP
model faces downward. Figure 4 shows the isometric view
of the setup for simulating natural convection. Gravity is
specified in the negative-X direction. There is no flow inlet.
The details of the numerical setup are discussed in the latter
sections.
g
This SFP CTM has been validated with multiple boundary
conditions that are applied on the sides of the SFP by
specifying heat transfer coefficients (h=1 to h=1000
W/m2K)[10]. The CTM predicted results with relative
errors less than 10% on the junction temperature of all the
four heat generating sources. A maximum relative error of
20% occurred on the heat flows predicted through the sides
for unrealistic extreme cases. Although a stand-alone
validation of the SFP CTM help validate the performance,
the boundary conditions used were not representative of the
practical situations in which the SFP CTM will be used. In
practical applications, the sides of the SFP do not face
uniform heat transfer coefficient on its sides. While this is
Fig. 4 Isometric View showing the Setup of the SFP inside the Duct for
Natural Convection
B. Case 2- Natural Convection with Heat Sink
For the second case, a heat sink is fixed on to the top
face of the SFP as shown in Fig. 5. The heatsink has inplane
base dimensions equal to the top face of the SFP (13.4
mm x 37 mm) that is inside the duct with 2 mm thickness.
©EDA Publishing/THERMINIC 2009 24
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7-9 October 2009, Leuven, Belgium
The fins are 1 mm thick and there are ten fins. The heat sink
is made of anodized aluminum with conductivity of 201
W/m K. The design of the heatsink is done loosely based on
W
commercially available SFP heatsinks.
Inlet
C. Case 3- Forced Convection
The SFP is setup inside the duct for simulation of
forced convection. In this setup, the inlet is specified with
fixed flow velocities. The flow velocities that are simulated
are 0.5, 1, 2, 3 and 4 m/s. The setup is shown in Fig. 6.
5W
10W
Fig. 7 Setup of the SFP inside the Duct
Outlet
Fig. 5 Side view showing the Setup of the SFP with Heat Sink inside the
Duct for Natural Convection
Fig. 8 Side View showing the Setup of the SFP inside the Duct
Fig. 6 View showing the Setup of the SFP inside the Duct for Forced
Convection
III.
NUMERICAL METHODOLOGY
In Cases 1 through 3, the detailed model of the SFP is
placed inside a computational duct with an ambient
temperature of 20˚C. The front part of the SFP model
protrudes outside of the duct on the side where the duct is
fitted with a 5 mm thick bezel. This resembles the actual
usage of the SFP where the front part of the SFP protrudes
outside the bezel of the switch or router. The SFP model sits
on the PCB which has a thickness of 1.65 mm. The
upstream distance from the SFP model is five times the
width of the SFP. The downstream distance is ten times the
width of the SFP. This is shown in Fig. 7. A side view of the
setup can be seen in Fig. 8. The detailed model sits on the
evaluation board which has orthotropic conductivities of 33
W/m K (in-plane) and 0.38 W/m K (normal). All the other
elements in the model such as the walls of the duct and the
bezel are considered to be non-conducting. Of the three
cases, natural convection cases require the most attention
while generating the mesh. ‘Regions’ in Flotherm allow for
localized dense meshing with gradual increase in mesh size
as it moves away from the object. ‘Region’ surrounding the
detailed SFP model is used for both mesh control and for
post processing the results. In post processing, they provide
the heat flow through each side of the SFP.
(b) Side View
Fig. 9 Mesh for Natural Convection Case
(a) Top View
The top view of the mesh for the natural convection
simulation is shown in Fig. 9a and the side view is shown in
Fig. 9b. The side view clearly shows the use of localized
meshing for the components within the SFP as well as in the
environment surrounding the SFP. A similar mesh is used
for the natural convection case with the heatsink. The heat
sink has four grid cells between the fins in order to resolve
the flow passing through the fins. The mesh used for the
natural convection case is used for the forced convection
case. Each case is checked for grid independency.
The objective of the cases (Case 1 through 4) is to
validate the CTM of the SFP in real-time situations. So far,
only the use of detailed model of the SFP is mentioned. This
is because meshing requirements for the detailed model is
more complicated than for the SFP CTM. The SFP CTM
does not require any meshing within the cuboid that
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7-9 October 2009, Leuven, Belgium
represents the CTM. It can be imagined to be a black box
IV. RESULTS AND DISCUSSIONS
with four nodes on each side and the remaining five nodes to The three cases are simulated with the detailed SFP
be inside. In order to ensure that the environment does model. This is followed by deactivating the detailed SFP
not change between the SFP CTM and the detailed SFP model and simulating the cases with the SFP CTM activated.
model, the same mesh is used for the SFP CTM. The
No parameter is changed between the two simulations. All
number of nodes inside the SFP CTM is not changed at all
simulations are initialized to an ambient temperature of
even though it can be significantly reduced.
20˚C. The predicted junction temperatures and heat flows are
In order to do this, the SFP CTM is included in the obtained using ‘Tables’, a Flotherm feature. Results for each
same “Assembly” in Flotherm and is placed at the exact of the cases are discussed below.
location of the detailed SFP. By doing this the detailed
model can either be activated or deactivated. This feature is
shown in Figs. 10a and b. In Flotherm, when a model is A. Case 1- Natural Convection
deactivated, although the object is removed from
computations, the mesh does not change. By taking
advantage of this feature, it is ensured that there is no change
in external parameters for both the detailed SFP model and
the SFP CTM.
Junction temperature and heat flow through the sides
are compared between the detailed and compact models of
the SFP in Table 1. As seen from this table, the SFP CTM
predicts the junction temperature for the active components
and heat flow through the sides with a relative error of less
than 2% of the results predicted by the detailed SFP model.
TABLE I
COMPARISON OF RESULTS PREDICTED BY SFP CTM AND SFP DETAILED MODEL FOR SIMULATION
OF NATURAL CONVECTION
Junction Temperature
(˚C) CTM Detailed Error %
Laser Diode 30.8 31.0 0.7
TIA 128.9 129.9 0.8
Laser Driver 32.4 32.1 -0.8
Post Amp IC 39 38.7 -0.9
Heat Flow (W)
Top 0.0450 0.0454 0.8
Bottom 0.4520 0.4494 -0.6
Left 0.0285 0.0288 1.1
Right 0.0151 0.0150 -0.6
(a) Detailed Model Deactivated
(b) SFP CTM Deactivated
Fig. 10 Screenshot of Flotherm showing Activation and Deactivation of
Models
The complete set of Navier Stokes equations are solved
with second order accuracy.
The natural convection cases are done with a laminar
model as the Rayleigh Number for the flow is 3.3e5. The
forced convection cases are solved with the K-Epsilon
turbulence model available in Flotherm. Radiative heat
exchange is considered only between the surfaces of the SFP
models to the ambient. None of the other surfaces (duct wall,
bezel and PCB) participate in the radiation heat transfer.
Modeling radiation in these components has minimal effect
on the validation process and avoiding it significantly
reduces the time consumed in solving the problem. Multigrid
double precision solver is used for solving the
equations. When the SFP CTM is activated instead of the
detailed model, though the number of grid cells within the
SFP CTM is large, the solver considers only conduction
between the 9 nodes used to represent the SFP CTM.
Apart from the above results, an analysis of the flow and
temperature fields is necessary because of the close coupling
between the two in the case of natural convection. The plots
show that the error from the SFP CTM is significantly low.
The temperature field and velocity field is compared at a
plane passing through the middle of the SFP. This plane is
shown in Fig. 11.
Plane
Fig. 11 Plane at which the Flow and Temperature Fields are analyzed
The flow field is compared in Fig. 12. Figure 12a shows
the velocity vectors plotted for the detailed SFP model and
Fig. 12b shows the velocity vectors plotted for the SFP
CTM. A comparison shows that the flow field predicted by
the detailed SFP model and the SFP CTM is identical. A
comparison of the temperature field from Figs. 13a and b
shows that the maximum temperature in the plane is 31.5˚C
for the detailed model while it is 32.4˚C in the case of the
SFP CTM. The error in prediction of the surrounding flow
and temperature field by the compact model is almost
©EDA Publishing/THERMINIC 2009 26
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negligible.
7-9 October 2009, Leuven, Belgium
detailed model is simulated first by keeping the SFP CTM
deactivated. The junction temperature of the components and
the heat flow through the sides are noted. The detailed model
is deactivated now and the SFP CTM is activated. The results
are recorded, and compared in Table 2. The table shows that
the maximum error occurs in the junction temperature which is
about 1.5 % deviant from the results predicted by the detailed
model.
TABLE II
COMPARISON OF RESULTS PREDICTED BY SFP CTM AND SFP DETAILED MODEL FOR SIMULATION OF
NATURAL CONVECTION WITH SFP HEATSINK
(a) Detailed SFP Model
(a) SFP CTM
Fig. 12 Comparison of Flow Fields Predicted by the Detailed and Compact
Models for Simulation of Natural Convection
Junction
Temperatures (˚C)
CTM
Detailed
Model
Error
%
Laser Diode 29.9 30.3 1.1
TIA 128.1 129.1 0.8
Laser Driver 31.6 31.4 -0.4
Post Amp IC 38.2 37.9 -0.8
Heat Flow (W)
Top 0.1080 0.1084 0.4
Bottom 0.4000 0.3998 -0.1
Left 0.0212 0.0214 1.3
Right 0.0102 0.0101 -0.7
For this case, the flow and temperature fields are compared at a
plane passing through the middle of the heatsink. The location
of the plane is shown in Fig.14
Plane
Fig. 14 Plane at which the Flow and Temperature Fields are analyzed for SFP
with Heatsink
(a) Detailed SFP Model
Figs. 15a and b compare the flow fields on the plane passing
through the middle of the SFP heatsink. The figures show that
the detailed model predicts a slightly higher maximum velocity
(0.132 m/s) than the maximum velocity predicted by the
compact model (0.127 m/s). The error is about 4%. Figs.16a
and b compare the temperature fields on the same plane for the
detailed and compact SFP models. There is a maximum of 1%
relative error seen in the temperature field predicted by the SFP
CTM.
(b) SFP CTM
Fig. 13 Comparison of Temperature Fields Predicted by the Detailed and
Compact Models for Simulation of Natural Convection
B. Case 2- Natural Convection with Heat Sink
In this case, the SFP was fitted with a heatsink on its
top surface. This increases the heat flow through the top. The
(a) Detailed SFP Model
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7-9 October 2009, Leuven, Belgium
and compact model for velocities of 0.5, 1, 2, 3 and 4 m/s
respectively. In Table 3, the maximum error of 6.3% occurs
on the heat flow prediction only when the SFP model is
exposed to a low forced convection environment of 0.5 m/s.
In all other cases, the maximum error is less than 4% on the
heat flow prediction. The junction temperatures are
predicted with errors less than 2%. Detailed analysis of flow
and temperature fields is not necessary as small variations in
temperature do not change the flow field prediction in forced
convection environments.
(b) SFP CTM
Fig. 15 Comparison of Flow Fields Predicted by the Detailed and Compact
Models for Simulation of Natural Convection with SFP Heatsink
TABLE III
COMPARISON OF RESULTS FOR FIXED FLOW VELOCITY OF 0.5 M/S
Junction
Temperatures (˚C)
CTM
Detailed
Model
Error
%
Laser Diode 26.7 27.1 1.5
TIA 124.8 126.0 0.9
Laser Driver 28.3 28.2 -0.5
Post Amp IC 35.0 34.7 -0.8
Heat Flow (W)
Top 0.0560 0.0568 1.4
Bottom 0.4232 0.4182 -1.2
Left 0.0469 0.0485 3.2
Right 0.0145 0.0137 -6.3
(a) Detailed SFP Model
(b) SFP CTM
Fig. 16 Comparison of Temperature Fields Predicted by the Detailed and
Compact Models for Simulation of Natural Convection with SFP Heat Sink
TABLE IV
COMPARISON OF RESULTS FOR FIXED FLOW VELOCITY OF 1 M/S
Junction
Temperatures (˚C)
CTM
Detailed
Model
Error
%
Laser Diode 25.7 26.0 1.3
TIA 123.8 124.9 0.9
Laser Driver 27.3 27.1 -0.7
Post Amp IC 33.95 33.7 -0.7
Heat Flow (W)
Top 0.0579 0.0589 1.7
Bottom 0.4085 0.4027 -1.4
Left 0.0560 0.0581 3.7
Right 0.0183 0.0182 -0.6
C. Case 3- Forced Convection
The detailed SFP model is now placed inside the duct
with a fixed flow inlet. Flow inlet velocities of 0.5, 1, 2, 3
and 4 m/s are simulated and the data is recorded. After
replacing the detailed model with the SFP CTM, the flow is
simulated for the four velocities. The data between the SFP
CTM and the detailed model is tabulated for each flow
velocity. The flow pattern causes impingement on the left
face of the SFP, recirculation on the right face of the SFP,
and separating flow over the top face of the SFP. The
convective heat transfer coefficient varies considerably from
one point to another point on the surface of the SFP on all
sides. Tables 3 through 7 show the comparison of the
junction temperature and heat flow predicted by the detailed
TABLE V
COMPARISON OF RESULTS FOR FIXED FLOW VELOCITY OF 2 M/S
Junction
Temperatures (˚C)
CTM
Detailed
Model
Error
%
Laser Diode 24.9 25.2 1.3
TIA 123.0 124.1 0.9
Laser Driver 26.5 26.3 -0.8
Post Amp IC 33.2 32.8 -1.1
Heat Flow (W)
Top 0.0664 0.0677 2.0
Bottom 0.3829 0.3763 -1.8
Left 0.0672 0.0695 3.3
Right 0.0243 0.0248 1.9
©EDA Publishing/THERMINIC 2009 28
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TABLE VI
COMPARISON OF RESULTS FOR FIXED FLOW VELOCITY OF 3 M/S
Junction
Temperatures (˚C)
CTM
Detailed
Model
Error
%
Laser Diode 24.5 24.8 1.3
TIA 122.6 123.7 0.9
Laser Driver 26.1 25.9 -0.9
Post Amp IC 32.8 32.4 -1.1
Heat Flow (W)
Top 0.0733 0.0749 2.2
Bottom 0.3638 0.3567 -2.0
Left 0.0734 0.0756 2.9
Right 0.0303 0.0312 2.9
TABLE VII
COMPARISON OF RESULTS FOR FIXED FLOW VELOCITY OF 4 M/S
Junction
Temperatures (˚C)
CTM
Detailed
Model
Error
%
Laser Diode 24.3 24.6 1.4
TIA 122.4 123.5 0.9
Laser Driver 25.9 25.7 -0.8
Post Amp IC 32.5 32.2 -1.1
Heat Flow (W)
Top 0.0834 0.0848 1.6
Bottom 0.3445 0.3377 -2.0
Left 0.0777 0.0798 2.6
Right 0.0351 0.0363 3.1
7-9 October 2009, Leuven, Belgium
of the current research. One of the limitations of the
methodology is the trial and error method used for laying out
the network topology. Although many different network
topologies were experimented, the network topology
suggested for the SFP CTM in the current work does not
have to be the final best network possible. There can be any
other types of network topologies, especially ones that have
multiple internal nodes, which can provide better redirection
of heat flow. The CTM is obtained through the
optimization of the cost function. It was found that the CTM
obtained was sensitive to initial start values of the resistors,
the upper and lower bounds on the resistors and the error
constraints. The authors realize that some of these limitations
can be overcome using the commercial code
DOTCOMP[23] which will be a subject for later study.
VI.
CONCLUSION
The CTM for the SFP has been generated using the
DELPHI Methodology. It has been validated up to the point
of end-user usage, which is usage in CFD codes for thermal
design and analysis in practical applications. The SFP CTM
is validated in real-time situations such as natural
convection, natural convection with heat sink fitted on the
SFP and forced convection for different velocities. In all
cases the SFP CTM predicted the junction temperature of all
its four active components with relative error of less than
10%. The errors on the heat flows through the sides were
also less than 10%. Thus, the SFP CTM can be used in
detailed system-level models for accurate prediction with a
large reduction in computational resources.
V. ADVANTAGES AND LIMITATIONS OF
GENERATING CTM FOR SFP BY DELPHI
METHODOLOGY
From the results, the DELPHI approach to generate CTMs
for SFP has proved to be very successful. This study shows
the obvious advantage of the DELPHI methodology – the
CTM for the SFP can be readily implemented for thermal
design and analysis of systems that use SFPs. Apart from
this, the results have shown that CTMs can be generated for
SFPs and SFP-like packages which have multiple-heat
sources using the DELPHI methodology. Also, the
methodology allows for better thermal characterization of
the SFP package by identifying junction temperatures as an
important quantity (as opposed to specifying case
temperatures of SFPs). The DELPHI-type CTM for the
SFP allows representation of the component using nine
nodes instead of hundreds of thousands of grid cells greatly
simplifying CFD-based computations to a matter of seconds
than hours. This type of reduction also allows accurate
analysis of system-level models that employ a huge number
of SFPs. Also, the CTM generated by this method is highly
portable; CTMs can be distributed in the form of library
models in CFD-based software such as Icepak and Flotherm.
Although there are significant advantages of the
application of DELPHI methodology to generate CTM for
the SFP, some limitations were identified during the course
ACKNOWLEDGMENT
The authors acknowledge the support of Electronic
Cooling Solutions and the Desktop Switching Business Unit
of Cisco Systems, California, for funding of this research.
The authors are grateful for the support of David
Meadowcroft and Ron Kaneshiro of Avago Technologies,
California, for providing enthusiastic support of the overall
research and more specifically with the experimental section.
The authors also acknowledge the assistance of Dr. Sarang
Shidore of Mentor Graphics in modeling the compact
thermal model in Flotherm.
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Diego, CA, pp. 189–200, 1999.
©EDA Publishing/THERMINIC 2009 30
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7-9 October 2009, Leuven, Belgium
Spatial and temporal temperature variations in CMOS
designs
J.H.J.Janssen
NXP Semiconductors
Gerstweg 2, 6534AE Nijmegen The Netherlands
H.J.M.Veendrick
NXP Semiconductors
HTC-32, 5656AE Eindhoven The Netherlands
Abstract
Due to the rapid growth in the number of transistors per
chip, the power consumption of the average nMOS ASIC
reached the level of one Watt, which is, in order of magnitude,
about the maximum power consumption allowed for a cheap
plastic package without thermal enhancements like drop-in
heat spreader, fused leads or exposed pads. The internal chip
temperature is the result of the combination of the chip power,
the package, a possible heatsink, the application board and the
airflow conditions. This requires a reasonably accurate model
that includes the thermal properties of the chip, the bonds, the
package and the system.
I. INTRODUCTION
The average power consumption of integrated circuits has
been steadily increasing since they have been introduced
about five decades ago. Until the early eighties, nMOS
technology was the most dominant VLSI technology. Logic
gates, then, were built from an nMOS transistor pull-down
circuit representing the logic function in combination with a
single nMOS load transistor, keeping the output high, when
the pull-down circuit was off. This logic had a major
disadvantage in that every logic gate whose output was zero,
meaning that the pull-down circuit was on, consumed static
power as long as this logic zero state was maintained. On the
average this means that half the number of logic gates was
continuously consuming static power, which was about an
order of magnitude more than the switching power. Due to
the rapid growth in the number of transistors per chip, the
power consumption of the average nMOS ASIC reached the
level of one Watt, which is, in order of magnitude, about the
maximum power consumption allowed for a cheap plastic
package without thermal enhancements like drop-in heat
spreader, fused leads or exposed pads. This forced the drive
from nMOS to CMOS technology and circuits in the early
80ies. Due to the absence of simultaneous conduction of the
nMOS and pMOS transistors in a CMOS logic gate, these
did not show any static power consumption. Therefore, an
average CMOS chip, at that time, consumed about a factor
of ten to twenty less than its nMOS counterpart. However,
today, about 25 years later, the average CMOS chip has
reached this package-limited power level of one Watt again,
but with no alternative technology solution. As a result, a
“less power” attitude is a must at all hierarchy levels of
design. Even when that is the case, the average power
consumption of an integrated circuit is still expected to
continuously increase.
Variability is another point of concern. Spatial variations
are variations due to the fact that identical devices have a
different physical position and environment. This variations
may cause a different behaviour of identical transistors due
to a variation in the channel doping level, a different
orientation, a temperature gradient across the chip, a
different metal coverage or other proximity effects, such as
mechanical stress (e.g., STI stress), the position of a well in
the vicinity of a transistor (well-proximity effect), and/or
pattern shape deviations as a result of imperfect lithographic
imaging and pattern density variations.
Time-based variations include signal integrity effects,
such as cross talk, supply noise, ground bounce, and iR-drop,
but also temperature variations over time, due to variations
in workload.
From the above we see that the temperature contributes to
both spatial and time-based variations. This combined with
the increasing power consumption leads to the idea that the
momentary temperature gradient across the chip can vary a
lot with the workload. This may cause circuits in certain
regions on the chip to slow down at a different rate then
others, which will certainly make the performance of a
digital circuit less predictable, and the timing closure more
complex.
In addition to this, steep and large temperature gradients
(hot spots) may also cause physical stress or may cause the
local temperature to exceed the maximum specified
temperature.
To really visualise the overall impact of the power
distribution across a chip, we first need to make the
transition from power distribution to temperature distribution
and then discuss the influence of the temperature on the
speed of the circuit. Temperature distributions are simulated
©EDA Publishing/THERMINIC 2009 31
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7-9 October 2009, Leuven, Belgium
using a compact model of the total physical structure of a
packaged die, including heat spreader.
II. FROM POWER DISTRIBUTION TO TEMPERATURE
DISTRIBUTION
Even when the power distribution across an SoC is
accurately known, the temperature distribution can still be
very different, depending on the thermal behaviour of the
package and the thermal design of the application. This
requires a reasonably accurate model that includes the
thermal properties of the chip, the bonds, the package and
the system. One way to achieve this is to use Compact
Thermal Models (CTM), simple board simulation tools like
COMIC and a Finite Elements (FE) program [1]. CTM’s are
widely used for predicting the maximum junction
temperatures. However, temperature gradients do not belong
to its predicting capability. In order to get to know the
temperature gradient across the die, first a CTM must be
derived. Next the CTM will be used in combination with
COMIC to predict the thermal behaviour of the product in a
simplified application. One of the calculation results is the
effective Heat Transfer Coefficient (HTC) which is working
on the ‘thermal’ contacts of the package with the application
PCB. Next, these HTC’s will be used as thermal boundary
conditions in the FE program. Since the FE model of the
package contains a detailed description of the floorplan of
the IC an accurate prediction of the temperature can be
achieved.
The chip used for case study
Many thermal simulations on integrated circuits are
performed on complex and high-speed processors,
consuming between 50W to a 100W [2, 3]. In [2], the total
temperature variation across the chip at a maximum power
consumption of P total =32.3W is: ΔT=31.3 0 C, with a
minimum temperature of T min =106.1 0 C and a maximum of
T max =137.4 0 C. This minimum and maximum temperature
values, as well as the chip locations where these occur, are
very much dependent on the floorplan of the chip and of the
applied package.
For our research, we use an advanced video and graphics
processor chip used in very advanced digital TV sets. Figure
1 shows the power distribution, based on the physical
position of the processor, controller, memory and interface
cores, when all cores are operating at maximum
performance.
low-performance interfaces
low-performance interfaces
U3
0.8W
U4
0.515W
U2
0.294W 2.94W
U8
0.83W
DDR interface
U1
1.11W
U5
0.21W U6
0.26W
low-performance interfaces
U7
2.02W
Fig. 1. Original floorplan and power distribution during full operation of all
IP cores.
The die would be mounted into a HBGA 40 x 40 mm
package, including a copper drop-in heat spreader. Figure 2
shows a cross section of the total physical structure that has
been included in the model for simulations.
Fig. 2. Physical structure that has been included in the model for
simulations.
DDR interface
Low-Performance
interfaces
Next, the above floorplan, together with the power
numbers were also fed into the finite elements model and
simulated. The goal of the simulations is twofold. First it is
important to predict the overall temperature distribution
across the die and check whether, at some local spot, it
would exceed the maximum specified temperature of 125 0 C.
Second, a large temperature variation may have severe
©EDA Publishing/THERMINIC 2009 32
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impact on the mechanical stress within and in between the
various compounds of the packaged die.
Figure 3 shows the resulting temperature map, with a
maximum temperature of 125 0 C in the right upper corner
and a maximum temperature gradient of 23 0 C
7-9 October 2009, Leuven, Belgium
Figure 5 shows the new temperature map as a result of the
simulation for the new floorplan.
Fig. 5. Temperature map of the die with the new floorplan.
Fig, 3. Temperature map of the die from the FE model temperature
simulations for the die glued in a BGA 40 x 40 mm package, including an
internal copper heat spreader and an external heat sink on top of the
package.
This gradient was considered as too high for the
application, particularly for the introduced mechanical stress.
Therefore the floorplan was changed in such a way that the
most intensive power consuming blocks were more evenly
distributed over the die, with the aim to reduce the gradient
to a level of 10 0 C max, set by the chip architect. The final
floorplan is shown in figure 4.
Although the maximum temperature of 1250C still
remains, the map clearly shows that the maximum
temperature variation over the die is limited to only 5.3
degrees, which is even less than required from the
application.
The following section shows that in a 45nm CMOS
technology, the temperature variation across the die has
much less influence on the performance than in conventional
technologies.
III. FROM TEMPERATURE TO PERFORMANCE
An increase in the operating temperature of a MOS
transistor affects its behaviour in two different ways:
1. The mobility of the majority carriers, e.g., electrons in
an nMOS transistor, in the channel decreases. Consequently,
since the transistor gain factor β□ = μ.C ox , also β□ decreases.
Its temperature dependence can be estimated with [4, 7]:
β□(Temp) = β□(298 K) x (298/Temp) 3/2 (1)
The exponent 3/2 in this expression is more applicable to
the electron mobility. For holes this exponent is closer to 1.
PMOS transistor currents are therefore less temperature
dependent than those of nMOS transistors.
2. The threshold voltage V T of both nMOS and pMOS
transistors decreases slightly. The magnitude of the influence
of temperature change on threshold voltage variation V T
depends on the substrate doping level. A variation of
-0.7mV/ 0 C is quite typical.
Both effects have different consequences for the speed of
an IC. This speed is determined by the delay τ of a logic
gate, which is defined as:
Fig. 4. Final floorplan and power distribution during full operation of all IP.
Cores.
τ = CV/I = 2CV/(β(V gs -V T ) 2 (2)
©EDA Publishing/THERMINIC 2009 33
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7-9 October 2009, Leuven, Belgium
supply voltage of 1.2V in this technology, the frequency
In conventional CMOS processes the overall circuit reduces with increasing temperature, while below this voltage
performance reduces dramatically with increasing the effect is opposite. For the same ring oscillator fabricated
temperatures, because the effect of the mobility reduction in with a standard V T , this ZTC is reduced to 0.95 V.
the transistor current, represented by β□, was traditionally As a result of this varying temperature behaviour, the worstcase
and best-case corners for simulation need to be
much larger than the effect of the reduction of the threshold
voltage V T . This was one of the reasons to keep high-speed reconsidered, since for modern CMOS technologies a higher
processors cool, by using a fan. Also worst-case corner temperature not automatically corresponds to a lower
simulations were usually done at high temperatures. performance! For the 45nm technology node and beyond, the
However, today's CMOS technologies offer several different temperature effect will diminish further, because of an
threshold voltages to support both high-speed and lowleakage
increasing compensation of the β□ and V T contributions to the
applications. For general-purpose and high-speed transistor current [8].
processes, V T is relatively low and a further reduction with ZTC also has consequences for certain failure analysis methods
0.7mV/ 0 C has less influence on this speed than the reduction that use local heating to detect changes in circuit behaviour,
in the β□.
because these changes will become smaller and less visible in
For low-leakage processes, with a relatively large V T , both modern technologies [9].
effects partly compensate each other, because of the From the above it is clear that thermal simulations on ICs in
increasing competition between mobility and threshold advanced CMOS technologies are very important to verify
voltage, so that there is a reduced influence on the speed. At whether the maximum temperature does not exceed the
a certain supply voltage the above two mechanisms fully specified temperature, and that the temperature variations
cancel each others contribution to the transistor current, such across the die remain limited to avoid potential mechanical
that the circuit speed has no longer a relation with the stress in and between the all physical compounds of the
temperature. This is the so-called zero-temperaturecoefficient
package mounted on a board. However, thermal simulations
(ZTC) voltage [5]. This reducing temperature have become less important for the prediction of the
dependence, which is expected to continue with further performance variations across the die, due to the weaker impact
scaling of the supply voltage, has serious consequences for of the temperature on the current behaviour of the individual
the static timing analysis, as it may invalidate the approach transistors.
of defining PVT (process, voltage and temperature) corners,
by independently varying voltage and temperature [6].
Figure 2 shows the frequency response of a high-V T ring
oscillator as a function of the supply voltage, for different
operating temperatures [7].
Fig. 2. Ring oscillator frequency responses as a function of the supply
voltage at different temperatures.
Above the ZTC voltage of 1.1 V, which is close to the nominal
IV. CONCLUSIONS
On-chip temperature variations had a relatively large impact on
the performance of the various cores on a die in conventional
CMOS technologies. In an advanced 45nm CMOS technology,
however, the relation between the temperature and the
performance is much weaker, because the reduction in
mobility, due to a higher temperature, is greatly compensated
by a reduction in the threshold voltage. However, prediction of
the absolute temperature is still important to meet the
specification requirements of the application. Next to that, it is
also important to limit the temperature variations across the
mounted die in order to reduce mechanical stress.
Therefore, extensive thermal simulations have been performed
for a complex video and graphics processing chip made for
digital TV applications. The target was to create an overall
temperature distribution diagram across the die, based on an
accurate compact model that includes all compounds from dieto-package-to-board.
The first floorplan of the chip showed a
temperature distribution in which the temperature variations
were too large for the targeted application area. This has led to
a change in the floorplan of the cores on the die. The final
floorplan resulted in a maximum temperature variation over the
die of 5 0 C, compared to the variation of 23 0 C of the original
floorplan.
©EDA Publishing/THERMINIC 2009 34
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7-9 October 2009, Leuven, Belgium
REFERENCES
[1] H. Pape, et al., “Thermal Transient Modeling and Experimental
Validation in the European Project PROFIT”, IEEE transactions on
Components and Packaging Technologies, Vol. 27, No 3,
September 2004
[2] Peng Li, et al., “Efficient Full-Chip Thermal Modeling and
Analysis” IEEE/ACM International Conference on Computer Aided
Design (ICCAD-2004), 2004
[3] T. Sato, et al., “On-Chip Thermal Gradient Analysis Considering
Interdependence between Leakage Power and Temperature”, IEICE
Trans, Fundamentals, Vol.E89-A, No 12 Dec. 2006
[4] R.S.C. Cobbold, `Theory and applications of field effect transistors',
John Wiley & Sons, Inc. New York
[5] I.M. Filanovsky, A. Allam, “Mutual Compensation of Mobility and
Threshold Voltage Temperature effects with Applications in CMOS
Circuits”, IEEE Transactions on Circuits and Systems:
Fundamental Theory and Applications, vol.48, no.7, pp. 876-884,
July 2001
[6] A. Dasnan, et al., “ Handling Inverted Temperature Dependence in
Static Timing Analysis”, ACM Transactions on Design
Automationof Electronic Systems, Vol. 11, No. 2, April 2006, pp.
306-324
[7] H.Veendrick, “Nanometer CMOS ICs, from Basics to ASICs”,
Springer, 2008, ISBN 978-1-4020-8332-7, pp. 71-73
[8] R. Kumar, et al., “Reversed Temperature-Dependent Propagation
Delay Characteristics in Nanometer CMOS Circuits”, IEEE
Transactions on Circuits and Systems-II: Express Briefs, Vol. 11,
No.2, April 2006, pp. 1078-1082
[9] E. Long, et al. “Detection of Temperature Sensitive Defects Using
ZTC”, Proceedings of 22nd IEEE VLSI Test Symposium (VTS
2004)
©EDA Publishing/THERMINIC 2009 35
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7-9 October 2009, Leuven, Belgium
Numerical Simulation of
Complex Submicron Devices with
Experimentally Determined Power Maps
Peter E. RAAD*, Mihai G. BURZO, and Pavel L. KOMAROV
IEEE Conference Publishing
Southern Methodist University and TMX Scientific,
5232 Tennyson Pkwy, Bldg. 2, Plano, TX 75024, U.S.A.
Abstract – Both computational and experimental methods
play a key role in thermal characterization, particularly in
prototyping and design with each having their own set of
strengths and weakness. In this work the authors demonstrate
that simulation methods can provide temperature information
in three spatial dimensions and in critical regions that are
inaccessible to measurement tools. Combining the
complementary tools of experimentation and simulation can
leverage their respective strengths and create a coupled
approach that is vastly more powerful than either tool alone.
I. INTRODUCTION
As electronic devices have shrunk, become more complex,
and experienced significant increases in local power
densities, their cooling problems have grown, to the point
that many now wonder whether Moore’s law is still
applicable. Irrespectively, heat extraction remains a serious
impediment in the continuing evolution of electronic
devices. Given society’s insatiable appetite for electronic
processing, effective solutions to the unavoidable thermal
issues are needed, which requires significant improvements
in our knowledge of the actual temperature distributions
within devices. Specifically, direct knowledge of thermal
behavior is pivotal to efforts to improve analysis and design,
shorten design cycle time, assess reliability, and diagnose
defects. However, the same culprits that have accentuated
the thermal issues – device complexity and shrinking feature
sizes – make realistic computations a challenging pursuit.
The difficult issue is associated with having to resolve
numerically the wide range of scales that characterize
microelectronic devices.
A. Numerical Simulation of Submicron Complex Devices
The authors have developed a transient, ultra-fast, selfadaptive
method that is capable of accurately and efficiently
solving thermal transient problems that are characterized by
a large range of spatial and temporal scales as well as
geometric and material complexities [1, 2]. In this approach,
it is the physics that dictate the grid’s size and concentration,
and as a result, significant advantages can be achieved over
existing methods, including independence from user
expertise in meshing, the ability to handle disparate materials
and geometric features, the elimination of the need to
perform time prohibitive convergence studies as well as
lower CPU speed and memory required.
In this paper, we begin by comparing the ultra-fast, selfadaptive
computational method against a commercially
available computational tool (ANSYS Fluent). A simple
heat transfer problem was chosen and computed with both
solvers so that the temperature results may be easily
compared side by side. We chose a simple representative
problem for the purposes of highlighting the accuracy and
speed of our method.
However, we next tackle a more difficult aspect of
modeling a thermal problem, which is in determining the
actual power map distribution in a device, since that
distribution is not a property of the device, but is rather a
result of the electrical flow fields that develop during
operation, and is even subject to change with the normal or
aging processes of a device. Therefore, we present an
approach for determining the actual power distribution
within the device by measuring experimentally its thermal
map with a thermal reflectance thermography system [3].
The experimentally determined thermal power distribution is
then used to simulate the behavior of the actual rather than
the theoretical device. The benefit of combining the
numerical and experimental approaches [4, 5] is that the
resulting transient three-dimensional thermal field reflects
the true behavior of the device.
B. Validation of the Numerical Method: Comparison to
ANSYS Fluent Results
The temperature results of the numerical solver used in the
present work are compared with the results of the
commercially available ANSYS Fluent solver. A simplified
version of the pyramid problem solved by Shakouri et al. [6]
and Raad et al. [7] was chosen. The problem considered here
consists of cooling a Silicon block with a single embedded
heat source that sits on top of a Copper heat sink. The
geometry of the structure is as follows: the Copper block is
2.8 by 2.8 mm wide and 1.8mm tall and centered below a
Silicon block 1 mm by 1mm wide and 0.5 mm tall.
The bottom of the Copper block is considered to be the
heat sink and thus isothermal conditions are specified for it,
©EDA Publishing/THERMINIC 2009 36
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7-9 October 2009, Leuven, Belgium
Fig. 1 SMU solver temperature results: a temperature contour slice
through the middle of the heat source is shown
while the heat transfer to the air is neglected and thus the rest
of the exterior walls were considered adiabatic. A 2.5W heat
source was placed in the center of the Silicon block. The
dimensions of the heat source are 10 x 5 x 50 µm. The
importance of the chosen geometry is that the solver has to
deal with over four orders of magnitude changes in scales.
The results of the steady-state simulation obtained using
the self-adaptive ultra-fast (SAUF) solver
are shown in Fig.
1 while the results obtained from the Fluent package are
shown in Fig. 2. The results are presented as temperature
contours on a vertical plane (YZ plane) that cuts through the
entire domain and passes through the middle of the heat
source. The temperature contours on the external surfaces of
the heat source are also shown in Figs. 1 and 2. Given a
prescribed accuracy level of 1%, the SAUF solver took 6
seconds to complete the solution whereas the ANSYS solver
took 370 seconds and an order of magnitude more memory
usage.
Fig. 2 ANSYS Fluent solver
temperature results: a temperature
contour slice through the middle of the heat source is shown
C. 3D Thermal Characterization: Combining the
Experimental and Numerical Results
The problem considered here is structurally and materially
complex, and is made of 12-finger MOSFETs with a channel
length of 100 µm and width of 1 µm. The widths of active
regions in state-of-the-art devices are significantly smaller
than those of the present device. The advantage in using this
device, however, is that the numerically simulated behavior
could be compared with measured data. But even more
interestingly, this device provides an opportunity to
demonstrate how input problem parameters can be adjusted
to more closely reflect the actual operation of a device.
The main features of the transistors can be seen in the top
view picture of Fig. 3. The main grey stem with 12 branches
running down the center of
the device is the poly-silicon
gate, while the brightest color is the Aluminum (Al) surface
Fig. 3 Top view of 12-finger MOSFET
(100×1 µm)
Fig. 4 Horizontal and vertical planes showing numerically-simulated
3D temperature fields, assuming total power is equally divided
among the
12 fingers
©EDA Publishing/THERMINIC 2009 37
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7-9 October 2009, Leuven, Belgium
self-adaptive method provided a steady-state solution of the
three-dimensional device within 13 CPU seconds, fully
converged within the prescribed accuracy level of 1%.
Contour plots of the thermal behavior are presented in Fig. 4
on three representative planes: the horizontal plane sits on
top of the poly-silicon, while
the two vertical planes bisect
each of the two banks of six transistors.
The non-symmetry in the construction of the device,
apparent in Fig. 3, can be determined and was thus
accounted for in the input to the numerical simulation.
Variations in material properties can also be measured in situ
for a given design of a device [8]. More difficult to
determine independently is the actual power distribution
within a device since that distribution is not a property of the
device, but is rather a result of the electrical flow fields that
develop during operation, and
is even subject to change with
either the normal or unexpected aging processes of a device.
Indeed, the surface temperature distribution for the present
device, measured experimentally with a thermal reflectance
thermography system (T°Imager [9]) indicates that the
power generation is not the same for all 12 channels (Fig. 5).
Fig. 5 Thermal image of 12 hot channel regions obtained
For the purposes of this investigation, only the gate regions
with T°Imager indicates that power distribution is nonuniform
were mapped; the (blue) areas outside of the channel regions
of interest were not calibrated or used. Given the measured
metallization used to activate the common sources and temperature field, an averagee temperature was obtained for
drains through the circular vias; the latter are more visible on each channel, reflecting a maximum variation of 20% from
the top fingers than on the lower ones. The devices are the coolest to the hottest. Since to a first approximation the
fabricated on a silicon wafer with 300 Å of silicon-
oxide (SiO2), experimentally determined average temperatures make it
power is proportional to the average temperature, the
germanium (SiGe), then 100 Å of gate silicon
then 500 Å of poly-silicon, and finally 1500 Å of field oxide. possible to verify the actual power levels dissipated by each
Hence, the first visible interface under the
transparent oxide of the 12 fingers. Therefore, the power levels of the sources
layer in the channel region is the poly-siliconknowledge of the construction of the device and its material simulation was repeated.
With the in the simulation were adjusted accordingly and the
properties the self-adaptive approach was used to simulate The results of the simulation with the adjusted power
the thermal behavior of the device. The total power was distribution are displayed in Fig. 6. The differences in the
determined from a direct measurement of an activated
device and then divided equally among the 12 gates. The
Fig. 6 Temperature contours showing the effect of adjusting
the individual power of the 12 fingers according to
the observed temperature measurements
Fig. 7 Effect of adjusting
power map of the transistors
according to the measured temperature field
©EDA Publishing/THERMINIC 2009 38
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temperature field from channel to channel are visible in Fig.
6 as well as in comparison with the results of Fig. 4.
For a closer inspection of the effects of altering the power
distribution, the temperature profiles along cuts B-B in Fig. 4
and C-C in Fig. 6 are compared in the upper part of Fig. 7.
The percent difference plotted in the lower half of the figure
shows that two channels experience a net increase in
temperature while another two experience a net decrease. At
first, one might expect that the magnitude of the change in
the temperature should correspond to that of the power, but
heat dissipation is three-dimensional and as the temperature
rises in one channel, the increased local heat flux tends to
raise the temperature of the adjacent channels. The threedimensional
nature of the heat diffusion is evident, for
example, by the widening of the temperature curves of the
second and third channel.
C. Conclusions
Experimental methods are important and necessary means
for obtaining temperature fields. Computational methods are
also important and can play a key role in thermal
characterization, particularly in prototyping and design. As
demonstrated in this work, novel simulation methods can
provide temperature information in three spatial dimensions
and in critical regions that are inaccessible to measurement
tools. By combining the complementary tools of simulation
and experimentation, one can leverage their respective
strengths and create a coupled approach that is vastly more
powerful than either tool alone.
7-9 October 2009, Leuven, Belgium
REFERENCES
[1] P. E. Raad, J. S. Wilson, and D. C. Price, “System and Method for
Predicting the Behavior of a Component,” U.S. Patent No.
6,064,810 (2000), Korean Patent No. 0501053 (2005), Japanese
Patent No. 3,841,833 (2006).
[2] J. S. Wilson and P. E. Raad, “A Transient Self-Adaptive Technique
for Modeling Thermal Problems with Large Variations in Physical
Scales,” International Journal of Heat and Mass Transfer, Vol. 47,
pp. 3707-3720, 2004.
[3] P. L. Komarov, M. G. Burzo, and P. E. Raad, “A Thermoreflectance
Thermography System for Measuring the Transient Surface
Temperature Field of Activated Electronic Device,” Proceedings to
the 22nd Semiconductor Thermal Measurement, Modeling, and
Management Symposium (SEMITHERM), Dallas, Texas, March 14-
16, 2006.
[4] P. E. Raad, P. L. Komarov, and M. G. Burzo, “Non-Contact Surface
Temperature Measurements Coupled with Ultrafast Real-Time
Computation,” Proc. Proceedings to the 23rd Semiconductor
Thermal Measurement, Modeling, and Management Symposium
(SEMITHERM), San Jose, CA (2007) pp. 57-63.
[5] P. E. Raad, P. L. Komarov, and M. G. Burzo, “Thermal
Characterization of Embedded Electronic Features by an Integrated
System of CCD Thermography and Self-Adaptive Numerical
Modeling,” Microelectronics Journal, v. 39, pp. 1008-1015, 2008.
[6] J.-H. Park, X. Wang, A. Shakouri, and S.-M. Kang, “Fast
Computation of Temperature Profiles of VLSI ICs with High
Spatial Resolution,” Proceedings to the 24th Semiconductor
Thermal Measurement, Modeling, and Management Symposium
(SEMITHERM), San Jose, CA, pp. 50-54, 2008
[7] P. E. Raad, P. L. Komarov, and M. G. Burzo, “Numerical
Simulation of Complex Submicron Devices,” Electronics Cooling,
Vol. 15, pp. 18-22, May 2009.
[8] M.G. Burzo, P. L. Komarov, and P. E. Raad, “Thermal Transport
Properties of Gold-Covered Thin-Film Silicon Dioxide,” IEEE
Transactions on Components and Packaging Technologies, Vol. 26,
pp. 80-88, 2003.
[9] P. E. Raad, “Thermography Measurement System for Conducting
Thermal Characterization of Integrated Circuits,” U.S. Patent No.
7,444,260 (2008)
©EDA Publishing/THERMINIC 2009 39
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7-9 October 2009, Leuven, Belgium
Design Modeling and Simulation of Electrothermally
Actuated Microgyroscope Fabricated using the
MetalMUMPs.
Rana I. Shakoor *† , Shafaat A. Bazaz, ** and M. M. Hasan *
*
Pakistan Institute of Engineering and Applied Sciences, Islamabad, Pakistan.
**
Institute of Engineering and Applied Sciences, Topi, Swabi, NWFP, Pakistan.
† Corresponding author, iqtidar@pieas.edu.pk, Tel: +92 333 5193862
Abstract— This paper presents a thermally actuated
resonant microgyroscope fabricated using commercially
available standard MEMS process MetalMUMPs. Chevronshaped
thermal actuator is being used to drive the proof
mass whereas sensing mechanism of the proposed device is
based on the parallel plate sensing electrodes. The proposed
model consists of three proof masses coupled with each
other to be driven in through a frame. To achieve larger
bandwidth and increased sensitivity, the proposed model of
microgyroscope is operated with a slight mismatch in the
resonant frequency. The resonant frequencies of
microgyroscope are predicted to be 5.37 kHz for drive mode
and 5.02 kHz for sensing mode. Finite element simulations
are carried out to predict the performance of the proposed
device using the thermo-physical properties of electroplated
nickel. A brief theoretical description, dynamics and
mechanical design considerations of the proposed
gyroscopes model are also discussed. Prototype fabrication
using MetalMUMPs has also been investigated in this study.
Static simulation predicted a high drive displacement of 4.88
µm at 0.1V dc whereas dynamic transient simulations
predicted a displacement of 0.28 µm when a sinusoidal
voltage of 0.1V is applied. The proposed device has a size of
1.8 x 2.0 mm 2 with an estimated power consumption of 0.26
Watts.
Keywords: Finite element method, Micromachined Gyroscope,
MEMS, thermal V shaped actuator, Chevron shaped actuator
I. INTRODUCTION
Small size, high force, large displacement and low
voltage consumption are the primary concerns for the
development of MEMS based gyroscopes. Electrostatic,
piezoelectric and electromagnetic are the common driving
mechanisms used for the actuation of gyroscope proof
mass. Most popular among them is the electrostatic
actuation using comb drive actuators [1-2]. But these
electrostatic actuators have typically small deflections thus
require either close fabrication tolerances or high voltages
to achieve large deflections.
During last couple of years extensive research has been
carried out on actuators using thermal expansion effects
[3-4] activated by Joule heating. These thermal actuators
can provide a large force and actuation both in parallel and
perpendicular to the substrate and maybe fabricated using
surface-micromachining technology that is compatible
with IC technology. Two types of thermal actuators are
very common: hot/cold arm thermal actuators and ‘V’ or
‘Chevron’ shaped actuators.
In this paper we presented a novel Nickel based
resonant micromachined vibratory gyroscope which
utilizes Chevron shaped thermal actuator for driving the
vibrating proof mass of the gyroscope in the primary drive
mode. The main motivation to use a Chevron shaped
thermal actuator instead of a conventional electrostatic
actuator is its distinctiveness in terms of high force
generation combined with the large displacements at a low
excitation voltage [4]. Furthermore, such actuators may
enable higher quality factor compared to the comb drive
actuators, as it reduce the damping significantly and
enhancing the use of such chevron based gyroscopes at
atmospheric pressure. The electroplated Nickel was used
as the structural layer for this Chevron based
microgyroscope as the metals are much better for such
heat actuators as they provide a relatively large deflection
and force for low operating temperatures and power
consumption. The lateral deflection of the heat actuators
made from Ni metal is about ~ 60% larger than that of the
Si based actuators under the same power consumption [5].
The simulated results presented in this study predict that
Chevron shaped actuators made from metal may have
very promising characteristics for the drive mode
actuation of microgyroscopes.
After introduction, this paper will cover the brief theory
of operation of the thermally actuated chevron based
microgyroscope. Section II describes the mechanical
structure design of the device including its suspension
design implementation. Section III comprehends a
detailed implementation of low cost commercially
available MetalMUMPs process for the fabrication of
device along with prototype modeling of the device. In
section IV, an FEM based systematic sequential
thermoelectromechanical analyses methodology for the
proposed gyroscope using the MEMS design software
IntelliSuite is described. This section also presents the
simulation results for modal, static and dynamic transient
analyses of proposed microgyroscope.
II. MICROGYROSCOPE STRUCTURE
Fig. 1, shows a simplified three dimensional model of
the proposed microgyroscope. The proposed model
consists of three proof masses m 1, m 2 and m 3 which are
©EDA Publishing/THERMINIC 2009 40
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7-9 October 2009, Leuven, Belgium
coupled with each other using a frame to be driven in The suspension connecting proof masses m 1 and m 3 with
resonance electrothermally using a chevron-shaped the substrate via anchor is consisted of four double folded
thermal actuator along the x-axis. When
the gyroscope is
subjected to an angular rotation along the z-axis, Coriolis
force is induced in the sense direction along y-axis.
The general expression for the rotation induced Coriolis
flexures. These folded flexures
can be modeled as fixed-
to the axis of the
guided beams, deformed orthogonally
beam. The general expression
of the stiffness for such
flexure is:
force is 2Ω where is
the translational
velocity of the proof is mass in the rotating system and Ω
N ⎛
3
12EI
⎞ 2Etw
is the angular velocity vector. If both the drive and sense
k x =
=
n ⎜
3
mode have the same resonant frequencies, the Coriolis
L
⎟ 3
(1)
⎝ x ⎠ L x
force excites the system into resonancee causing the sense
electrodes along the sense y- direction
[6]. This motion
Where E is the Young’s Modulus, I=tw 3 /12 is the
creates a capacitance change due to change in the
second moment of inertia of the rectangular beam cross
electrode gap. This capacitance change is then detected by
section, t, L and w is the beam thickness, length and width
the CMOS capacitive interface circuit output of which is
respectively, N is the total number of the flexure
then conditioned using external electronics providing an
supporting the mass and n is
the number of folds per
electrical output proportional to the applied angular rate
flexure.
input [7].
Chevron actuator can be modeled as fixed-fixed beam if
we neglect the small angle change. For M number of
A. Suspension Design
beams of length of L c each, the stiffness of the Chevron
The complete suspension configuration of the system is shaped actuator can be calculated as [8]:
shown in Fig.2. Suspension flexures of the proposed
microgyroscope is designed in way that the all proof
⎡
3
192EII
⎤ ⎡16Etw
⎤
masses, m 1 , m 2 and m 3 moves together
under the driving
k
chev
= M ⎢ 3 ⎥ = M ⎢ 3 ⎥
force defining 1-DoF drive mode. The center mass m 2 is
⎢⎣ L c ⎥⎦ ⎢⎣ L c ⎥⎦
free to oscillate in the orthogonal sense direction under the
(2)
influence of rotation induced Coriolis force.
Where M is the The overalll stiffness of the system in
drive x-direction can be calculated by adding the
expression given in (1) and (2).
The suspension system of mass m 2 comprised of four
triple-folded flexure and stiffness in the sense y-direction
for the mass m 2 can also be
calculated by using the
expression given in (3).
k
y
=
N
n
⎛
⎜
⎝
3
12
EI 2Etw
=
3 3
L ⎟ L
y
⎞
⎠
y
(3)
Fig. 1. The layout of the electrothermally actuated microgyroscope
Fig. 2. The suspension system configuration
III. PROTOTYPE
FABRICATION
A prototype gyroscope is designed to be fabricated in
the Metal-Multi User MEMS Processes (MetalMUMPs)
[9] for the design concept verification. MetalMUMPs is a
low cost, commercially available, general purpose
electroplated nickel micromachining process for MEMS
devices. MetalMUMPs consists of a 20μm thick
electroplated nickel layer used
as the primary structural
material and electrical interconnect layer. A trench layer
in the silicon substrate can also be incorporated for
additional thermal and electrical isolation. Process
simulation of the prototype carried out in MEMSPro and
the device is shown in Fig. 3. Cross sectional views are
given in Fig. 4 (a) and (b) to illustrate different layer used
during prototype fabrication.
The process steps involved
in the fabrication of the
proposed microgyroscope using
MetalMUMPs are shown
in Fig. 5. The overall size of the device is 2.2mm ×
2.6mm. The movable parts of the MVG like Chevron
shaped actuator, proof masses and folded flexure are
defined using the 20µm thick nickel layer. A 25µm deep
trench is defined underneath the movable parts of the
MVG to provide electrical and
thermal isolation from the
silicon substrate. The anchors and fixed parts are formed
©EDA Publishing/THERMINIC 2009 41
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7-9 October 2009, Leuven, Belgium
by the isolation oxide, nitride layers, anchor metal and
IV. FEM METHODOLOGY & RESULTS
nickel layers.
To verify design concept and
device parameters, device
level FEM simulation methodology for the proposed
microgyroscope is devised in this section.
Thermoelectromechanical (TEM) analysis module of the
MEMS Design software IntelliSuite has been used for this
purpose.
3D Builder is used to build and mesh the three-
dimensional geometry of the
MEMS structure before
transferring to TEM module to assign material properties,
loads and boundaries to fully
analyze a device in the
static, frequency and dynamic domain. Simpler and faster
simulations like modal and static analyses were performed
prior to lengthy dynamic simulations to understand the
initial behavior of the device.
A. Modal Analysis
Fig. 3. Microgyroscope fabricated through MetalMUMPs process First of all modal analysis was carried out to predict the
using L-Edit of MEMSPro.
natural frequencies and their respective mode shape for
the proposed microgyroscope. While calculating natural
frequencies and associated mode shapes, a residual stress
of 100 MPa has been incorporated with other
thermophysical properties of nickel (Ni) for accurate
results [9].
Fig. 6, (a) and (b) show the respective drive and sense
mode shape at 5.73 kHz and 5.02 kHz. A slight difference
in the natural frequency of both drive and sense mode is
intentionally made to achieve a larger bandwidth,
compromising the drive displacement at resonance.
(a)
(b)
Fig. 4. Cross sectional views of a microgyroscope (a) 3D view and
(b) 2D view
(a)
Fig. 5. Process flow for the fabrication of microgyroscope using
MetalMUMPs in MEMSPro (a) N-type silicon wafer (b) 2µm
thick isolation oxide layer (c) patterning of Oxide
1 layers (d) patterning
of 0.7µm thick Polysilicon layer (e) patterning of
anchor metal layer (f)
patterning of 20µm electroplated structural layer of Ni and trench etch in
the substrate.
(b)
Fig. 6. Modal analysis results (a) Drive mode at 5.37 kHz and (b)
Sense mode at 5.02 kHz.
©EDA Publishing/THERMINIC 2009 42
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7-9 October 2009, Leuven, Belgium
B. Static Analysis
To analyze the initial response of the proposed device,
static analysis is performed. This analysis calculates the
results for the stress distribution, displacement distribution
and mechanical deformation of the structure. In case of
the thermally actuated microdevices like the proposed
one, static analysis generally comprised of thermalelectrical
and thermal-stress analyses. Thermal-electrical
analysis solves coupled thermal electrical equations
whereas thermal-stress analysis calculates mechanical
stresses in the device due to the thermal loads calculated
during the thermal-electrical analysis [10].
Predicted displacement vs. voltage and temperature vs.
voltage plots are presented in Fig. 7. Static analysis is
carried out over a range of applied static voltages from
0.10-0.13V with an increment of 0.05V. The results Fig. 9. Temperature profile predicted by the Static analysis at 0.1V dc.
showed that achieved displacements and temperatures are
the function of the V 2 at constant resistivity. A drive
C. Dynamic Analysis
displacement of 109 µm/V along with a temperature rise FEA based dynamic simulation results are shown in
of 640 o C/V predicts that voltage-stroke ratio of the Fig. 10. The thermal actuator was driven by a sinusoidal
proposed device is very high in comparison with voltage of 0.1V at 2.51 kHz, half of the operating
electrostatic comb drives. Displacement and temperature frequency as one sinusoidal cycle results in two complete
profile of the device at 0.10V DC is shown in Fig. 8 and 9. cycles of the thermal actuator [4]. The predicted drive
A predicted displacement of 4.88 µm with a temperature displacement achieved by the proof mass is 0.28µm
of 52 o /C is achieved by the device at this voltage.
(shown blue in Fig. 10(a)). The temperature profile
developed across the device when subjected to the same
voltage excitation signal is shown in Fig. 10 (b).
Fig. 7. Predicted drive direction displacement and maximum temperature
at different applied static voltages.
(a)
Fig. 8. Displacement profile predicted by the Static analysis at 0.1V dc.
(b)
Fig. 10. (a) Displacement and (b) temperature profile predicted when the
Dynamic analysis is carried at 0.1V ac applied at 2.51kHz.
©EDA Publishing/THERMINIC 2009 43
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
CONCLUSION
A novel design concept of a thermally actuated Ni
based resonant micromachined gyroscope utilizing
Chevron shaped thermal actuator to drive proof mass is
presented in this paper. The simulation results have
successfully demonstrated that Chevron shaped thermal
actuator has a strong potential to replace the traditional
interdigitated comb drive electrostatic actuator. Exploiting
the thermophysical properties of electroplated Ni, high
drive direction amplitudes of 4.88µm and 0.28m at low
actuation static and periodic voltage of 0.1V with an
estimated power consumption of 0.26 watts and reduced
device size of 1.8 x 2.0 mm 2 . This paper further
demonstrated that low cost commercially available
MetalMUMPs can be a cost effective fabrication option
for future microgyroscopes. These actuators have low
damping compared to electrostatic comb drive actuators
which may result in high quality factor microgyroscopes
operating at atmospheric pressure.
ACKNOWLEDGMENT
This research is mainly supported by Higher Education
commission of Pakistan (HEC) through 5000 Indigenous
fellowship program. Authors are thankful to National ICT
R&D Fund, Ministry of Information technology, Pakistan
for their financial assistance to promote MEMS activities
in Pakistan.
REFERENCES
[1] Said E. Alper and Tayfun Akin, “A Single-Crystal Silicon
Symmetrical and Decoupled MEMS Gyroscope on an Insulating
Substrate” J. Microelectromechanical Systems, 14(4), 2005, pp
707-717.
[2] C. Acar, Andrei M. Shkel, “Non resonant Micromachined
Gyroscopes with Structural Mode-Decoupling” IEEE Sensor
Journal, 3(4), 2003, pp 497-506.
[3] R. Hickey, D. Sameoto, T. Hubbard and M. Kujath, “Time and
frequency response of two-arm micromachined thermal actuator”
Journal of Micromechanics and Microengineering, 13, 2003, pp
40-46.
[4] Y. Lai, J. McDonald, M. Kujath and T. Hubbard “Force,
deflection and power measurement of toggled microthermal
actuators” Journal of Micromechanics and Microengineering, vol.
14, pp 49-56. (2004)
[5] J. Luo, J. He, , A. Flewitt, D. F. Moore, S.M. Spearing, N. A.
Fleck, W. I. Milne, “Development of all metal electrothermal
actuator and its application” J. Microlith.,Microfab., Microsyst.,
2005, 4(2), , pp 023012-1-10
[6] Rana I. Shakoor, Shafaat A. Bazaz, M. Kraft, Y. Lai, M.M. Hasan
“Thermal actuation based 3-DoF Non-resonant Microgyroscope
using MetalMUMPs.” Sensors, 2009, pp. 2389-2814.
[7] Said E. Alper, Kanber M. Silay, Tayfun Akin “A low-cost rategrate
Nickel gyroscope” Sensors & Actuators A, 132(2006), pp.
171-181.
[8] Young, W. C. Roark’s Formulas for stress and strain. Mc-Graw-
Hill, New York, USA, 1989, pp 93-156.
[9] Cowen, A., Dudley, B., Hill, E., Walters, M., Wood, R., Johnson,
S., Wynands, H. and Hardy, B. MetalMUMPs Design Hand book
(MEMSCap Inc. USA.)
[10] IntelliSuite Technical Reference Manual 8.2, 2007, IntelliSense
Inc. USA.
©EDA Publishing/THERMINIC 2009 44
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Fine Grain Thermal Modeling of 3D Stacked
Structures
H. Oprins 1 , M. Cupak 1 , G. Van der Plas 1 , P. Marchal 1 , B. Vandevelde 1 , A. Srinivasan 2 , E. Cheng 2
1
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
2 Gradient Design Automation Inc., 4633 Old Ironsides Drive, Santa Clara, CA 95054, USA
Abstract- 3D stacking of dies is a promising technique to
allow miniaturization and performance enhancement of
electronic systems. Key technologies for realizing 3D
interconnect schemes are the realization of vertical connections,
either through the Si-die or through the multilayer
interconnections. The complexity of these structures combined
with reduced thermal spreading in the thinned dies complicate
the thermal analysis of a stacked die structure. In this paper a
methodology is presented to perform a detailed thermal
analysis of stacked die packages including the complete back
end of line structure (BEOL), interconnection between the dies
and the complete electrical design layout of all the stacked dies.
The calculations are performed by 3D numerical techniques
and the approach allows importing the full electrical design of
all the dies in the stack. The methodology is demonstrated on a
2 stacked die structure in a BGA package. For this case the
influence of through-Si vias (TSVs) on the temperature
distribution is studied.
Keywords –thermal modeling, design layout, thermal aware
design, 3D stacked ICs.
I. INTRODUCTION
General trends in microelectronics show increase in
functionality and power dissipation combined with an
ongoing miniaturization [1]. These trends lead to increasing
power densities in the dies. As a result these elevate power
densities might give rise to excessive operating temperatures
which influence the electrical performance and reliability of
the device. 3D stacking of dies is an enabler for further
miniaturization and increase of functionality [2]. Here the
individual dies are thinned down aggressively – down to
about 20 μm – and are glued on top of each other. In the case
of such 3D stacks even more thermal issues appear [3]. The
glue used to bond the dies together typically is poorly
conductive. Furthermore the thinned dies will only allow a
reduced thermal spreading effect compared to full thickness
dies. Therefore the same dissipation will lead to higher
temperatures in a stacked die package compared to a single
die package. Other aspects to be considered are multiple
localized areas of heat dissipation in the different dies, the
complex interconnection schemes between and/or through
the dies which allow multiple paths for the heat flow and the
complicated back end of line (BEOL) structure metal and
oxides. In the case of a full thickness die the thermal
influence of the BEOL is limited on temperature distribution
in the conductive silicon. However in the case of thinned
dies the thickness of the BEOL can be of the same order as
the thickness of the Si itself (up to 10 µm thickness for a 10
metal layer BEOL structure), and should be included in the
thermal analysis.
Therefore there is a need to perform a detailed thermal
analysis including the structure of the BEOL and the location
of all the power sources in the layout. Furthermore the
thermal analysis should be included in the design loop to
assess the thermal consequences of design iterations and
verify the final design before sign-off. Turowski et al. [5]
presented a multiscale analysis for a single die. [3], [6–8]
present a compact model approach using transfer functions
for a thermal analysis on a higher level of abstraction for a
stacked die structure. In this paper a methodology is
presented for a full detail analysis based for stacked dies on
the design layout of all the stacked dies. In this approach
Cadence Virtuoso TM is used for the layout design and the
thermal simulator FireBolt TM [4] for the thermal analysis. In
section II the general approach is explained. In section III
this approach is demonstrated on a specific test case of a
structure of 2 stacked dies packaged in a BGA.
In section 2 the general approach to perform the detailed
simulations is explained. This approach is applied on a
typical case of a two die stack with TSVs and integrated
heaters and sensors. The results of these simulations and the
validation aspects are discussed in section 4.
Simulation setup
Selection of simulation domain for thermal analysis
Deriving package model from global modeling or
from available package information
Build up layer stack in the simulation domain
Import design layout and power maps
Detailed thermal simulation in simulation domain
Results and interpretation
Fig. 1. Flow chart with the consequent step in the approach for detailed
thermal modeling of a stacked die structure.
©EDA Publishing/THERMINIC 2009 45
ISBN: 978-2-35500-010-2

OASIS files
Final 2D layout
design_top.oas.gz
design_bot.oas.gz
Adding Extra
Layers
Cadence Virtuoso
design.tf
design.drf
Package
Model
Pkg.ini
Oasis2GDSII
Translation
CalibreLITHOView
Layout
Modifications
Cadence Virtuoso
Heaters/Monitors
Layout Data
Extraction
Cadence Virtuoso
SKILL scripts
AWK scripts
Layers
Specification
design.layerprops
layers_t.map
layers_b.map
GDSII files
2D Layout
design_top.gds.gz
design_bot.gds.gz
Heaters/Monitors
Specification
design.ptab
Heaters Power
Dissipation
AWK scripts
2D to 3D Layout
Translation
Cadence Virtuoso
GDSII top
level 3D Layout
design.gds.gz
Techonology
Files
design.lyrs
local_lib.tcl
gdatech.tcl
Heaters/monitors
Power Dissipation
design.pval
GDSII files
3D Layout
design_top.gds.gz
design_bot.gds.gz
GDA thermal simulation
Computed
Temperatures
design.tval
Fig. 2. Flow chart of the preparation procedure of the 3D layout design and
material information to be used in the thermal simulation.
II. METHODOLOGY
Fig. 1 shows an overview of the different steps in the
methodology to perform a detailed thermal analysis
including the full chip design. In the first step the main
region of interest in the structure is selected. There is large
difference in length scale in the thermal phenomena in the
structure; from the heat generation at transistor level
(submicron level) to the board level and ambient (cm-level).
Therefore a partitioning is being made between the main
region of interest, in which the full 3D thermal analysis will
be performed numerically and the outside area which will be
transformed to thermal boundary conditions for simulation in
the internal part [9]. In this case the internal region, to be
simulated in detail is the die stack and the interface layers
and interconnections in between them.
The package (overmold, interposer,…), solder balls, PCB
and ambient environment will be converted to a ‘package
model’ in a second step and will be used as boundary
conditions for the detailed simulation. This can be done
using the thermal package properties in the data sheet or by
extracting the information from a system (board) level
simulation to estimate the heat flow through each of the
sides. In this case steady state or transient boundary
condition are extracted from the higher level simulation tool
and represented as thermal RC networks to mimic the
thermal behavior of the surrounding of the simulation
domain. This RC representation is referred to as a ‘package
model’. Depending on the structure of the package a more
complex package model can be used to represent the external
part of the structure to account for the local effect of
wirebonds or solder balls.
The third step in the approach shown in Fig. 1 is the
representation of the materials used in the die stack. Here all
material properties, their temperature dependencies and the
thickness of the respective layer are specified for the
materials present in design layout files. This description of
the layer stack links the design layout to the actual 3D
simulation model. Fig. 2 shows a schematic representation of
the preparation and transformation of the separate individual
7-9 October 2009, Leuven, Belgium
GDSII design files of all the dies in the stack to the
representation of the 3D stacked structure. The process
consists of several steps. After optional format conversion
which translates data to the Cadence Virtuoso layout design
tool, the layout is converted from a 2D to a 3D
representation. This step brings back the stack hierarchy
flattened in the post-layout design phase and opens space for
possible thermal layout modifications (i.e. adding extra
layers representing overmold). Next the inputs for the
thermal simulator are added. These include the top level 3D
description of the layout, the exact locations of the thermal
sources and the monitors location. The inputs are generated
making use of automated Linux scripts. The rest of the input
files which define the design layers, the material list, the
thermal-layer list and the material-layer definition, are
generated manually. This data preparation in a semi-manual
way is a tedious and error-prone process. Ideally the design
and data preparation should be done in a 3D environment
and in a fully automated manner to allow and check
consistency and alignment between the layouts in the
different layers. At this moment the integrated 3D
functionality is not yet available in the EDA tools .
When all information is assembled correctly the
simulation domain is discretized using the thermal
simulation tool FireBolt [4]. FireBolt [4] solves the the heat
diffusion equation [11] , which in steady state, in Cartesian
co-ordinates is
∇⋅[ k( r, T) ∇ T ( r)] + P V
( r ) = 0
(1)
where r ≡ ( x, y, z)
in (m), T is the temperature (K), k is the
thermal conductivity (W/(mK)), and P V is the power density
(W/m 3 ) . Boundary conditions (BCs) are expressed at the six
die faces as described in “Package Model” Section III.B. P V
is considered invariant with temperature, assuming power
values may be iteratively updated in an electro-thermal loop
(not done in this case). Sub continuum heat-transport is
modeled where required. FireBolt uses fast meshless
methods for initial discretization of the 3DIC, followed by
refinement iterations in an adaptive, multi-level hierarchical
modeler and solver. Simplification of the layout in a single
die, or 3DIC, may result in significant errors in thermal
simulation [12]. Even non-functional layout such as metal
fill may significantly affect heat-transport in a chip. In
FireBolt the 3DIC chip is modeled at the length-scales of its
layout geometries, as needed to meet specified spatial and
thermal error-tolerances.
Fig. 3. Schematic of the test case of two stacked dies: a 25µm thin top die
5x5mm² with TSVs on top of a thicker 250 µm thick die 8x8mm² in a BGA
type package.
©EDA Publishing/THERMINIC 2009 46
ISBN: 978-2-35500-010-2

III.
CASE STUDY: 2 STACKED DIE STRUCTURE
In this the section the general approach detailed thermal
modeling presented in the previous section for is applied on
specific 3D integrated structure. A schematic of the test case
is shown in Fig.3. The test case consists of a two die stacked
structure in a BGA package. The BGA package in soldered
to a PBC and the whole structure considered to be in an
ambient environment of still air at 300K. The top die is a 25
µm thick die, 5x5 mm² in size. The active region of the top
die is connected to the bottom die by means of Cu through-
Si vias (TSVs) through the top die [13]. These vias have a
diameter of 5µm. Several pitches of the TSVs are considered
to study the effect of the TSV on the thermal behavior or the
stack. The bottom die is an 8x8 mm² die with a thickness of
250µm. The different steps of the procedure presented in
Fig. 2 with now be dealt with in detail.
A. Definition of simulation domain
First the region of interest is selected in the structure. In
this domain the detailed numerical simulation will be
performed. In this test case the stack including the 2 Si dies,
the adhesive layer in between the dies. Also all the
interconnections between the two dies and the complete back
end of line structure (BEOL) of both dies are included in the
model. To simplify the geometry of the simulation domain
part of the overmold compound surrounding the top die is
included in the model.
B. Package model
The region outside the simulation domain is converted to
thermal boundaries conditions applied on the simulation
domain. Inside FireBolt, the boundary conditions are
formulated for each face S i with uniform heat transfer
coefficient h i and thermal capacitance c i parameters as
shown in the following equation where φ is the flux density:
dT ( ri
)
ϕ r = h ⋅ T r − T + c ⋅ with r ∈S
(2)
( ) ( ( ) )
i i i A i i i
dt
Here the parameters of the package model are extracted
from a full 3D finite element model of the package and PCB.
For the finite element analysis the software tool Msc.Marc is
used. From this thermal model the heat flow through each of
the faces of the simulation domain can be obtained and
converted to boundary conditions in the form of RC thermal
networks, to be used in the detailed model.
7-9 October 2009, Leuven, Belgium
Bottom view
Heat flux (W/mm 2 )
Fig. 5. Distribution of the heat flux at one quarter of the bottom of the die
stack extracted from the FE model of the package and PCB.
The board level finite element of the structure can be seen
in Fig. 4 (left). Fig. 4 (right) shows a schematic
representation of RC networks as boundary conditions at the
sides of the simulation domain. At the location of the
wirebonds at the top the die stack and the solder balls at the
bottom addition faces S i can be attributed with a local higher
value of h i , since the wirebonds and solder balls act as local
heat sinks. Fig. 5 show a bottom view of the distribution of
the heat flow through the bottom of the considered
simulation domain. Higher values of the heat flux at the
bottom of the die stack can be observed at the locations
corresponding with the placement of the solders balls.
C. Material layer stack information
In this step of the data preparation the information of the
several materials and thickness of the respective material
layers is included. Fig. 6 gives a schematic overview (not to
scale) of the material layers and their respective thickness in
the die stack. For both the top and the bottom die a BEOL
structure with 2 metal layers is used.
PASSIV_T
METAL2_T
METAL1_T
CA_T
BULK_T
TSV
bump
metal
metal
via
250nm
poly 150nm
500 nm SiN
330nm Si0 2
600nm Si0 2
500nm Si0 2
300nm Si0 2
400nm Si0 2
25 um Si
50 nm SiC
50 nm SiC
50 nm SiC
50 nm SiC
50 nm SiN
METAL2_B
metal
600nm Si0 2
50 nm SiC
via
500nm Si0 2
50 nm SiC
METAL1_B
metal
300nm Si0 2
50 nm SiC
CA_B
BULK_B
250nm
poly 150nm
400nm Si0 2
250um Si
50 nm SiN
Fig. 4. Full 3D FE model of the package and PCB (left). Representation of
the boundary conditions applied on the simulation domain (right).
Fig. 6. Schematic representation of the materials in the die stack (not to
scale), including the BEOL structure of the top and bottom die.
©EDA Publishing/THERMINIC 2009 47
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7-9 October 2009, Leuven, Belgium
Bottom die: 8x8 mm²
Top die: 5x5 mm²
TSVs top die
Heaters
100 x 100 µm²
•7 x 7 TSVs
• 11 x 11 TSVs
• no TSVs
Heaters
50 x 50 µm²
Fig. 7. Combined view of the layout of the top die on top of the bottom die
including the heating structures and the TSVs through the top die.
The metal layers of the top die are connected to the metal
layers of the bottom by TSVs (through-Si vias) through the
thinned top die [13]. At the backside of the top die, the TSVs
are connected to the metal 2 layer of the bottom die by small
CuSn bumps with a diameter of 20 µm and a height of 13
µm.
C. Design layout and power sources location
The design layouts of both individual top dies are
combined to a 3D design layout according to the procedure
specified in Fig. 2. Fig. 7 shows the 3D design for this stack
of a smaller die on top of a larger bottom die. In the figure
the location of 6 heat sources in indicated. This heat sources
are located in the ‘metal 2’ layer of the top die. In normal
operation of logic dies the heat is generated in a region close
to the top of the bulk of the Si. However in the thermal test
chips available the metal meander resistors to dissipate the
power are located in the ‘metal 2’ layer. To be able to
validate the modeling experimentally the heat sources are
therefore placed in the ‘metal 2’ layer in the model. In all
heat sources a power of 10mW is dissipated. This is a typical
value of the power dissipation in structures in low power
devices. For the 3 heat sources at the left side the area of the
heat source is 100x100 µm². At the right side of the top die,
the same amount of heat is dissipated in areas of 50x50µm².
Fig. 8. Surface plot of the temperature distribution (°C) in the metal 2 layer of
the top die for a power of 10mW dissipated in the heat sources with an array of
100x100µm² on the left side and 50x50µm² on the right side.
To study the influence of the TSV density on the
temperature distribution different array densities of TSVs are
placed right below the location of the heaters. The different
densities are an array of 7x7, 11x11 and no TSVs in the area
of 50x50 and 100x100µm² respectively. The locations of
these TSVs areas are indicated on Fig. 7.
D. Thermal simulation
The 3D steady state heat equation is solved numerically in
the simulation domain using the information of the package
and environment as boundary conditions as shown in Fig. 4.
A grid resolution matching the feature size in the design
layout is used for the discretization. For this specific design a
spatial resolution of 100 nm is used. Table 1 summarizes the
numerical details of the simulations. 10 mW is dissipated in
each of the heat sources in the metal 2 layer of the top die.
The total power dissipated in the structure is 6 x 10mW in
the heat sources in the top die. The ambient temperature is
considered to be 300K.
Since the temperature dependence of the material
properties is included several iterations are required to meet
the convergence criterion of 0.05°C. For this low power case
two iterations are sufficient to meet this criterion. Which
amounts to a typical calculation time of 4h30min.
TABLE I
SIMULATION PERFORMANCE DETAILS
Die size
X
8.34 mm
Y
8.34 mm
Z 280.68 µm
Power sources
Power level
60 mW
Nr. of sources 2100
Resolution
Thermal 0.05 °C
Spatial
100 nm
Calcualation
Runtime
~ 4h 30min
Peak memory
~ 5.8Gb
Fig. 9. Surface plot of the heat flux at the top the bulk of the Si of the top die.
©EDA Publishing/THERMINIC 2009 48
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7-9 October 2009, Leuven, Belgium
Fig. 10. Schematic representation of the experimental set up to validate the
thermal modeling [14].
IV. DISCUSSION OF SIMULATION RESULTS
Fig. 8 shows the temperature distribution in the ‘metal 2’
layer of the top die. This is the layer where the power is
dissipated. A sharp temperature peak can be observed at the
location of the hot spots. As expected the temperature peak
is higher in the smaller hotspots due to the higher power
density. In this case with the power dissipation in the metal
layer of the BEOL structure a very sharp peak is observed
due to the poorly conductive oxide layers surrounding it. For
normal operation with heat dissipation in the bulk of the Si a
less pronounced peak is expected. The influence of the TSV
density can be seen on Fig. 8: in the case without TSVs the
maximum temperature amounts to 8.08°C in the 50x50µm²
hot spot. For the TSV density of 7x7µm² and 11x11µm² the
temperature peak is 7.15°C and 5.51°C respectively. In the
case of the 50x50µm² hotspots the effect of TSV density is
less pronounced. Fig. 9 shows a surface plot of the heat flux
in the bulk of the Si of the top die. At the top of the TSV an
influx of heat can be seen. The heat is generated fairly
uniform in the layers on top the Cu TSVs. The heat will flow
down through the stack concentrated through the Cu TSVs.
V. EXPERIMENTAL VALIDATION APPROACH
To trust and improve the proposed approach of the
detailed thermal modeling the simulations need to be
validated by experimental results. To be able to evaluate the
thermal modeling early in the development of the 3D
integration including the TSVs a more simplified version of
the packaged die stack is considered. Therefore a dedicated
thermal test vehicle has been developed to experimentally
characterize the thermal effects in the stacked die structure
and to validate the modeling approach [14]. Fig. 10 shows a
schematic of the simplified package on which transient
thermal measurements are performed. The die stack is glued
to a Cu interposer plate. This Cu plate is attached to a watercooled
cooling block. On top of the outer edge of the Cu
plate a PCB is connected. In this PCB an opening is
provided to fit the die stack. Wirebonds from both the top
and bottom die to bonding pads on the PCB provide the
electrical connections to access the heaters and diodes in the
die stack. The power is dissipated in heaters located in the
BEOL structure of the top die. Temperature is measured
using temperature sensitive diodes which are located in both
top and bottom die. Assembly and testing of experimental
set-up is ongoing at the time of publication.
TIM 1
glue
Cu plate
TIM 2
Water cooled heat sink
PCB
VI. CONCLUSIONS
In this paper a methodology to perform a detailed, fine
grain thermal analysis of the stacked die structure is
presented. This methodology allows to include the complete
detail of the design layout and the full description of the
BEOL structure of all the dies in the stack. The approach is
demonstrated on a test case of a stacked die structure of two
dies BGA package. Both the complete design layout of the
top and bottom die, including the interconnections, such as
TSVs and solder balls, between both dies are combined to a
3D design. A detailed thermal simulation with a spatial
resolution of 100 nm is performed based on the 3D layout
specified in the GDSII file and the definition of the stack of
materials. Using this approach the thermal influence of the
proximity and array density of the below the heat sources
TSVs in the top die is studied.
REFERENCES
[1] The International technology Roadmap for semiconductors (ITRS),
2008 edition. URL:
http://www.itrs.net/Links/2008ITRS/Home2008.htm
[2] E. Beyne, “The Rise of the 3 rd Dimension for System Integration”
Proc. IEEE Int. Interconnect Technology Conference, pp. 1-5, 2006.
[3] M. Rencz, “Thermal Issues in Stacked Die Packages”, 21 st IEEE
SEMI-THERM Symposium, pp.307-312, March 2005.
[4 ] FireBolt (Nanoscale Full-Chip Thermal Simulator), Gradient
Design Automation, Inc, http://www.gradient-da.com/
[5] M. Turowski,, S. Dooley, A. Raman, M. Casto, Multiscale 3D
thermal analysis of analog ICs: From full-chip to device level, 14th
International Workshop on Thermal Inveatigation of ICs and
Systems, pp. 64-69, 2008.
[6] M. Rencz, V. Székely: Structure function evaluation of stacked
dies, Proceedings of the XXth SEMI-THERM Symposium, March
9-11, San Jose, CA, USA, pp 50-55, 2004.
[7] Enrico A. Garcia, Chia-Pin Chiu: Compact Modeling Approaches to
Multiple Die Stacked Chip Scale Packages. , 19th IEEE SEMI-
THERM Symposium, pp. 160-167, 2003.
[8] Li Zhang, Noella Howard, Vijaylaxmi Gumaste, Amindya Poddar,
Luu Nguyen: Thermal Characterization of Stacked-Die Packages,
20th IEEE SEMI-THERM Symposium, pp. 55-63, 2004.
[9] R. Gillon, P. Joris, H. Oprins, B. Vandevelde, A.Srinivasan, R.
Chandra, Practical chip-centric electro-thermal simulations,
Proceedings of THERMINIC, Rome, Italy, pp. 220-223, 24-26
September 2008.
[10] C. Chiang, S. Sinha, The road to 3D EDA tool readiness,
Proceedings of the 2009 Asia and South Pacific Design Automation
Conference, pp. 429 – 436, 2009.
[11] E.R. Eckert and D. Eckert, "Analysis Of Heat And Mass Transfer",
eq (1-14), p.11, CRC Press, 1986.
[12] S. Melamed, T. Thorolfsson, A. Srinivasan, E. Cheng, P. Franzon
and R. Davis, "Junction-level Thermal Extraction and Simulation
of 3DICs", IEEE International Conference on 3D System
Integration (3D IC), Sep 2009.
[13] B. Swinnen et al., “3D Integration by Cu-Cu Thermo-Compression
Bonding of Extremely Thinned Bulk-Si Die Containing 10 μm
Pitch Through-Si Vias”, Int. Electron Devices Meeting, pp. 1-4,
December 2006.
[14] C. Torregiani, V. Cherman, F. Duflos, R. Labie, B. Vandevelde,
3D-SIC: Thermal modeling & experimental validation, presentation
at IMEC Core Partner Week: 3D Integration, 20 - 24 October 2008.
©EDA Publishing/THERMINIC 2009 49
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7-9 October 2009, Leuven, Belgium
Emulation-Based Transient Thermal Modeling of
2D/3D Systems-on-Chip with Active Cooling
David Atienza
Embedded Systems Laboratory (ESL), EPFL
ESL-IEL-STI-EPFL, Station 11, CH1015, Lausanne, Switzerland
E-mail: david.atienza@epfl.ch
Abstract-New tendencies envisage 2D/3D Multi-Processor
System-On-Chip (MPSoC) as a promising solution for the
consumer electronics market. MPSoCs are complex to design,
as they must execute multiple applications (games, video), while
meeting additional design constraints (energy consumption,
time-to-market, etc.). Moreover, the rise of temperature in the
die for MPSoCs, especially for forthcoming 3D chips, can
seriously affect their final performance and reliability. In this
context, transient thermal modeling is a key challenge to study
the accelerated thermal problems of MPSoC designs, as well as
to validate the benefits of active cooling techniques (e.g., liquid
cooling), combined with other state-of-the-art methods (e.g.,
dynamic frequency and voltage scaling), as a solution to
overcome run-time thermal runaway.
In this paper, I present a novel approach for fast transient
thermal modeling and analysis of 2D/3D MPSoCs with active
cooling, which relies on the exploitation of combined hardwaresoftware
emulation and linear thermal models for liquid flow.
The proposed framework uses FPGA emulation as the key
element to model the hardware components of 2D/3D MPSoC
platforms at multi-megahertz speeds, while running real-life
software multimedia applications. This framework
automatically extracts detailed system statistics that are used as
input to a scalable software thermal library, using different
ordinary differential equation solvers, running in a host
computer. This library calculates at run-time the temperature
of on-chip components, based on the collected statistics from
the emulated system and the final floorplan of the 2D/3D
MPSoC. This approach creates a close-loop thermal emulation
system that allows MPSoC designers to validate different
hardware- and software-based thermal management
approaches, including liquid cooling injection control, under
transient and dynamic thermal maps. The experimental results
with 2D/3D MPSoCs illustrate speed-ups of more than three
orders of magnitude compared to cycle-accurate MPSoC
thermal simulators, at the same time as preserving the accuracy
of the estimated temperature within 3% of traditional
approaches using finite-element simulations for 3D stacks and
liquid cooling.
Keywords – Thermal modeling, transient analysis, FPGA
emulation, 2D/3D MPSoC, active cooling, close-loop
systems
I. INTRODUCTION
The power density of high performance systems continues to
increase with every process technology generation. Nowadays,
several commercial multi-processor system-on-chip (MPSoC)
architectures are available several tens of cores, such as IBM’s
Cell [1], Sun’s Niagara T1 [2] and Tilera’s 64-core architecture
[3]. However, in these new MPSoC architectures, power
density increases the operating temperature and creates
significant hot-spots on the die that need to be managed.
Furthermore, 3D stacking is an emerging solution to increase
the integration capabilities and frequency of forthcoming
MPSoCs [4,5], but it substantially increases further power
density due to the placement of computational units on top of
each other. Therefore, temperature-induced problems
exacerbate in 3D systems and are a major concern to be
explored as early as possible in 3D MPSoC design and
integration.
To explore the hardware/software (HW/SW) thermal
interaction, cycle-accurate MPSoC simulators including SW
thermal models exist, based on post-processing of run-time
power consumption and floorplanning information [6, 7, 8].
However, these complex SW environments are very limited in
performance (i.e., up to 100 KHz) due to signal management
overhead and are not interactive with thermal control systems
in real-time. Thus, they are not suitable for thermal control
exploration in 2D/3D MPSoCs running complex real-life
applications. Moreover, higher abstraction levels simulators
attain faster simulation speeds, but lose significantly the
accuracy for fine-grained thermal-aware architectural tuning or
thermal modeling.
One alternative to cycle-accurate simulators is HW
emulation. Various MPSoC emulation frameworks have been
proposed [9, 10, 11]. Nevertheless, they are not designed for
thermal exploration and are usually very expensive for
(between $100K and $1M) and not flexible enough for MPSoC
architecture exploration since their baseline architectures (e.g.
processing cores or interconnections) are proprietary, not
permitting internal changes. Furthermore, no flexible
interconnection interfaces between HW emulation and also no
fast thermal libraries that model active cooling behavior (e.g.,
liquid cooling [12, 13]) exist nowadays. Thus, thermal effects
can only be verified in the last phases of the design process,
typically when the final architecture and cooling components
are available can be tested in the final system integration
process, which can typically result in very expensive MPSoCs
redesigns.
As a result, one major design challenge is the deployment of
fast exploration methods of multiple HW and SW
implementation alternatives for 2D and 3D MPSoCs with
©EDA Publishing/THERMINIC 2009 50
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accurate estimations (e.g. performance, energy) that address the
modeling of transient thermal behavior to tune the final 2D/3D
MPSoC architectures.
In this paper I present a new HW/SW FPGA-based emulation
framework of the 2D/3D MPSoC architectures, which enables
realistic thermal studies in an early stage of system integration,
including active (liquid) cooling modeling, as well as power,
energy and performance constraints validation in real-time.
First, the HW components of 2D/3D MPSoC components are
mapped on an FPGA-based framework and statistics are
extracted from three key MPSoC architectural levels
(processors, memory subsystem and interconnections), while
real-life applications are executed. Second, this run-time
information is sent using a standard Ethernet connection to a
dynamically adaptable SW thermal modeling tool running on a
host PC. Third, this tool evaluates in real-time the thermal
behaviour of the final MPSoC design, selecting different
ordinary differential equation solvers according to the desired
accuracy in thermal exploration and simulation time of 2D/3D
chip stacks, and returns this information to the FPGA
emulating the MPSoC design. This final step creates a closedloop
thermal simulation environment for 2D and 3D chips that
enables testing temperature management strategies in real-time.
The experiments results with 2D/3D MPSoCs, using real-life
case studies models of the UltraSPARC T1 [2] and other
industrial platforms from Freescale [14], Philips [15], etc.,
show that this HW/SW emulation framework for transient
thermal analysis can achieve speed-ups of more than three
orders of magnitude compared to state-of-the-art cycle-accurate
2D/3D MPSoC thermal simulators, while keeping the accuracy
of uncertainty levels of the simulated temperature obtained
with the proposed method within 3% with respect to finiteelement
simulations.
The remainder of this paper is structured as follows. It starts
in Section II with a detailed overview of prior art in thermal
modeling and architectural simulation for 2D and 3D MPSoCs.
Then, in Section III it is presented the proposed HW/SW
thermal emulation flow for 2D/3D MPSoCs. Next, in Section
IV it is described the 3D liquid cooling model. After that, in
Section V we present the experimental setup and results with
different 2D and 3D MPSoCs. Finally, in Section VI, I
summarize the main conclusions of this work.
II.
RELATED WORK
It is widely accepted that 2D/3D MPSoCs represent a
promising solution for forthcoming complex processing
systems [18]. This has spurred research on modeling and
prototyping MPSoC designs, using both HW and SW. From
the SW viewpoint, solutions have been suggested at different
abstraction levels, enabling tradeoffs between simulation speed
and accuracy. First, fast analytical models have been proposed
to prune very distinct design options using high-level
languages (e.g., C or C++) [19]. Also, full system simulators,
like Symics [20] and others [7, 8], have been developed for
embedded SW debugging and can reach megahertz speeds, but
are not able to accurately capture performance and power
effects (e.g., at the interconnection level) depending on the
cycle-accurate behavior of the HW. Second, transaction-level
7-9 October 2009, Leuven, Belgium
modeling in SystemC, in academic [21] and industrial context
[22, 23] has enabled more accuracy in system-level simulation
at the cost of sacrificing simulation speed (about 100–200
KHz). Such speeds render unfeasible the transient testing of
large systems due to overly long simulation times, conversely
to the proposed 2D/3D thermal emulation framework.
Moreover, in most cases SW simulations are only limited to a
number of proprietary interfaces.
Finally, important research has been done to obtain cycleaccurate
frameworks in low-level SystemC or HDL languages.
Companies and universities have developed cycle-accurate
simulators using post-synthesis libraries from HW vendors [27,
28]. However, their simulation speeds (10–120 KHz) are
unsuitable for long MPSoC thermal exploration.
The most important alternative nowadays to MPSoC
simulation is HW emulation. In industry, one of the most
complete sets of statistics is provided by Palladium II [9],
which can accommodate very complex systems (i.e., up to 256
Mgate). However, its main disadvantages are its operation
frequency (approximately 1.6 MHz) and cost (around $1
million). Then, ASIC integrator [10] is much faster for MPSoC
architectural exploration. Nevertheless, its major drawback is
its limitation to only up to few ARM-based cores and only
AMBA interconnects. The same exploration limitation of
proprietary cores occurs with Heron SoC emulation [24] and
Zebu-XL [11], both based on multi-FPGA emulation in the
order of MHz. They can be used to validate intellectual
property blocks, but are not flexible enough for fast MPSoC
design exploration or detailed statistics extraction. In the
academic world, a recent emulation platform for exploring
performance of MPSoC alternatives is TC4SOC [25]. It uses a
proprietary 32-bit VLIW core and enables exploration of
interconnects by using an FPGA, but, it does not enable
detailed extraction of statistics and performing thermal
modeling at the other three architectural levels proposed in this
work, i.e., memory hierarchy, interconnects and processing
cores. Finally, an interesting approach that uses FPGA
prototyping to speed-up co-verification of pure SW simulators
is described in [26], which uses a cycle-by-cycle
synchronization basis with the C/C++ SW part by using an
array of shared registers in the FPGA that can be accessed by
both sides at a speed of 1 MHz, outlining the potential benefits
of combined HW-SW frameworks which it is exploited in the
proposed approach to reach an MPSoC emulation speed of
hundreds of MHzs.
Turning our attention to thermal modeling, [6] presented a
thermal/power model for 2D super-scalar architectures. It can
predict the temperature variations between the different
components of a processor and show the expected influence in
performance. Additionally, [14, 17] have investigated the
impact of temperature and voltage variation across the die of
2D and 3D MPSoCs. Their results show that the temperature
can vary by more than 25 degrees across the die and tiers. In all
these works, a “1D” approximation is often assumed to
evaluate the thermal behavior [29, 30]. This means that the
power is uniformly produced on active levels (or on parts of
them), one per stratum. This assumption may lead to strongly
underestimated maximum temperature. Thus, several authors
[31] use this simplification but perform detailed simulation of
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3D thermal effects due to the presence and localization of
supervias, and analyze the local (3D) and global (1D) modeling
contribution to the maximum temperature, showing that
thermal resistance can be higher than 1D thermal resistance due
to local 3D effects and even more fine-grain transient analysis
need to be performed to avoid thermal overestimations.
Finally, numerical thermal simulations have been carried out to
convert power dissipation distribution into a temperature
distribution in a 3D IC [32]. Based on the past work, the
development of a fundamental analytical model for heat
transport in 3D integrated circuits is highly desirable. Such an
analytical model provides a framework in which to analyze the
general problem of heat dissipation in 3D ICs, and will enable
simple thermal design guidelines.
A key component of the 3D technology is the through-silicon
via (TSV) that enables communication between the two dies as
well as with the package. Several works have analyzed the
optimization of placement of TSVs for heat dissipation in 3D
ICs [31, 32]. Other works [33] propose analytical and finiteelement
models of heat transfer in 3D electronic circuits and
use this model to analyze the impact of various geometric
parameters and thermo-physical properties (through silicon
vias, inter-die bonding layers, etc.) on thermal performance of
a 3D IC, but at the cost of very time-consuming simulations.
Overall, all of these works prove the importance of hot spots in
2D high-performance multi-core systems (and even more in 3D
structures), as well as the need of accurate and fast transient
temperature analysis tools for the different architectural
components of MPSoCs (cores, TSVs, etc.). Thus, the
proposed emulation method aims at estimating accurately the
transient temperature of integrated circuits implementing
2D/3D MPSoCs, including active cooling mechanisms (e.g.,
liquid cooling).
III. HW/SW THERMAL EMULATION FLOW FOR MPSOCS
In Figure 1 it is depicted an overview of the instantiation of
the proposed HW/SW thermal emulation environment for a
Freescale-based 3-core MPSoC [14], implemented onto a
Xilinx Virtex-V FPGA, modeling the transient thermal
behavior of the system while executing multiple multimedia
applications (e.g., SW-defined radio, video streaming, etc.) and
a multi-processor operating system (OS). The system can be
scaled to any number of cores sub-systems by using
appropriate FPGAs.
The instantiation flow of the proposed HW/SW transient
thermal emulation environment is created in four steps. First,
the HW part of the MPSoC emulator is defined. It implies
synthesizing the MPSoC architecture onto a certain FPGA
target technology (a multi-FPGA environment exists, if it is
necessary). Second, specific hardware sniffers are included in
the FPGA that monitor particular signals of each component of
the target 2D/3D MPSoC architecture [15]. The purpose of this
step is to define a very fast method to extract the switching
activity of MPSoC components, while being transparent to the
normal MPSoC operation; thus, the power extraction method
does not interfere or alter the actual run-time power
consumption, conversely to including SW profiling to extract
the execution statistics of the target MPSoC.
Fig. 1. Overview of the 2D/3D MPSoC thermal emulation framework
In the third step, the run-time power information is sent using
a standard Ethernet connection to a dynamically adaptable SW
thermal modeling tool running on a host PC. This tool
evaluates in real-time the thermal behaviour of the final 2D/3D
MPSoC design using a thermal model developed for bulk
silicon chip systems [15], and calculates the temperature of
each cell according to the floorplan of the emulated MPSoC,
the frequency/voltage of each MPSoC component at run-time,
as well as the specific leakage power at run-time for each
component in the MPSoC. It includes different types of
ordinary differential equation solvers [16](Forward Euler 1 st
order, Crank-Nicholson 2 nd order method, Runge-Kutta 4 th
order method, etc.), which enables multiple trade-offs between
accuracy and thermal modeling time in 2D/3D chip stacks.
Finally, in the fourth step of the thermal emulation flow, the
temperatures calculated by the SW thermal library are sent
back to the FPGA emulating the MPSoC system (see link
between the host PC and the FPGA on the right side of Figure
1) and are stored in registers of the FPGA that emulate the
presence of thermal sensors in the target MPSoC in certain
positions of the floorplan.
This final mechanism provides real-time temperature
information visible by the running multi-processor OS on the
modeled 2D/3D MPSoC, as the registers storing the predicted
temperature are memory-mapped in a restricted position of the
memory hierarchy visible only by the OS of the MPSoC. Then,
the emulated temperature sensors are updated by the thermal
monitoring subsystem in regular intervals, typically
configurable in the range of 10 ms to 1s, according to the
system designer interest. Thus, thanks to a handshake
mechanism between the thermal model and the multi-processor
OS middleware to synchronize the upload/download of
temperatures, our extended framework implements a closedloop
thermal monitoring system, which enables exploring the
impact of thermal control mechanisms in the transient thermal
behavior of 2D/3D MPSoCs at multi-megahertz speeds.
IV.
ACTIVE COOLING MODEL FOR 2D/3D MPSOC
Modeling of the 3D stacked architecture with liquid cooling
can be accomplished in three steps: (i) defining a grid-level
thermal RC network of 2D/3D chip stacks, (ii) adding models
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for the interlayer material and TSVs distribution and (iii) measurements and heat source injection). This figure shows
modeling water flowing in independent thermal cell layers, that the average error in the worst thermal propagation part in
which represent microchannels in the stacks. These three steps 3D stack (inter-tier thermal model) is very small, i.e., 2.7%,
are detailed in this section.
and the maximum error is less than 5%.
A. RC Network for 2D/3D Stacks
2D/3D thermal modeling can be accomplished using an
automated model that forms the RC circuit for certain grid
dimensions. In this work, it is used the model proposed in [15],
which has been extended to include 3D modeling capabilities
as discussed in [17]. The extension for the existing multilayered
thermal modeling provides a new interlayer material
model to include the TSVs (cf. Section IV-B) and the
microchannels (cf. Section IV-C). Then, in a typical automated
thermal model, the thermal resistance and capacitance values of
the blocks or grid cells are computed initially at the start of the
simulation, considering that the system properties do not vary
at runtime. To model the heterogeneous characteristics of the
interlayer material including the TSVs and microchannels, I
introduce two major differences to other works: (1) as opposed
to having a uniform thermal resistivity value of the layer, our
infrastructure enables having various resistivity values for each
grid, (2) the resistivity value of the cell can vary at runtime.
The interlayer material is divided into a grid, where each grid
cell except for the cells of the microchannels has a fixed
thermal resistance value depending on the characteristics of the
interface material and TSVs. The thermal resistivity of the
microchannel cells is computed based on the liquid flow rate
through the cell, and the characteristics of the liquid at runtime.
Bonding
Pads
Epoxy with
alumina particles
Micro-Heaters
and
Temperature Sensors
Fig. 2. Manufactured 5-tier stack chip for 3D thermal library validation
The proposed RC thermal model has been calibrated for the
manufacturing technologies of 2D MPSoCs using experimental
data based on the technologies used by industrial partners (Sun,
Freescale, IBM, etc.). Then, the tuning of the version of the
thermal library for 3D MPSoCs has been performed by
manufacturing a 5-tier 3D chip stack with resistors and thermal
sensors, as shown in Figure 2.
Exhaustive experiments have been performed in the 5-tier stack
to characterize the possible inaccuracy of the proposed RC
thermal network for 2D/3D chip stacks. One of the measured
sets of experiments is shown in Figure 3, with heat sources
modeling cores in the first tier and measurements in the last tier
(to create the largest possible temperature variation between
336
333
330
327
324
321
318
315
312
Sim ulation
Inter Layer
Measurement
Layer 2 Layer 3 Layer 4 Layer 5
Fig. 3. Thermal measurements of inter-layer heat propagation vs. RC-network
simulations for the 5-tier stack chip
B. Through-Silicon-Vias Modeling
In order to model the effect of TSVs on the thermal behavior of
3D MPSoCs, it is necessary to first perform a study to
determine which modeling granularity is required. In the TSV
model it is required to provide a TSV density for each unit (i.e.,
core, cache, interconnect line, etc.). Therefore, it is assumed
that the effect of the TSV insertion to the heat capacity of the
interface material is negligible, which is reasonable as the total
area of TSVs constitutes a very small percentage of the total
area of the material. Then, it is differentiated among the
different block functionalities to adjust the TSV density. For
example, a crossbar structure requires a high TSV density,
while a processing core does not require any modeling of TSV
interference in its thermal spreading properties. As, a result, we
assign a TSV density to each unit based on its functionality and
system design choices. The TSV dimensions are set to 10µm x
10µm, and a minimum spacing of 10 µm from each side of the
TSV is employed. In fact, the experiments developed in the
calibrated 3D stack thermal simulation model of the 5-tier stack
indicates that a block-level granularity provides very similar
results to providing the exact locations of TSVs, while it has a
very important complexity reduction in transient thermal
analysis.
C. Active (Liquid) Cooling Modeling
Next, active cooling properties (i.e., liquid cooling) have
been modeled using additional layers of thermal cells with
different cooling thermal conductance and resistance properties
than silicon and metal layers, using IBM’s technology [12, 13].
In fact, in a 3D system with liquid cooling, the local junction
temperature can be computed using a resistive network, as
shown in Figure 4.
In this figure, the thermal resistance of the wiring layers (R b ),
the thermal resistance of the silicon (R Si ) and the convective
thermal resistance are combined to model the 3D stack.
Considering the heat flux (q) as the source and the chip backside
temperature (T fluid ) as the ground, the electrical circuit can
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be solved to get the junction temperature (T junction ). Thus, the
total thermal resistance (R tot ) of the junction is computed as in
Equation 2 [13]. The parameters of the equations are listed in
Table I, and their values are fixed according to [12] and [13].
R tot = R cond + R conv + R heat (1)
R tot = 1/(G si /t + 1/R b ) + A/(h.A t ) + A/(V.P.c p ) (2)
Fig. 5. Representation of microchannels/TSVs layout in emulated 3D MPSoCs
Fig. 4. Equivalent 3D resistive network including liquid cooling
According to [13], it is considered a base flow rate between
15ml and 150ml/min. Then, each channel has a width of
500µm and a depth of 300µm.
TABLE I
2D/3D THERMAL AND LIQUID COOLING CHARACTERISTICS
Parameter name
Definition
R tot Total thermal resistance
R cond Conductive thermal resistance
transient thermal analysis. In fact, the results of the exploration
of 2D thermal behavior on a commercial 8-core MPSoC [2] has
shown that the proposed thermal emulation can achieve speedups
of more than to 800× with respect to thermal simulators.
Moreover, the thermal exploration of 3D MPSoCs with
active cooling (liquid) modeling shows even larger speed-ups
(more than 1000×) due to power extraction and thermal
synchronization overhead in thermal simulators [6, 7, 17].
R conv
Convective thermal resistance
R heat Thermal resistance of passive material layers
Variable thermal conductivity of Si
G si (dependent on T)
t Si baseline thickness
R b Thermal resistance of interconnection layers
A Area of high power dissipation intensity
h Heat transfer coefficient of fluid
A t Total surface area
V Volumetric flow rate
P Density
c p Heat capacity
Then, Figure 5 outlines the emulated microchannels liquid
cooling and TSVs layout. Thus, the microchannels are
distributed uniformly on each tier and the fluid flows through
each channel with the same flow rate, which can be modified at
run-time by the OS, and do not intersect with TSVs.
V. EXPERIMENTAL SETUP AND RESULTS
The proposed HW/SW thermal emulation framework for
2D/3D MPSoCs has been compared with different SW thermal
libraries for 2D/3D MPSoCs [6, 7, 17], while running intensive
MPSoCs processing kernels. The obtained results are depicted
in Figure 6 and show significant speed-ups with respect to
state-of-the-art temperature estimation frameworks [14,15, 17].
In particular, these results outline that the proposed modeling
approach for MPSoC HW/SW thermal emulation scales
significantly better than state-of-the-art SW simulators for
3-core 2D 4-core 2D 8-core 2D 8-core 3D 8-core 3D
MPSoC[14] MPSoC [15] MPSoC [17] MPSoC [17] MPSoC [17]
with liquid cooling
Fig. 6. Simulation speed-ups of the proposed HWSW thermal emulation
framework for transient thermal analysis with respect to state-of-the-art
2D/3D thermal simulators
In the second set of experiments it has been evaluated the
accuracy of the proposed thermal model with respect to
transient thermal analysis of 3D liquid cooling-based
MPSoCs. To this end, it has been compared the temperature
evolution at the junction (cf. Equation 2) using finite-element
simulations [13] (red straight line) with the estimated
temperature of the linear model of Figure 4 (yellow dashed
line). The results are shown in Figure 7, which indicates that
the variations between both types of simulations are less than
1.5% on average (encircled area). Furthermore, while the
proposed emulation framework using the simple liquid
cooling model for straight channels can calculate the junction
temperature evolution in the order of few milliseconds, the
detailed finite-element simulation can take few hours. Thus,
it illustrates the potential of linear thermal estimation
methods for simple geometries of liquid microchannels using
a laminar flow regime.
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Fig. 7. Temperature evolution at the junction in liquid-cooling based
systems using finite-element simulation and the proposed model for straight
liquid cooling channels
All in all, these experiments outline the potential benefits of
the proposed HW/SW thermal emulation framework to
explore the design space of complex thermal management
policies in 2D/3D MPSoCs, compared to exiting methods
based on SW cycle-accurate simulators or finite-elements
simulation, which suffer from very important speed limits for
long simulations, necessary to achieve representative
transient thermal analysis of real systems.
VI. CONCLUSIONS
2D and emerging 3D MPSoC architectures have been
proposed as a promising solution to exploit the available area
in forthcoming computing systems. In this paper I have
presented a new HW/SW FPGA-based emulation framework
that enables the rapid analysis of run-time thermal behavior
in 2D/3D MPSoCs with active liquid cooling. The
experimental results have shown that the proposed
framework obtains detailed transient thermal exploration with
a speed-up of more than 1000× with respect to cycle-accurate
MPSoC simulators, even more when active (liquid) cooling
effects are considered in the overall thermal system analysis.
Furthermore, almost no loss in thermal estimation accuracy
(less than 3%) is experienced with respect to classical (and
very time-consuming) finite-element simulations. Overall,
this HW/SW thermal emulation approach is a promising
mechanism to perform long-time transient behavior
characterization in 2D and 3D MPSoC stacks.
ACKNOWLEDGMENT
The author would like to thank Ayse K. Coskun and Prof.
Tajana Simunic Rosing from UCSD, Prof. Luca Benini at
Bologna University, and the group of Advanced Packaging
Technologies at IBM Zürich for their useful feedback and
inputs in the validation of the 3D thermal modeling and
liquid cooling technology. This work has been supported in
part by the Swiss NanoTera NTF Project - CMOSAIC, and a
FPGA donation of the OpenSPARC University Program of
Sun Microsystems.
REFERENCES
[1] D. Pham et al., Design and Implementation of a First-Generation
Cell Processor., Proc. ISSCC, 2005.
[2] P. Kongetira et al.,Niagara: A 32-way multithreaded SPARC
processor., IEEE Micro, 2005.
[3] Tilera Corporation, Tilera’s 64-core architecture, 2008,
www.tilera.com/products/processors.php
[4] W. Davis, et al., Demystifying 3D ICs: The Pros and Cons of Going
Vertical. IEEE Des&Test, 2005.
[5] M. Healy, et al., Multiobjective microarchitectural floorplanning for
2D and 3D ICs. IEEE Transactions on CAD, 2007
[6] K. Skadron et al., Temperature-aware microarchitecture: Modeling
and implementation (Hot-spot simulator), IEEE TACO, 2004
[7] G. Paci et al., Exploring temperature-aware design in low-power
MPSoCs, Proc. DATE, 2006.
[8] M.-N. Sabry, High-precision thermal models, IEEE TCPT, 2005.
[9] Cadence Palladium II, 2005. http://www.cadence.com.
[10] ARM integrator AP, 2004. http://www.arm.com.
[11] Emulation Engineering. Zebu models, http://www.eve-team.com.
[12] T. Brunschwiler et al., Direct liquid-jet impingement cooling with
micron-sized nozzle array and distributed return architecture. Proc.
ITHERM, 2006.
[13] T. Brunschwiler, et al., Interlayer cooling potential in vertically
integrated packages, Microsyst. Technologies, 2008.
[14] F. Mulas et al., Thermal Balancing Policy for Streaming Computing
on Multiprocessor Architectures, Proc. DATE, 2008.
[15] D. Atienza, et al., A fast HW/SW FPGA-based thermal emulation
framework for multi-processor system-on-chip. Proc. DAC, 2006.
[16] B. Richard, et al., Numerical Analysis, Brooks Cole, 2000.
[17] A.K. Coskun, et al., Dynamic Thermal Management in 3D
Multicore Architectures, Proc. DATE, 2009.
[18] A. Jerraya, et al. Multiprocessor SoCs. Morgan Kaufmann, 2005.
[19] G. Braun, et al. Processor/memory co-exploration on multiple
abstraction levels. Proc. DATE, 2003.
[20] P. S. Magnusson, et al. Simics: A full system simulation platform.
IEEE Computer, 2002.
[21] P. Paulin, et al. Stepnp: A system-level exploration platform for
network processors, IEEE Des&Test , 2002.
[22] Coware, Convergence and Lisatek product lines, 2006.
http://www.coware.com
[23] ARM, PrimeXSys platform architecture and methodologies, white
paper, 2005, http://www.arm.com/
[24] Heron Engineering, SoCemulation, 2004, http://www.hunteng.co.uk
[25] M. D. Nava, et al., An open platform for developing MPSoC, IEEE
Computer, 2005.
[26] Y. Nakamura, A fast HW/SW co-verification method for SoC by
using a C/C++ simulator and FPGA emulator with shared register
communication, Proc. of DAC, 2004.
[27] Mentor Graphics, Platform express and primecell, 2005,
http://www.mentor.com/
[28] Synopsys, Realview Max-sim ESL Exploration Framework, 2004,
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[29] T.-Y. Chiang, et al, Thermal analysis of heterogeneous 3-D ICs
with various integration scenarios, Proc. of IEDM, 2001.
[30] A. Rahman, et al., Thermal analysis of three-dimensional integrated
circuits, Proc. of IITC, 2001.
[31] P. Leduca et al., Challenges for 3d IC integration: bonding quality
and thermal management, Proc. of IITC, 2007.
[32] K. Puttaswamy, et al., Thermal analysis of a 3d die-stacked highperformance
microprocessor, Proc. of GLSVLSI, 2006.
[33] A. Jain, et al., Thermal modeling and design of 3D integrated
circuits, Proc. of ICTTPES, 2008.
©EDA Publishing/THERMINIC 2009 55
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Thermal Analysis of Hot Spots in Advanced 3D-
Stacked Structures
C. Torregiani 1 , B. Vandevelde 1 , H. Oprins 1 , E. Beyne 1 , I. De Wolf 1,2
1 IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium
2 MTM Dept., K.U.Leuven,Kastelpaark Arenberg 10, B-3001 Heverlee, Belgium
Email: cristina.torregiani@imec.be
Abstract- 3D integration architectures for microelectronic
circuits have attracted much interest in the recent past, due to
their capabilities for more efficient device integration and
faster circuit operation. This type of assembly is formed by
bonding multiple active layers through a dielectric material,
and employs through-silicon vias for electrical interconnection.
In this work we present the thermal analysis of a typical 3Dstack,
performed by finite element simulations. The effect of the
variation of various parameters on the area of influence of a hot
spot and on the overall temperature in the stack has been
analyzed. We have also investigated the thermal impact of
copper studs in the dielectric: the results suggest that Cu studs
with a small pitch in the glue can efficiently reduce the
temperature in the Si dies.
I. INTRODUCTION
Thermal management for electronic devices, circuits, and
packages has become an issue of concern during the last
years, and even more of a concern for vertically integrated
stacked structures. The determination of the temperature
distribution in 3D systems has become an increasingly
important need: the increase in power dissipation per die and
in the number of stacked dies, together with the use of
poorly conductive interface layers limits the dissipation of
heat generated by electronic devices [1-5]. The problem is
made worse by the fact that the power in electronic systems
is usually dissipated in localized regions (so called hot
spots). This causes an increase in thermal resistance due to
heat spreading effects, and it makes the temperature
distribution non-homogeneous over the dies.
The advanced 3D stacked die assembly considered in this
paper can be simply described as a stack of dies separated by
interface layers. The assembly is attached to a package with
a specified thermal resistance. The ambient conditions define
the case-to-ambient thermal resistance.
II. METHODOLOGY
In this paper a vertically stacked structure is modeled
using a finite element code [6]. The structure is composed by
three silicon dies including the back-end-of-line (BEOL)
layers. The active layers are attached to each other by a
polymer, functioning both as glue and dielectric. The reason
why the BEOL is also modeled as an additional layer is that
it has a relatively low thermal conductivity, which is mainly
dominated by the low thermally conductive dielectric [7]. A
fixed reference temperature, chosen to be 0 0 C, is considered
as boundary condition at the back side of the stacked
structure, while the four sidewalls and the top surface are
considered adiabatic. These boundary conditions can be
viewed as a first order approximation of a real stack
embedded in a poorly thermally conductive path at the top
and the side, and glued through a bottom package resistance
to a heat sink. Figure 1 shows the FEM mesh. Table I lists
the thickness and thermal properties of each layer. The
silicon thermal conductivity has been considered constant,
with its value fixed at the room temperature value. For the
temperature excursions considered here the error introduced
by using this approximation is small [8].
Fig. 1. 3D model of the stacked structure.
TABLE I
THICKNESS AND THERMAL PROPERTIES OF THE LAYERS COMPOSING THE STACK
Layer thickness (μm) Thermal conductivity,
k (W/mK)
Die 1 100 150
Die 2 20 150
Die 3 20 150
BEOL 8 0.5
Polymer 1 0.3
III.
RESULTS
A. Hot spots thermal footprint and impact of parameters
variation
The study evaluates the steady state thermal performance
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of a 2.5 x 2.5 mm 2 wide stack when a power of 0.1 W is cylindrical shape, due to the presence of a resistive interface
dissipated over an area of 100 x 100 μm 2 (hot spots), located below both levels. In these cases the temperature drops
at different die levels and at different positions on the dies. across the interface layers, and there is a limited thermal
The effect of the variation of several dimensional and effect on the bottom die.
physical parameters has been investigated. The study
quantifies the thermal impact of a variation in thermal
resistivity of the interface layers (such a variation may be
due to a change in the layer’s material properties and/or of
its thickness), the variation in the die thickness, and the
thermal impact of the presence of a package.
The simulation results indicate that the temperature around
a hot spot is distributed in a typically bell-shaped profile,
with a characteristic radius of influence (or “thermal
footprint”) dependent on the parameters mentioned. The
temperature profile due to the single hot spot is centered in a
narrow region on the level where the power is dissipated,
while it spreads over larger regions on the other levels. The
interference of multiple hot spots can be inferred by the
superposition principle, if a linear problem (i.e. temperatureindependent
thermal conductivity and non-convective
boundary conditions) is considered.
Figure 2 shows the local temperature increase at different
vertical positions in the stack for power dissipated in
different dies, and assuming a perfect cooling at the bottom
of the stack. The study clearly indicates that the thermal
impedance of the structure is dominated by BEOL and the
bonding layers.
Fig. 3. Temperature contour bands in the stack when the hot spots located in
different dies (die 3 to 1, top to bottom) are separately active. The horizontal
black lines show the width of the hot spot in each level.
Fig. 2. Left: structure modeled. Right: local temperature increase sampled at
different vertical positions in the stack. The path plots are taken along the
lines indicated in the left figure.
The temperature contour bands in the stack are shown in
figure 3 for the three cases reported in figure 2. The images
emphasize the difference in the radial geometry of the
temperature field for the three cases. When power is
dissipated in die 1 (bottom image of fig. 3) the heat spreads
in an elliptical distribution to the ideal heat sink; the effect of
this hot spot on the top dies is limited. When a hot spot is
activated in the middle or the top die (middle and top
images), the temperature distribution approximates rather a
It is also observed that the presence of a resistive layer
below the level in which the power is dissipated causes a
broadening of the temperature field.
In order to quantify this effect we show in figure 4 the
thermal footprint of the hot spots. In this figure the radius of
influence is defined as the half width at half maximum
(HWHM) of the temperature distribution.
The graphs show the temperature profile variation when
the thickness of the resistive layers, BEOL and polymer, is
varied. The “thin layers” case corresponds to the nominal
values of the interface layers thickness as given in table I
whereas in the “thick layers” case both BEOL and polymer
are 10 μm thick. It can be noticed that the largest footprint is
found on the top die. A change in the thickness of these
resistive layers causes both a higher peak temperature and an
enlargement of the hot spot thermal footprint, due to
spreading in the die located above them.
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Fig. 5. Temperature contour bands for a hot spot active in Die 1 and
different boundary conditions at the bottom of the structure. Top picture:
perfect cooling; middle and bottom picture: resistive package with a
resistance of 0.3 and 1.3 K/W, respectively.
Fig. 4. Temperature profile as a function of distance around a hotspot
dissipating 0.1W of power in one of three possible locations: top die/middle
die/bottom die. The hot spot thermal footprints (HWHM) for the two cases
thin/thick layers are indicated by dashed arrows.
Since real electronic assemblies are mounted on a
package, an external (bottom) resistance mimicking the
package resistance has also been considered in the study.
R1 is the package thermal resistance between die 1 and the
heat sink. The presence and magnitude of the package
resistance causes an overall increase in temperature in each
die, a larger hot spot thermal footprint, and changes the
geometry of the temperature distribution – these effects are
similar to the ones illustrated in the previous figures.
B. Hot spots interaction
Since in a typical chip stack more than one hot spot may
be active simultaneously, it is of interest to explore their
interaction, both at the same die level (in-plane die
interference) as well as for hot spots located at different
vertical positions (die to die interference). For this study a
3D FEM model has been considered. The graphs in figure 6
show the in-plane die interaction of two hot spots located on
the stack upper level (die 3); the two hot spots have the same
size (100 x 100 μm 2 ) and in each one a power of 0.1 W is
dissipated. A perfect cooling at the bottom of the stack is
assumed. Figure 6a shows how the maximum die
temperature depends on the distance between the two active
hot spots. The variable considered here is the ratio r between
the hot spots distance and their diameter (r = D/HS). When
the hot spots are distant (r = 10) there is little interaction and
the peak temperature approaches the value found in the case
of non-interacting hot spots (i.e. the case in which only one
hot spot is active). As the hot spots move closer their
temperature fields start to interfere; if we consider the
interference distance as the distance at which the peak
temperature increases 10% with respect to its asymptotic
value, for this structure r = 3 marks the interference distance.
This appears clearly in figure 6b, where we report the
temperature variation along the hot spots horizontal plane for
some r-values of interest. It is worth noticing that, since the
superposition principle holds, it is possible to obtain the
curves in the figure by adding up the single curves that
pertain to each hot spot. A similar operation can give the
resulting peak temperature when the hot spots are
simultaneously active in different vertical levels.
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C. Effect of copper vias
In the IMEC approach (figure 8), a 3D-die stack is built
by using through-silicon Cu vias (TSVs) and a polymer
material to fill the gap between the dies [4, 7, 9].
Interconnections between dies are made using the vias
(nails) which have electrical functionality but also a thermal
advantage since the copper thermal conductivity is three
orders of magnitude higher than the thermal conductivity of
the polymer glue.
Fig. 8. Right: schematic view of IMEC`s 3D-SIC chip stacking approach
with hybrid Cu/dielectric bonding. In this figure and in the study reported,
BCB has been assumed as the bonding dielectric. Left: SEM image of a TSV
in a IMEC`s 3D stack.
Fig. 6. Interaction of two hot spots located on the same level (die 3). (a) The
graph reports the temperature measured in the center of hotspot 1, when the
ratio (r) between the hotspots separation and their diameter is varied. (b)
Temperature as a function of the distance from the hotspot 1 center, for
different values of r.
The meaning of the interaction distance can be better
understood when looking at the flux plots in figure 7. For r =
7 the hot spots spreading angles - visualized through the heat
flux lines - almost do not intercept. On the other hand, an
interaction between the respective temperature fields start to
be visible when the power sources are so closely spaced (r =
3) that their spreading angles overlap.
Fig. 7. Heat flux emanating from two hot spots active in die 3, for two
significant values of r.
The presence of TSVs in the polymer layer alters its
thermal properties: a decrease in thermal resistance of the
polymer, and thus in the overall temperature, is expected in
this case. It has been previously demonstrated [6] that, for
the case of a homogeneous power dissipation in stacked dies,
the presence of copper bumps in the polymer accounts for
the major part of the reduction in the thermal resistance in a
stack. This suggests the use of dummy Cu studs in the
polymer as a thermal management aid.
In order to quantify the impact of dummy copper on the
stack temperature a series of FEM simulations have been
performed. We have used a 2D axisymmetric model of a 2.5
x 2.5 mm 2 wide structure with 5 μm diameter Cu studs
placed in the interface layer - BCB in this case (figure 9 a).
A package resistance R1 = 1.3 K/W has been considered for
all simulations.
At first, a parametric study has been performed in which
the polymer thickness has been varied while keeping the Cu
studs pitch fixed. Figure 9b reports the results and
demonstrates that the presence of Cu studs with a
sufficiently small pitch affects significantly the thermal
resistance of the polymer layer. The copper provides for an
effective heat conduction path (fig. 10), and reduces
considerably the overall stack temperature. The maximum
temperature in a stack with dummy Cu studs is found to be
almost independent on the polymer thicknesses when the
studs pitch is small, thus the copper thermal impact is more
significant for thicker BCB layers. A similar conclusion can
be drawn from figure 9c, where the copper impact as a
function of bumps pitch is explored for two different BCB
thicknesses.
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The maximum temperature reached on a given die in the
stack and the extent to which the hotspot influences the
surrounding plane is also influenced by the die thickness.
Figure 11 reports the variation in the peak temperature in die
3 for a hot spot located in the same die.
Fig. 11. Peak temperature variation in die 3 as a function of the die
thickness.
VI. CONCLUSIONS
We have presented the thermal analysis of a typical 3-D
stack solution for microelectronics circuits with localized
heat sources (hot spots). The analysis aimed at quantifying
the impact of various parameters on the hot spots thermal
footprint on the temperature distribution in the stack. The
interaction between hot spots located on the same die level
has also been analyzed. The potential thermal impact of the
presence of dummy Cu in the dielectric glue has been
demonstrated.
Fig. 9. (a) Model used to study the thermal impact of Cu studs in BCB.
(b) Peak temperature in the top die (die 3) as a function of polymer
thickness. P is the studs pitch. (c) Peak temperature in the top die as a
function of the studs pitch for two different polymer thicknesses.
REFERENCES
[1] M. Rencz, “Thermal issues in stacked die packages,” 21 st IEEE
SEMI-THERM Symposium, pp. 307-312, March 2005.
[2] S. Pinel et al, “Thermal modeling and management in ultrathin chip
stack technology,” IEEE Trans. On Components and Packaging
Technologies, vol. 25, Issue 2, pp. 244-253, June 2002.
[3] S. Im and K. Banerjee, “Full chip thermal analysis of planar (2-D)
and vertically integrated (3-D) high performance ICs,” IEDM Tech.
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[4] E. Beyne, “The rise of the 3 rd dimension for system integration,”
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[5] The International Technology Roadmap for Semiconductors
(ITRS), ed. 2008. Available for free downloading, url:
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[6] Msc. MARC, commercially available software, url:
http://www.mscsoftware.com.
[7] L. C. Chen, B. Vandevelde, B. Swinnen, E. Beyne, “Enabling
SPICE-Type modeling of the thermal properties of 3D-stacked
ICs,” Electronics Packaging Technology Conference, pp. 492-499,
December 2006.
[8] V. Palankovski, S. Selberherr, “Thermal models for semiconductor
device simulation,” High Temperature Electronics, pp. 25-28, July
1999.
[9] B. Swinnen et al, “3D integration by Cu-Cu thermo-compression
bonding of extremely thinned bulk-Si die containing 10 μm pitch
through-Si vias,” Int. Electron Devices Meeting, pp. 1-4, December
2006.
Fig. 10. Structure with Cu studs built in a 3 μm thick BCB with a pitch of 15
μm. Top: Model of the structure. Bottom: temperature distribution.
©EDA Publishing/THERMINIC 2009 60
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Thermal Issues of Solar Irradiation Sensor
B. Plesz, Á. Földváry, E. Bándy
Budapest University of Technology and Economics, Department of Electron Devices
Goldmann György tér 3
1111 Budapest, Hungary
Abstract- Nowadays the importance of solar cells and R&D in
this field is steadily increasing. The most important parameter
of a solar cell is the generated power, which can be enhanced by
use of solar tracking. For a correct determination of the
tracking system’s efficiency an irradiation sensor is necessary,
because the irradiation from the sun changes constantly. This
sensor device is placed on the tracker’s frame and transfers the
intensity data to a monitoring system. The sensor developed for
irradiation measurement must have accuracy and a reliable
construction under outdoor use conditions (between the
temperature values of -20°C and 80°C). The sensor is based on
a photoelectric cell, and incorporates a read out circuit for
providing steady short circuit conditions for the cell as well as
for signal amplification. Thermal tests (HTS, LTOL) were
accomplished in a climate chamber in the temperature range of
-20 to 80 °C in steps of 10°C. To determine the fundamentals of
the thermal dependence of the sensor cell spectral response
measurements under varying temperatures were performed.
I. INTRODUCTION
The solar irradiation measurement is of importance to
most engineering applications, which involve photovoltaic
devices. Solar irradiation data is needed in fields like
agriculture, astronomy, atmospheric science, climate change,
health, hydrology, oceanography, photobiology and at last,
but not to be ignored renewable energy.
In our case it will be used for an accurate determination of
the Heliotrex solar tracking system’s efficiency, which is
necessary because the irradiation from the Sun changes
constantly [1]. This sensor device will be placed on the
tracker’s frame and transfers the intensity data to the
monitoring system to evaluate the overall efficiency of the
Heliotrex solar tracker over a longer period of time e.g. one
year, so the sensor developed for irradiation measurement
must have an adequate accuracy and a reliable construction
under outdoor conditions.
This paper describes the design of a low cost photoelectric
irradiation sensor and its thermal characterization. The
irradiation sensor developed by us compared to industrial
ones is less expensive, has a simple construction and with
help of an electronic circuit the output signal can be directly
measured and digitalized. In the following paper we present
the solar cell parameter’s temperature dependence [2][3] and
the connection between the thermal behaviour of the short
circuit current and solar cell technology used.
II.
THEORETICAL BACKGROUND
Solar irradiation instrumentation used today can be of four
basic types: thermo-mechanical, calorimetric, thermoelectric
and photoelectric. Of these, thermoelectric and photoelectric
are the most common sensors in use today. Photoelectric
sensors normally use silicon solar cells and measure their
short circuit current. Such detectors have the advantage of
being simple in construction [4].
The Heliotrex system’s irradiation sensor belongs to the
photoelectric type. The construction of the photoelectric
irradiation sensors is very simple, the sensor is a solar cell
which must be used in short circuit condition, this way the
light intensity can be converted directly to an electrical
signal. In addition this circuit is supplemented with common
signal processing electronics.
Inaccuracy of photoelectric irradiation sensors has been
due to errors introduced by systematic, time-of-day
dependent variation in the solar spectrum, solar angle of
incidence and operating temperature [5].
In our particular case we’re not interested in the angle of
incidence, because due to tracking the sensor will be
continuously perpendicular to the sun. Most important factor
is the temperature dependence which acts as a primary
design parameter for our intensity sensor. Temperature
changes influence both signal processing circuit and solar
cell parameters.
The solar cell’s open circuit voltage and short circuit
current depends on the intensity of the illuminating light.
Theoretically we could integrate the change of open circuit
voltage for measurement of the irradiation, but the
logarithmic dependence is more complex to evaluate and in
addition the open circuit voltage is highly dependent on
temperature, -2.2 mV/°C [2].
Therefore, the device measures the short circuit of the cell
in use, because it is linearly dependent on the intensity of
light and the thermal effects are much smaller. In case of
short circuit the current of the cell is given by (1),
I
sc
= I
ph
æ
- I ç
0
e
ç
è
Rs×
Isc
m×
UT
ö Rs
× I
-1÷
-
÷
ø
R
sh
Where: I ph - photocurrent, I 0 - reverse saturation current,
R s - series resistance, R sh - shunt resistance, U T - thermal
voltage, m - diode ideality factor.
For nearly ideal solar cells under short circuit conditions the
following linear approach can be considered (2),
sc
(1)
I
sc
» I ph
(2)
©EDA Publishing/THERMINIC 2009 61
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Thermal behaviour causes some variations in the short
circuit current and thus can influence the precision of the
irradiation measurement, this is the reason why these effects
must be minimized. The temperature dependence of short
circuit current arises from the variations of diffusion length,
band gap, spectral behaviour and absorption with
temperature [6].
Relation between the diffusion length and diffusion
coefficient is (3),
L = D × τ
(3)
Where: L - diffusion length, D - diffusion coefficient,
τ - life time. Relation between diffusion coefficient and
carrier mobility µ, called Einstein’s relations (4),
k × T
D = × μ
(4)
q
where µ and τ are also temperature dependent [6].
The band gap width changes with the temperature [7], and
can be expressed with the following term (5),
2
α × T
Eg
(T) = E
g
(0) -
(5)
T + β
Where in Si: E g (0)= 1.166 eV, α= 4.73·10 -4 eV/K, β= 636 K.
The absorption coefficient near the absorption edge can be
given as a function of E g (6),
( hν ) γ
α µ -
(6)
Where: α - absorption coefficient, hν - photon energy,
γ - constant. It can be seen, that due to the temperature
dependence of E g absorption increases with rising
temperature [8].
III.
E g
INDUSTRIAL PHOTOELECTRIC SENSORS
Several industrial irradiation sensor parameters were
studied in order to investigate the desired range of
temperature dependence for our sensor. All the examined
industrial sensors had solar cell detectors and the result is
concluded Table I.
Sensor
name
EKO
ML-020
HydroLynx
M4016
IKS
Photovoltaik
ISET
Kipp&Zonen
SP-LITE2
LI-COR
LI 200SA
TABLE I
INDUSTRIAL IRRADIATION SENSOR DEVICE PARAMETERS
Overall
accuracy
[%]
Temp.
dependence
[%/°C]
Operating
temp.
[°C]
Sensitivity
[1/W/m 2 ]
±5 -10 to 50 7µV
±5 0.15 -30 to 70 80µV
±5 -25 to 80 100µV
±5 0.15 -30 to 70 100µV
±5 0.15 -40 to 65 90nA
7-9 October 2009, Leuven, Belgium
Overlooking Table I one can notice that the average
temperature stability for these devices is 0.15 %/°C and the
operating conditions are measured in the range of -30 to
70°C. Many sensors also work with very low level signals
and need additional signal transforming units to be able to
use the signal in digital systems.
IV.
EXPERIMENTAL
The device is planned for irradiation measurement. Our
irradiation sensor system is composed of two main parts:
1. Sensor cell
2. Read-out circuit which is the signal processing circuit,
with signal amplification and transmitting role.
A. The sensor
As sensor cell a self-made solar cell Fig. 1, incorporating a
simple n-p single junction structure without BSF, surface
texturing and special ARC coating is used. The raw material
for the solar cell is a sc-Si wafer, wafer type: N + /N epitaxial.
Wafer thickness is 330μm from which the epitaxial layer’s
thickness is 10μm according to manufacturer’s specification,
sheet resistance of the substrate and the epitaxial layer is
ρ N+ = 0.006 Ωcm and ρ N = 5.2 – 7.8 Ωcm, respectively. The
diffused P-layer was driven in to a depth of 1.5 µm in
oxygen, during this a dark blue coloured SiO 2 ARC coating
was formed. After the opening of the contact windows Ni
evaporation was performed with a source of 99.99 Ni wire
on hot filament. Contact Ni layer was thickened with
electroplated Ni and Cu galvanic deposition solution to a
thickness of 1 µm and 5 µm respectively. The multilayered
metal contact and the N + substrate were adopted in order to
reduce the serial resistance.
Galvanized
Cu layer
Electroless
Sn layer
B. The circuit
P
N
N+
Galvanized
Ni layer
Evaporated
Ni layer
ARC layer
Fig. 1. Cross-section of self-made solar cell
Read-out circuit is responsible for measurement and
conversion of the sensor cell’s short circuit current into a
voltage signal. The device is designed to work at 5V power,
with a maximum measurement range of 1350 W/m 2 , thus
can be incorporated into digital systems. On the output of the
measuring device a voltage value appears corresponding to
the instantaneous irradiance, in case of 1000W/m 2 the output
voltage U out = 3V, so the sensitivity is 3mV/W/m 2 . At the
selection and testing of the components used for the device,
due to outdoor use of the sensor, the thermal effects must be
regarded. This unit consists of four parts Fig. 2.
©EDA Publishing/THERMINIC 2009 62
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Solar cell
Control unit
Reference
voltage
Final stage
amplifier
Calibration
unit
Fig. 2. Block diagram of the read-out circuit
7-9 October 2009, Leuven, Belgium
which is registered as the changes in the irradiation sensor’s
output signal according to temperature. We’ve conducted
separate analysis to find out the thermal behaviour of our
sensor cell and the circuit, these test were also applied to an
industrial solar cell.
While investigating the circuit the solar cell was replaced
with a current source. This way the changes caused by the
solar cell could be ruled out and the circuit’s effective
temperature dependence could be determined. This
parameter can be defined if we measure the circuit’s output
voltage as a function of temperature Fig.4.
The most important active component is the control unit.
This unit consists of two parts, a voltage generator and a
regulator circuit Fig. 3. Compared to industrial solutions,
where small shunt resistors are used to transform the short
circuit current into a voltage signal, an active regulation is
used, which always ensures proper short circuit conditions.
Precise short circuit is adjusted by a reference voltage value.
Climate chamber
Temp.
Read-out
circuit
current
source
0.0V
W
V A
V A
OFF
V W
A
CO M
U ref
U ref
I PV cell
= I sc
U PV cell
= 0V
Fig. 4. Experimental setup for determination of the temperature
dependence of the circuit
Investigation of the solar cell is performed in a similar
manner. The photovoltaic cell is connected to the electronics
and if illuminated a measurement voltage appears on the
output of the circuit Fig. 5. As light source a Tungsram
EXN-WFL 12V 50W halogen incandescent lamp with a
colour temperature of 3000K was used.
Climate chamber
U ref
U m
→ Final stage amplifier
Temp.
PV
cell
V
W
0.0V
A
Fig. 3. Electrical diagram of the control unit
The voltage created over a measurement resistor (R 5 ) by
the short circuit current is amplified by the final stage
amplifier, because higher voltage levels can be more
precisely digitalized by commonly available devices.
Verification of the measuring device can be carried out with
the calibration unit, which sets the voltage of the final stage
amplifier.
C. Thermal testing
Both the sensor cell and the read-out circuit can be
affected by changing temperature. Similarly to the industrial
sensors the operation will be studied using different
methods. Thermal tests were performed in a climate chamber
in the temperature range -20 to 80 °C in steps of 10°C.
In order to determine the reliability of the sensor device
accelerated life tests were carried out. Thermal testing begins
with the determination of the temperature dependence,
Read-out
circuit
Fig. 5. Experimental setup for determination of the temperature
dependence of the solar cell
The second test that was carried out determined the sensor
cell’s spectral response as a function of temperature. In this
test the cell while fixed to a thermostated copper bulk was
illuminated through 8 narrow bandpass filters. The bulk’s
temperature (and solar cell’s temperature) was varied in the
range of -10°C to 80°C with a Cole-Palmer Polystat 12100-
25 type thermostat. At given temperature values the short
circuit current of the sensor cell is measured for each filter.
This way the spectral response can be determined at different
temperatures.
Third HTS (High Temperature Store) according to Mil-
Std-883 Method 1008 is performed to determine the effect
V
A
OFF
V W
CO M
A
©EDA Publishing/THERMINIC 2009 63
ISBN: 978-2-35500-010-2

on devices of long-term storage at elevated temperatures
without any electrical stresses applied. Purpose of
Stabilization bake is usually to serve as part of a screening
sequence or as a preconditioning treatment prior to the
conduct of other tests. Test condition applied to both sensor
cell and read-out circuit is condition A, specifically 75°C for
24 hours minimum [9].
Last the LTOL (Low Temperature Operating Life) test
was carried out in order to determine the reliability of the
device under low temperature conditions over an extended
period of time. It consists of subjecting the parts to a
specified bias or electrical stressing, for a specified amount
of time, and at a specified low temperature. LTOL test is
documented by JEDEC in a single standards spec, JEDEC
JESD22-A108. Test condition applied to both solar sensor
and read-out circuit is -20 °C for 24 hours minimum [10].
7-9 October 2009, Leuven, Belgium
For the self-made sensor cell we’ve experienced an
average change of 0.24 %/°C in output voltage of the
irradiation sensor (short circuit current of the sensor cell)
Fig. 7. Compared to industrial sensors these values are
almost two times higher (0.15 %/°C), for this reason
comparing spectral response and temperature dependence
measurements with an industrial solar cell (manufactured by
Siemens) were performed.
Observations in case of industrial cell’s temperature
dependence test revealed an average change of 0.11 %/°C in
output voltage Fig. 7. These values correspond to the
parameters given by the industrial irradiation measurement
devices. Based on the measurements performed we could
conclude that the cell’s short circuit current changes not only
according to temperature, but is also influenced by the
structure of the solar cell.
V. DISCUSSION
The circuit’s temperature dependence was studied first.
The reference point is a set output voltage value at T=25°C,
changes that occur will be compared to this value.
5
T=-10°C T=0°C T=10°C T=25°C
T=40°C T=60°C T=80°C
3005
4
Output voltage [mV]
3000
2995
2990
2985
2980
2975
2970
-20 -10 0,2 9,2 20 25 30 40 49,6 59,2 70 80
Temperature [°C]
Short circuit current [mA]
3
2
1
0
392 465 550 622,5 705 790 871,5 1023
Wavelength [nm]
Fig. 6. Temperature dependence of read-out circuit
This resulted in an average output voltage decrease of
0.005 %/°C with temperature Fig. 6.
Afterwards the sensor cell’s temperature dependence was
investigated.
12
Fig. 8. Spectral response of self-made solar cell
T=-10°C T=0°C T=10°C T=25°C
T=40°C T=60°C T=80°C
Uout, Siemens cell [mV]
Uout, our cell [mV]
10
Output voltage [mV]
1800
1700
1600
1500
1400
1300
1200
-20 -10 0 10,2 20 25,5 30 40,6 50 60,5 70,7 80
Temperature [°C]
Short circuit current [mA]
8
6
4
2
0
392 465 550 622,5 705 790 871,5 1023
Wavelength [nm]
Fig. 9. Spectral response of Siemens cell
Fig. 7. Temperature dependence of self-made and Siemens solar cell
The sensor cell made by us is because of the N + substrate,
incorporated to ensure low series resistance, only sensitive
©EDA Publishing/THERMINIC 2009 64
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up to the spectral region of ca. 900 nm. Compared to this the
industrial cell has a different structure (P type wafer, N-
diffusion and BSF) and is more sensitive in the IR-domain,
because the minority charge carriers generated at the backend
of the solar cell can be collected if within the diffusion
length.
As Fig. 8 and Fig. 9 indicate, the spectral response of the
sensor cell is more influenced by temperature change, than
in the case of the Siemens cell. Since in both cases the
diffusion lengths for the minority carriers are higher than the
width of the effective charge collection regions, the effects
from temperature dependence of the diffusion length are
neglectable. Thus most of the current increase is caused by
the changes in the absorption spectrum. The wide P-region
in the Siemens cell absorbs already most of the incoming
light, while the shallow N region (ca. 10 um) can absorb
only a small part of the IR-region, where the absorption
coefficient is low. With rising temperature the absorption
coefficient increases, which leads to higher absorption in the
near IR-region, and thus a higher short circuit current, than
in case of the Siemens cell, where the increase can be seen
only in the regions of beyond 1000 nm.
Result of the HTS concluded that electronics of the sensor
device will not be affected by storage at high temperature. In
case of the solar cell we’ve experienced a 0.12% change,
which can originate in the illumination imprecision. With a
good approximation we can state that the sensor cell’s HTS
test did not cause any change in the output voltage, contrary
to the preliminary tests which revealed a decrease of the
short circuit current. The reason could be the defective
contact metal layer deposition, where the resistance of the
metal-semiconductor interface is increased or because there
is a difference between the thermal expansion coefficients
causing the metal layers to peel off.
After executing the LTOL test we can deduce that the
electronic circuit will not be affected by low temperature
operation, the measured deviation is 0.06%. The sensor cell
after the LTOL test produced a 0.27% change, which as in
the previous case can originate in the illumination
imprecision. With a good approximation we can conclude
that after this test the sensor cell’s output did not change.
7-9 October 2009, Leuven, Belgium
concluded, that our solution which uses an N + layer in order
to reduce the serial resistance, is not an appropriate
approach, because its higher sensitivity of the spectral
response to temperature variations results in a higher
temperature dependence. To minimize temperature
dependence solar cells with nearly ideal spectral response
should be used. From the spectral response of the sensor cell
it can be also seen that the future thin film crystalline silicon
solar cells favourized by some manufacturers might suffer
from the same temperature behaviour.
ACKNOWLEDGMENT
This work was supported by the project PVMET-08 of the
Hungarian Technology Program.
REFERENCES
[1] P. Sági, B. Plesz, and V. Timár-Horváth, “Building the Heliotrex
Solar Tracking System”, Procs. of IWTPV’08 Prague, pp. 101-106,
March 2008.
[2] Priyanka Singh, S.N. Singh, M. Lal, and M. Husain, “Temperature
dependence of I–V characteristics and performance parameters of
silicon solar cell”, Elsevier Solar Energy Materials & Solar Cells,
vol. 92, pp. 1611-1616, August 2008.
[3] M.A. Mosalam Shaltouta, M.M. El-Nicklawy, A.F. Hassan,
U.A. Rahoma, M. Sabry, “The temperature dependence of the
spectral and efficiency behavior of Si solar cell under low
concentrated solar radiation”, Elsevier Renewable Energy, vol. 21,
pp. 445-458, November 2000.
[4] D. Yogi Goswami, Jan F. Kreider, “Principles of solar engineering”,
Taylor & Francis, 2000, ISBN 1560327146, pp. 67.
[5] D.L. King, W.E. Boyson, B.R. Hansen, and W.I. Bower, “Improved
accuracy for low-cost solar irradiance sensors”, Sandia National
Laboratories, Albuquerque, New Mexico, USA, Presented at the
2nd World Conference and Exhibition on Photovoltaic Solar Energy
Conversion, Vienna, July 1998.
[6] E. Radziemska, “The effect of temperature on the power drop in
crystalline silicon solar cells”, Elsevier Renewable Energy, vol. 28,
pp. 1-12, January 2002.
[7] T. Markvart , L. Castaner, “Practical Handbook of Photovoltaics:
Fundamentals and Applications”, Elsevier Science, ISBN
1856173909, pp. 99, October 2003.
[8] S. M. Sze, “Physics of Semiconductor Devices”, WileyBlackwell,
3 rd ed., ISBN 0471143235, pp. 52 - 53, November 2006.
[9] MIL-STD-883E, “Test method standard microcircuits”, 1996.
[10] JESD22-A108, “Temperature, Bias, and Operating Life”, 2000.
VI.
CONCLUSION
In this paper a solar irradiation sensor for usage in solar
tracking systems was presented. The sensor is based on a
photoelectric cell, and incorporates a read-out circuitry for
providing steady short circuit conditions for the cell as well
as for signal amplification.
Read-out circuit’s electronics has a stable thermal
behaviour. After performing HTS and LTOL accelerated life
tests the output signal value didn’t change essentially. On the
other hand the sensor cell has varied it’s short circuit current
when subjected to thermal tests.
These procedures revealed that mainly because of its
structure the sensor cell has a higher temperature
dependence than the industrial cell it was compared to
(Siemens). From spectral response measurements it can be
©EDA Publishing/THERMINIC 2009 65
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7-9 October 2009, Leuven, Belgium
Thermal Simulation and Package Investigation of
Wireless Gas Sensors Microsystems
Andrea Paoli 1 , Lucia Seminara 2 , Daniele D. Caviglia 1 , Alessandro Garibbo 2 , and Maurizio Valle 1
1 Department of Biophysical and Electronic Engineering- University of Genoa,
Via Opera Pia 11/a, 16145 Genoa, Italy
2 SELEX Communications S.p.A. - Via Pieragostini 80, 16151 Genoa, Italy
Abstract - Gas sensor arrays based on metal oxides
operating at high temperature are commonly used in
many application fields. They can operate on different
principles and each sensor may show very different
responses to the individual gases in the environment.
Data coming from the array can be merged for reliable
gas detection. One point which is common to the
different sensors types is that the atmosphere to be
sensed must flow on or through the sensor itself. This
work investigates air flows in gas sensor packages, and
proposes a new package to improve gas exchange
through natural convection, aiming to allow the gas
detection in the case of very small gas concentrations.
The study is based on multiphysics Finite Element
Method simulations using a commercial software tool.
I. INTRODUCTION
Gas sensors can be used in several applications like
standard fire alarm, Wireless Sensor Networks and
monitoring environmental conditions [7] [8]. As chemical
gas sensors are based on chemical reactions between the
sensor itself and the molecules of the analyzed gas, the
detection of gas is possible only if the desired molecule
comes in contact with the sensing material [1]. This is why
the package of a gas sensor needs apertures to let the gases
enter and react with the sensing elements. However, to
avoid damages to the sensor, it is necessary to eliminate the
particles and relatively big objects by filtering the air
entering into the sensor.
The transport of a passive tracer in the atmosphere may
occur either through molecular diffusion from the higher
concentration zone to the lower concentration zone and/or by
advection by the air flow. The latter process is much faster
than diffusion and needs to be optimized to achieve a higher
sensor’s efficiency by increasing the probability of gas
molecules impact on the sensor’s surface per unit time.
Chemical gas sensors work at high temperature (typically
around 300-400°C) which triggers a natural convection flow
in the atmosphere surrounding the sensing element. Though
such a flow can help transporting the substance to be
detected by interacting with the outside air through the
package holes, however it is necessary that the natural
convection forces the air in the sensor to be expelled and
allows new air to come in. This process of air exchange is
strongly related to the shape and position of package
apertures and to the orientation of the package.
Fig. 1. Standard TO8 package:
a) base with the suspended sensors array; b) cap with hole and grid
on top
The classic TO8 package used for gas sensors is a metal
package made by a metal base with some pins and a
cylindrical metal cap. The diameter and the height of TO8
are about 13mm. The cap on top has a hole of 7mm
diameter and a grid to allow gas propagation in the package.
The grid does not affect significantly the gas diffusion
process but creates a relatively strong resistance to air flows
compared with an open hole.
The reference sensor used in this work is a nanostructured
material based sensor deposited on an alumina substrate.
The alumina is about 6mm x 6mm x 300µm and has metal
traces on both sides. On one side a platinum heater is placed,
while on the other side a platinum thermometer is located
along with four fingered contact areas where different metal
oxides are deposited by a Pulsed Microplasma nanoparticles
source [5] [6]. Metal oxides react in different ways with
various gases, reducing or increasing their electrical
conductance, which is measured and processed in order to
ascertain whether some gases are present in the atmosphere
and measure their concentrations [2] [3] [4]. This sensor
works at about 600K and this temperature has been
employed for investigation in this work. To avoid problems
due to different thermal expansion of various materials and
to simultaneously provide a suitable thermal insulation
preventing excessive energy consumption in the heater, the
alumina substrate is suspended in the package by bonding
wires.
II. SIMULATION METHOD
As explained earlier, this work aims at studying natural
convection within the package with the goal to propose a
new package with optimized apertures that improve the air
exchange in all orientations. An optimization of the air
exchange between the environment and the atmosphere
inside the cap becomes necessary for being able to detect
©EDA Publishing/THERMINIC 2009 66
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very small gas concentrations (parts per million or lower).
As a matter of fact, if gas concentrations are very low
sensors risk to detect nothing for a long period of time.
Optimizing the air flow through package apertures should
provide higher sensor’s efficiency by helping the few gas
molecules in the atmosphere to reach the sensor’s surface
and to be detected.
Multiphysics finite elements (FE) simulations are used to
model the air flow within the package, and the main
parameters considered to evaluate the performance of the
package are the average air flow entering and exiting the
package. Simulations are carried out using Comsol which is
a commercial multiphysics simulator with an extensive
library of predefined equations and material properties.
The main problem with FE simulations of natural
convection is that it is difficult to get convergence. For
convergence it is better to have a homogeneous meshing on
the whole simulation domain. The mesh must be quite fine
with mild density to adapt to the smaller structure and to
avoid an excessively large number of variables. Some
approximations are needed to reduce the geometry to a twodimensional
domain as a three dimensional model would be
computationally too heavy for a common workstation. The
two-dimensional approximation is achieved by simulating
only a slice of the system and then extend results to the
whole system using symmetry. Two positions of the
package, with pins on bottom and with pins on top, have
been analyzed. In the analyzed sensor, the alumina chip is
suspended by the bonding wires to avoid problems due to
heat sinking and thermal expansion of different materials.
Bonding wires have been neglected in simulations because
their size is very thin compared with sensor and package.
The model includes the alumina, the package with a slice of
the grid, and a volume of air located inside and outside the
package. The heater power is simulated by a simple
mathematical relation that expresses the power dissipated
point by point within a thin portion of the alumina block.
The temperature control is mathematically performed
comparing the desired temperature with the average
temperature recorded from alumina side.
Due to convergence issues, it is necessary to run transient
simulations, evaluate it manually and obtain a stationary
solution when the initial transient has been exhausted and the
distribution of temperature and air velocity is constant. It is
important in this respect to note that a stationary solution is
to be expected, as the Rayleigh number R a , i.e. the
dimensionless parameter controlling thermal convection,
attains relatively low values. More precisely, for an infinite
layer of fluid of thickness D, characterized by thermal
diffusivity k, kinematic viscosity ν, coefficient of thermal
expansion α, the Rayleigh number R a reads:
R a = g α D 3 (T 1 - T 2 ) / k ν , (1)
where T 1 is the temperature of the lower hot boundary and T 2
is the temperature of the upper cold boundary. Though the
geometry of the present configuration differs from an infinite
layer due to the presence of the confining cylinder, however,
the use of the above definition leads to a simple estimate of
R a , which may provide some qualitative suggestion on the
nature of thermal convection. In fact, the estimated values
7-9 October 2009, Leuven, Belgium
of R a range about few tens of thousands. It is then reasonable
to expect that convection keeps laminar and convection cells
are steady. On the other hand, one may estimate a Reynolds
number
R e (≡U D / ν) (2)
with U scale for the flow velocity. As discussed below, U
does not exceed few cm/s, hence R e ranges about few tens,
an estimate which confirms the laminar picture.
The results also strongly depend on external air flows.
However, such flows are neglected here, as they are
unpredictable. If the sensor is placed inside a cabinet, as
done most of the times, external air flows are not very strong
and in that event the model presented here approximates the
real situation very well.
III. SIMULATION RESULTS
First set of simulations, modeling the classical TO8 sensor
package without modifications, shows that the air flow is
very low, when the package is vertical “face down”
compared with the package “face up”. In fact, if the hole in
the package is on the bottom side only and the heater is in
the upper part, the hot air stands still in the upper part of the
package where the heater continues to heat it and hence no
free convection is possible. In the simulation results, shown
in Fig. 3 and Fig. 4, the color on the surface is proportional
to the temperature point by point and a grid of arrows
visualizes the velocity field in the air domain. It is then clear
that, for the package with the grid on top, an air exchange is
possible but strongly limited by the presence of the filter
grid, while for the solution with the grid on bottom, the air
starts to circulate in a small part of the package, without a
real exchange with the external environment. Values of air
speed near the hole are about 4·10 -2 m/s for the package with
hole up, and 4·10 -5 m/s for the package with hole at bottom.
IV. PROPOSED MODIFICATION
Following the results presented earlier, a modified
package – aimed at enhancing air circulation is proposed.
This is obtained by inserting 1mm high windows on the
vertical walls adjacent to the sensor (see Fig. 2).
Simulations with new package show that in “face up”
configuration the air flow is almost the same as that in the
old package, but with much less vortices. Moreover, most of
Fig. 2. Proposed new package (half section)
©EDA Publishing/THERMINIC 2009 67
ISBN: 978-2-35500-010-2

Fig. 3. Standard package simulation results: Arrow and color
scale indicate air speed direction and value (m/s)
7-9 October 2009, Leuven, Belgium
Average
inlet velocity
[m/s]
Average
outlet
velocity
[m/s]
Average
exchange
flow [m 3 /s]
Standard
package
face up
TABLE I
RESULTS SUMMARY
Standard
package
face
down
Modified
package
face up
Modified
package
face
down
4·10 -2 4·10 -5 5·10 -2 5·10 -3
4·10 -2 4·10 -5 6·10 -2 2·10 -2
6·10 -7 6·10 -10 1·10 -6 2·10 -7
the new air entering the package flows along the sensor
surface and thus provides an optimal condition for the
sensing process.
A major improvement is also achieved with the package in
the “face down” orientation as, in that case, the windows are
in the upper part - where hot air accumulates. The windows
allow the air to flow out of the package, enabling new air
from the circular hole on the bottom face to come in. This
allows the flow to reach the same values as that of “face up”
orientation, with an about 1000 times increment.
Table I summarizes the estimated air speed and the
exchange flow for the two examined orientations. It can be
noticed that the modified package improves the air exchange
and consequently the efficiency of the sensor. Furthermore,
the difference between air exchanges in different positions is
reduced and the sensor, in the proposed new package, seems
not to have a preferred orientation for best performance.
At this point some comments are to be made about the
accuracy of the numerical predictions.
It would be important to show that the presented solutions
are mesh independent. Some preliminary tests have been
made by increasing the mesh size to be able to compare the
velocity fields in different mesh cases. Some inconsistencies
are found which show that the mesh with “larger” size is not
yet appropriate as important details are missed. When trying
to reduce the mesh size, convergence problems occur. The
problem under analysis is computationally too heavy to be
solved with a common workstation and it would require
more powerful tools. This critical point is under analysis and
some confirmations are expected in the next future.
Fig. 4. Proposed package simulation results: Arrow and color scale
indicate air speed direction and value in m/s
V. FINAL RESULTS
A new package has been proposed and first results suggest
that it is likely to improve the efficiency of the sensor. The
proposed package may also help in applications that require
a specific orientation of the sensor which is not optimal for
sensing efficiency. For instance, in a common smoke
detection system the sensing units are attached to the roof of
the room and sensors need to be placed with the pin side on
top.
Future developments will include simulations with the
same package in a horizontal position.
ACKNOWLEDGMENT
Authors thank Dr. Ravinder S. Dahiya for the kind
revision.
REFERENCES
[1] R. Gmür, J. Goschnick, T. Hocker, H. Schwarzenbach
and M. Sommer, “Impact of sensor packaging on
analytical performance and power consumption of
metal oxide based gas sensor microarrays”, Sensors
and Actuators B: Chemical, vol 127, Issue 1, 20 Oct.
2007, Pages 107-111, Special Issue: Eurosensors XX
The 20th European Conference on Solid-State
Transducers, the 20th European conference on Solid-
State Transducers.
[2] Grassi, M. Malcovati, P. Baschirotto, A., “Flexible
high-accuracy wide-range gas sensor interface for
portable environmental nosing purpose”, Proc. of
IEEE International Symposium on Circuits and
Systems, 2005. ISCAS 2005. Kobe Japan, 23-26 May
2005, vol. 6, pp: 5385- 5388.
[3] A. Chaiyboun, R. Traute, T. Haas, O. Kiesewetter and
T. Doll, “A logarithmic multi-parameter model using
gas sensor main and cross sensitivities to estimate gas
concentrations in a gas mixture for SnO2 gas sensors”,
Sensors and Actuators B: Chemical - vol 123, Issue 2
(2007), Pages 1064-1070
[4] Hanns-Erik Endres et al. “Improvement in signal
evaluation methods for semiconductor gas sensors”,
Sensors and Actuators B 26-27 (1995), pp. 267-270.
[5] E. Barborini, P. Piseri and P. Milani, “A pulsed
©EDA Publishing/THERMINIC 2009 68
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
microplasma source of high intensity supersonic
carbon cluster beams,” J. Physics D: Appl. Phys, vol.
32 , pp. L105-L109 (1999).
[6] K Wegner, P Piseri, H Vahedi Tafreshi and P. Milani,
“Cluster beam deposition: a tool for nanoscale science
and technology”, J. Phys. D: Appl. Phys. 2006 – 39,
R439-R459
[7] Graf, M. Frey, U. Reichel, P. Taschini, S. Barsan,
N. Weimar, U. Hierlemann, A., “Monitoring of
environmentally monolithic metal-oxide relevant
gases by a digital microsensor array”, Proceedings of
IEEE Sensors 2004, Vienna, Austria, 24-27 Oct. 2004,
IEEE Press, pp: 776- 779 vol.2
[8] Dae-Sik Lee, Sang-Woo Ban, Minho Lee, and Duk-
Dong Lee, “Micro Gas Sensor Array With Neural
Network for Recognizing Combustible Leakage
Gases”, IEEE SENSORS JOURNAL, vol. 5, n°. 3, Jun.
2005, pp. 530-536.
©EDA Publishing/THERMINIC 2009 69
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Electro-thermal simulation: a new Subsystem
in Mentor Graphics IC Design Flow
K.O. Petrosjanc, N.I. Ryabov, I.A. Kharitonov, P.A. Kozynko
Electronics and Electrical Engineering Dept.
Moscow State Institute of Electronics and Mathematics
Mentor Graphics Training Center – MIEM
Moscow, Russia, eande@miem.edu.ru, +7 (495) 235-50-42
Abstract-New electro-thermal simulation subsystem was
introduced into Mentor Graphics IC Design flow. The
subsystem incorporates IC thermal simulation tool “Overheat”,
dispatcher “ETh SimCoupler” as the simulation manager and
layout converter “ETh Model Generator”. Application example
of power voltage regulator IC simulation is described. A good
agreement between simulated and IR-camera measured
temperature pictures is achieved.
Index Terms- Electro-thermal simulation, IC, CAD.
I. INTRODUCTION
Constant decreasing of IC element dimensions, ever
increasing packing density of ICs, combining of digital and
analog blocks, integration of elements with low and high
power consumption on the same chip lead to a number of
complex problems connected with high working
temperatures and mutual thermal influence of IC elements as
a result of increasing power density.
Elements of semiconductor IC is known to be sensitive to
temperature changes. For example, temperature rise of 1 ºC
leads to 2 mV fall in forward biased p-n junction. And in the
case of temperature rise of 10 ºC the current of reverse
biased p-n junction is doubled.
Power dissipation of some IC and VLSI types may be
10..100 W, which leads to significant temperature rise of the
chip. For industrial and domestic smart power ICs the area of
power BJT, DMOST, IGBT output devices takes 30-70% of
the chip size. For instance, Intel Xeon series 7100, produced
by deep submicron 65 nm technology, dissipates 150 Watt.
Its case and junction temperatures are 70 ºC and 90 ºC. It is
known that temperature of Si ICs should not be higher
120-150 ºC to operate properly.
For analog and mixed type ICs the temperature gradients
on the chip are as much critical as the temperatures of
components. For example, temperature difference of
transistors, connected to input branches of operational
amplifiers, comparators, high precision DAC/ADCs
normally should not be more than 0.1-0.3 ºC.
Therefore presence of “hot spots” (as places of local
overheat) leads to significant changes of electrical
parameters of element or element groups, which results in
chip performance degradation. High temperature impacts not
only electrical parameters of ICs, but they force undesirable
physical-chemical processes in semiconductor material and
IC construction as well. These may lead finally to the fault
of IC.
Factors mentioned above make IC developers to hardly
constrain working temperatures of elements, introduce
thermal protection circuits and improve cooling.
As conclusion, electro-thermal simulation is one of the
most important stages of modern ICs and VLSIs design. This
simulation let to choose optimal electrical and thermal
modes for different elements, develop IC layout and
construct, resulting in: 1) minimal junction temperatures of
devices; 2) minimal mutual influence of elements through
the bulk; 3) better conditions of thermal transfer to case, heat
sink and environment; 4) minimal thermal gradients
excluding thermal strain of materials.
There are two major approaches to doing electrothermal
simulation.
In the first approach (called – relaxation method) two
independent simulators, one thermal simulator, solving
numerically heat conduction problem, and one electrical
circuit simulator (SPICE or its modifications) are used in
iterative loop to deliver the solution of the given
electrothermal problem [1], [2]. The advantages are: the high
accuracy and visualization; the on-chip or on-board steadystate
2D or 3D temperature profiles directly identify hot
spots and „poor” components; the ability to move different
©EDA Publishing/THERMINIC 2009 70
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7-9 October 2009, Leuven, Belgium
components (heat sources) on the chip/board layout to
correct the temperature map. The drawbacks are: in case of
very strongly couled electrothermal problem, the solution
cannot achieve convergence; the approach is computational
time consuming and limited by the very large number of
mesh points due to numerical solution methods.
In the second approach (called – direct method) the
thermal subsystem is represented by an electrical model
network and an electrical solver (SPICE, SPECTRE, ELDO)
performs simultaneously co-simulation of both electrical and
thermal subsystems [3]. The advantages are: capability to
achive a fast thermal solution even in case of strongly
coupled electrothermal problem; more simpler preparation
and implementation of design task. The drawbacks are: less
accurate thermal solution in the form of the set of average
temperatures of components; poor ability to change the
placement of components to improve the thermal condition.
Earlier SISSI electro-thermal simulation software package
was reported to be included in Cadence IC Design Flow [4],
[5]. Mentor Graphics lacks thermal modeling packages in its
IC Design Flow, so its capabilities are limited, particularly in
development of power analog and mixed type ICs for
industrial control, automotive electronics, power regulators
and others.
This paper describes fully automated subsystem for
electro-thermal simulation of ICs introduced into Mentor
Graphics IC Design Flow (IC Station).
II.
ELECTRO-THERMAL SIMULATION SUBSYSTEM
Relaxation method using simulator coupling approach was
chosen to introduce electro-thermal simulation into Mentor
Graphics IC Station. Electrical simulation is carried out by
Eldo – Mentor Graphics SPICE analog. Thermal simulation
is carried out by quasi-3d computational IC thermal
simulator named Overheat [6]. These simulators are coupled
through number of sequential iterations. First element
temperatures approximation is used in Eldo to compute IC
electrical behavior and powers dissipated by the elements.
Then these powers are used by Overheat to compute new
temperatures of elements, which differ from firstly
approximated. New temperatures are used by Eldo again to
compute powers for Overheat etc. These iterations are
repeated until thermal and electrical behaviors become stable
from iteration to iteration.
Developed flow chart of electro-thermal simulation is
shown in fig. 1. New blocks introduced in Mentor Graphics
IC Station and their links are shown in bold lines.
Overheat
Thermal
simulation
4
1
IC Station
Layout
Design
ETh Model Generator
Layout into thermal
IC model translation
3
ETh SimCoupler
- electro-thermal
simulation
management;
- data convertion
and transfer.
Eldo
Electrical
simulation
Fig. 1. Flow chart of electro-thermal simulation
in Mentor Graphics IC Station.
“Overheat” – quasi-3d computational thermal simulator
for monolithic ICs. The chip, fixed in the package is
represented as multi-layer structure (fig. 2); its layers have
different heat characteristics. The heat sources are circuit
elements (transistors, resistors, etc.), the heat dissipates from
package surface by convection into environment and through
lead-out wire.
Fig. 2. Model of multi-layer IC structure used in Overheat.
The mathematical model is the three-dimensional heat
conduction equation:
5
2
©EDA Publishing/THERMINIC 2009 71
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∂ 2 T
∂ x ∂2 T T
2
∂ y 2 ∂2 =0 (1)
2
∂ z
with the following boundary conditions:
a) on the boundary between chip and air:
∂T
1
=−P x , y T −T
∂ z env
, (2)
∣z=0
P x , y= /S ,x , y∈S ,
el el el {P 0, x , y∉S el
,
b) on the boundaries of different layers:
∂T
∂T
−i
=
∂ z i1 , (3)
∣z =z i
−0 ∂ z ∣z= z i
0
T x , y , z i
−0=T x , y , z i
0 (4)
c) on the bottom of the package there are two variants:
1) the heat conduction of package is large (metallic
package) its temperature is constant, but it is not
equal to environmental temperature, then the
bottom of parallelepiped is the bound solder –
package, or compound – package, and the boundary
condition:
T x , y , z n
=T pack
=const (5)
2) the package is not isothermal through the little
heat conduction (plastic package), then the bottom
of parallelepiped is the bound air – package and
there is the convective heat exchange on it:
∂ T
−n
=T x , y , z
∂ z n
−T env
(6)
∣z =z n
d) there is no heat exchange on the lateral surfaces of the
chip:
∂ T
= ∂ T = ∂T = ∂T =0 (7)
∂ x∣x=0 ∂ x∣x= x C
∂ y∣y=0 ∂ y∣y= y C
In equations (1) – (7) the following notations are used:
T – absolute temperature (K), P el – power of element
(W), S el – area of element (mm 2 ), i – coefficients of
thermal conductivity of layers (W/mm·K), T pack –
temperature of package (К), T env – the environmental
temperature (K), – coefficient of convective heat
exchange (W/mm 2·K), x C , y C – the chip sizes on
layout plane (mm), z i – the layer co-ordinates.
Thermal conductivity of silicon depends on temperature:
7-9 October 2009, Leuven, Belgium
Si =311.0/T 4 /3 , W/mm·K, (8)
For solving of the three-dimensional heat conduction
equation (1) with the boundary conditions (2) – (7) we use
the separation of variables method with the discrete Fourier
transformation and fast Fourier transformation algorithms
(FFT) [7]. The solution of equation (1) has the form:
T i , j = F −1 F P i , j ⋅ k , l ,1 ,
i=0,,M x
, j=0,,M y
,
(9)
where: T i , j and P i , j – the temperature of top of the
chip and power density in the difference network nodes
respectively; F ⋅ , F −1 ⋅ – right and inverse
discrete Fourier transformations, respectively:
f k ,l =F f i , j =
M
2
x
∑
M x
M y i=0
M x
M y
∑
j=0
f i , j
cos k i
M x
cos l j
M y
,
f i , j =F −1 f k ,l =
M y
∑
l =0
2
∑
M x
M y k=0
f k ,l
cos k i cos l j ;
M x
M y
factors k ,l ,1 , k=0,,M x , l=0,, M y
are determined from the boundary conditions.
Overheat input data consist of four types of parameters:
1. parameters, describing IC package: number and
type of each construct layer, its sizes, physical and
thermal properties of the material;
2. parameters describing IC layout: number and type
of each elements; its configuration sizes, thermal
conductivity;
3. powers of IC elements;
4. parameters directing the simulation process:
M x
×M y grid sizes, accuracy of solutions.
Output data:
1. M x
×M y matrix of temperatures in i , j grid
points;
2. multi-color temperature map of IC chip;
3. average and maximal temperatures of elements.
Execution time rises as M∗lnM , where M – grid
size in one dimension. Overheat was developed for
GNU/Linux operating system for including into developed
electro-thermal simulation subsystem.
ETh SimCoupler – dispatcher program is developed to
manage thermal and electrical simulators and their
©EDA Publishing/THERMINIC 2009 72
ISBN: 978-2-35500-010-2

interaction. ETh SimCoupler converts data transferred
between simulators (Overheat and Eldo) and launches them,
when appropriate. The program runs under GNU/Linux
operating system.
ETh Model Generator – converter for changing layout
data format from IC Station into Overheat input file format.
ETh Model Generator is developed as additional component
to layout editor IC Station.
The flow chart of electro-thermal simulation is shown in
fig. 1. Simulation begins with thermal model generation
(arrow #1 in fig. 1) made by ETh Model Generator. It
requires layout to be fully developed in IC Station and
corresponding electrical netlist to be successfully simulated
in Eldo. On the second stage ETh SimCoupler is launched to
manage iteration simulation and transfer data between
Overheat and Eldo. ETh SimCoupler runs Eldo and reveals
information about powers from this simulation (arrow #2 in
fig. 1); writes these information into Overheat input file
(arrow #3 in fig. 1); runs thermal simulation through
Overheat and reveals temperature information (arrow #4 in
fig. 1); forms new Eldo input file using gained temperatures
(arrow #5 in fig. 1). Simulation is looped this way (stages
from 2 to 5 in fig. 1) until values of dissipated powers of
elements on two consequential iterations differ less then
P parameter.
III.
APPLICATION EXAMPLE
The effectiveness of developed electro-thermal subsystem
fig. 1 is demonstrated in the example of power voltage
regulator IC K142EN9 (see fig. 1). Input voltage is 40 V,
output voltage 27 V, output current 270 mA, total power
about 11 W.
The IC chip layout with sizes 2 mm X 2 mm (see fig. 4)
was covered in Overheat by the 513x513 grid for numerical
quasi-3d solution of heat transfer equation (1).
IBM PC compatible computer (RAM – 512 Mb, CPU
frequency – 1.8 GHz) with GNU/Linux version 2.4.18
operating system was used. Simulation finished in 3
iterations and took 14 seconds. Power accuracy parameter
P was set to 10 mW.
In fig. 4 isothermal lines on the IC chip surface are shown.
IV.
IR THERMOGRAPHY OF IC CHIP
IR camera A40 of FLIR Systems with 18 μm macrolens
was used to measure IC chip thermal map and temperatures
of elements. Camera thermal sensitivity is 80 mK when
7-9 October 2009, Leuven, Belgium
temperature is 25 ºC, resolution is 320x240 pixels, tolerance
+/- 2 ºC. IC chip thermal map is shown in fig. 5. Comparing
simulated and measured thermal maps shown in fig. 4 and 5,
one can see sufficient accuracy. The differences in
temperatures of IC elements are 2-5 ºC (see Table 1).
TABLE 1
SIMULATED AND MEASURED TEMPERATURES COMPARISON
Dot
Temperature
Difference
Measured Simulated
A 355.2 K 353.5 K 1.7 K
B 353.0 K 353.0 K 0.0 K
C 347.2 K 350.4 K 3.2 K
D 343.4 K 339.5 K 3.9 K
E 341.1 K 339.9 K 1.2 K
V. CONCLUSIONS
Fully automated electro-thermal simulation subsystem is
introduced into Mentor Graphics IC Station Design System.
Efficiency of new electro-thermal subsystem were
demonstrated by the examples of different types of power
analogue and mixed A/D ICs produced by different
semiconductor technologies [8].
REFERENCES
[1] S. Wünshe, C. Clauß, P. Schwarz, F. Winkler, „Electro-Thermal
Circuit Simulation Using Simulator Coupling”, IEEE Trans. on VLSI
Systems, 1997, Vol. 5, № 3, pp. 277-282
[2] V. Székely, A. Poppe, A. Páhi, A. Csendes, G. Hajas, M. Rencz.
Electro-Thermal and Logi-Thermal Simulation of VLSI Designs. IEEE
Transactions on VLSI Systems, 1997, vol. 5,№¹ 3, pp. 258–269.
[3] V. Sabry, A. Bontemps, R. Vahrmann, „Realistic and efficient
simulation of electrothermal effects in VLSI circuits”, IEEE Trans.
VLSI Systems, 1997, Vol. 5, № 3, pp. 283-289
[4] V. Székely, A. Páhi, A. Poppe, M. Rencz, A. Csendes. SISSSI – a tool
for dynamic electro-thermal simulation of analog VLSI cells. Proc. of
European Design and Test Conference, 1997, p. 617.
[5] G. Horvath, A. Poppe. The Sissy electro-thermal simulation system
based on modern software technologies. Proc. of the
11th THERMINIC Workshop, Sept. 2005, Belgirate, Italy, pp. 51-54.
[6] K.O. Petrosjanc, I.A.Kharitonov, N.I. Ryabov, P.P. Maltcev. Software
System for Semiconductor Devices, Monolithic and Hybrid ICs
Thermal Analysis. Proc. of EURO-DAC’95 European Design
Automation Conf., Sept. 1995, Brighton, UK, pp. 360-365.
[7] K.O. Petrosjanc, N.I. Ryabov. Algorithms and Software Tools for
Electro-Thermal Design of Semiconductor Devices and ICs. Proc. of
Intern. Conf. on Parallel Computing in Electrical Engineering
(PARELEC’98), Sept. 1998, Biarlystok, Poland, pp. 310-312.
[8] Thermal Analysis and Modeling of Electronic Components:
Semiconductor Devices, Chips, PCBs and Units // Official Catalogue
CeBIT-2007, 2008 “Russian Information Technologies”. Hannover,
Germany.
©EDA Publishing/THERMINIC 2009 73
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7-9 October 2009, Leuven, Belgium
Fig. 3. Power voltage regulator IC schematic (K142EN9).
C
A
B
356,0
K
353,0
350,0
347,0
343,9
340,9
D
E
337,9
334,9
331,9
Fig. 4. Simulated thermal map of K142EN9 IC.
Fig. 5. Thermal distribution on top of K142EN9 IC,
measured using IR thermography.
©EDA Publishing/THERMINIC 2009 74
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Thermoelectric Energy Scavenging from
Waste Heat of Power Amplifier Transistors
Kyoung Joon Kim 1 , Marc Hodes 2
1 Bell Labs Ireland, Alcatel-Lucent, Blanchardstown, Dublin 15, Ireland
2 Department of Mechanical Engineering, Tufts University, Medford, MA 02155, USA
Abstract-- A thermoelectric (TE) energy scavenging technique is
proposed to recover energy from the waste heat of power amplifier
(PA) transistors. Explored are optimized pellet geometries for
maximum efficiency and performance of TE power generation
scavenging energy under various parametric conditions. A
fully-coupled TE model is developed and integrates TE physics
with heat transfer physics. The TE model is exercised to optimize
pellet geometries under various heat dissipations of PA transistors,
heat sink performances, and load resistances. The TE model
determines the efficiencies and the performances of the energy
scavenging module associated with optimized pellet geometries.
I. INTRODUCTION
Base stations consume up to 70% of the total energy of a
wireless access network (WAN), and thus increasing energy
efficiency of base stations may considerably reduce the
operating cost of the WANs and improve their ecosustainability.
However, current power amplifiers (PAs)
adversely impact the energy efficiency of base stations [1] and
PA transistors consume most energy in PAs. Indeed, PA
transistors waste 20% of the total energy used in a WAN in the
form of heat. Hence, the energy recovery from the waste heat
of transistors may considerably improve the net energy
efficiency of the WAN.
Recently, researchers have studied on the energy recovery
performances of thermoelectric generators (TEGs) from waste
heats [2]-[8]. Ikoma et al. [2] developed a Si-Ge based TEG to
apply to gasoline engine vehicles. Haidar and Ghojel [3]
demonstrated the use of the commercial Bismuth Telluride
based TEG to apply to the low-power stationary diesel engine.
Kajikawa [4] reported the feasibility to use thermoelectric
power generation systems to recover the electricity from the
municipal waste heat. Maneewan et al. [6] reported the
performance of a thermoelectric power generator using solar
heating. Suski and Edward proposed the conceptual idea to
recover the electricity from the waste heat of a CPU [7].
Solbrekken et al. [5], [8] demonstrated the recovery of the
electricity from a CPU waste heat.
In order to improve the power generation efficiency, recent
studies have been focused on the development of novel
thermoelectric materials having better figure of merit (ZT); e.g.
PbSeTe/PbTe quantum dot superlattice structures [9], p-type
Bi 2 Te 3 /Sb 2 Te 3 supperlattice devices [10], AgPb m SbTe 2+m
material [11], and silicon nanowires structure [12-13].
However, due to the practical difficulties in scaling and
manufacturing advanced materials and novel structure based
TEGs, other approaches are needed to improve the generation
efficiency. Pellet geometries are expected to considerably
affect the efficiency of TEGs, and thus the optimization of
pellet geometries can be an effective approach to improve the
efficiency.
This study seeks to investigate the efficiency and the
performance of the power generation of the energy scavenging
module under various thermal and electrical conditions. A
fully-coupled TE model is developed. The TE model combines
thermoelectric theory with heat transfer physics. The TE
model is used to optimize pellet geometries; pellet height,
pellet cross sectional area, number of thermocouples; for the
power generation and the generation efficiency of the energy
scavenging module under various heat dissipations of a PA
transistor, heat sink performances, and load resistances.
Maximum power generations and efficiencies associated with
optimized pellet geometries for various parametric conditions
are also explored.
II. BASICS OF THERMOELECTRIC POWER GENERATION
The principle of a thermoelectric power generation is
illustrated in Fig.1. A single thermocouple is shown for the
illustration purpose although typical TEGs often contain
hundreds of thermocouples. A thermocouple consists of two
dissimilar materials (p- and n-type semiconductors) and one
material is electrically positive relative to the other material.
One of the most common thermocouple materials is Bi 2 Te 3 .
Two pellets are connected electrically in series and thermally in
parallel between ceramic substrates.
When a heat rate, q h , is transferred to a thermocouple, a
certain amount of the heat rate is converted into electrical
power by generating the electrical current, I, in the generation
circuit due to the Peltier effect. The Peltier effect occurs due to
the fact that the amount of electrical energy carried by the
charged carriers associated with the flow of the electrical
current depends on the material. Further explanations regarding
the Peltier effect can be found in the literatures [14].
Consequently, the amount of q h that was not converted into the
electrical power, q c , flows out of the thermocouple. In Fig.1, T h
and T c are the temperatures of the thermocouple’s hot and cold
junctions, respectively, and R L is an electric load on the
generation cycle.
III. THERMOELECTRIC MODELLING OF ENERGY
SCAVENGING MODULE
©EDA Publishing/THERMINIC 2009 75
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q h
T h
7-9 October 2009, Leuven, Belgium
Heat Source
Heat
Spreader
TEG
P
N
Heat
Sink
q c
T c
I
Fig. 2. Thermoelectric energy scavenging module.
R L
Fig. 1. Schematic of a thermocouple in generation mode.
This section shows a proposed thermoelectric (TE) energy
scavenging module to recover the wasted energy from PA
transistors. This section also presents a fully-coupled TE model
developed to explore the performance and parametric behaviors
of the energy scavenging module.
A. Energy Scavenging Module
An energy scavenging module contains a Cu heat spreader, a
Bi 2 Te 3 based thermoelectric generator (TEG), and a heat sink
as illustrated in Fig. 2. A Cu heat spreader is used to minimize
the thermal resistance between the transistor and the
thermoelectric generator (TEG). Forced-air convection is
utilized for the reliability of high power PAs, e.g. PAs for
macro-cell base stations. Hence, the module contains a heat
sink that enhances the heat transfer from the TEG to the
ambient.
B. Fully-Coupled TE Model
A fully-coupled TE model was developed to explore the
power generation performance as well as the thermal
performance of the energy scavenging module. The TE model
integrates the TE theory with heat transfer theory by
embedding a power generation cycle in a thermal network; as
per Fig. 3. q tot is the total heat flow from the source (the
transistor), q h is the heat flow to the TEG hot side, h, P L is the
generated power by the TEG, and q c is the heat flow out of the
TEG at the TEG cold side, c. j and a denote the junction and
the ambient. θ jh and θ ca are thermal resistances between j and h
and between c and a. Fig. 3 shows basic physics of the TE
model, i.e., heat flow from the source conducts to the TEG, a
fraction of the heat is converted into the useful power, and the
remainder is dissipated to the ambient.
q h and q c can be expressed by the following equations.
q
( ) /
2 tot
= qh
= NIα Th
+ Th
−Tc
θTEG
− NI R / 2 (1)
q = NIα T + ( T −T
) / θ NI
2 R / 2 (2)
c c h c TEG +
where N is the number of thermocouples, I is the generated
current, α is the Seebeck coefficient, T h and T c are temperatures
of hot and cold sides of the TEG, respectively, θ TEG is the TEG
thermal resistance, R is the electrical resistance of a
thermocouple. Equation (1) shows that q tot is equal to q h . It is
based on the assumption that the heat loss from the source to
the ambient is negligible compared with the heat flow
conducting through the heat spreader to the TEG hot side.
In (1) and (2), the first terms, NIαT h and NIαT c are the energy
terms due to Peltier effect, the 2nd term, (T h -T c )/θ TEG is the heat
conduction purely due to the temperature difference across
pellets, the 3rd term, NI 2 R/2 is the Joule heating effect. The
further information including the derivation of q h and q c in the
form of three terms can be found in the literature [14].
q h and q c can be expressed in the form of heat flows between
j and h and heat flow between c and a as
q
q
h
c
( T j −Th
)/
θ jh
= (3)
( Tc
−Ta
)/
θca
= (4)
where T j is the junction temperature and T a is the ambient
temperature.
I is defined as
( T −T
)
N h c
I = α (5)
NR + R
where the numerator is the generated voltage across the TEG,
the denominator is the total electrical resistance of the
generation system evaluated by adding the net electrical
resistance of the TEG, NR to R L .
R is defined as
p
L
H
R = 2 ρ + Rc
(6)
A
where ρ is the electrical resistivity of the pellet, H is the height
of the pellet, A p is the pellet cross sectional area, R c is the
electrical contact resistance of a thermocouple.
R c is defined as
R
c
Rc−ρ
= 4 (7)
A
where R c-ρ is the electrical contact resistivity of a thermocouple.
θ TEG can be defined as
P
θ H
TEG
= 2 N⋅kA
(8)
where k is the thermal conductivity of the pellet.
The generated power, P L , associated with R L is defined as
2
L
R L
p
P = I
(9)
Considering the energy balance in a TEG, one can see that the
©EDA Publishing/THERMINIC 2009 76
ISBN: 978-2-35500-010-2

•θ jh
•θ ca
j h c a
q tot TEG
q h
q c
P L
Fig. 3. Schematic of fully-coupled thermoelectric model.
power can be also obtained by subtracting q c from q h .
The power generation efficiency, η, is defined as the ratio of P L
to q tot as follows.
P
=
q
L
η (10)
Solving (1) to (10) simultaneously, thermal and power
generating performances and generation efficiencies are
determined.
IV. THERMOELECTRIC ANALYSIS
This section shows optimized pellet geometries to obtain the
maximum performance and the maximum efficiency of the
energy scavenging module under various q tot , θ ca and R L.
Predicted power generations and efficiencies corresponding to
the optimized pellet geometries are also shown here.
A. Parameters and Conditions
The optimized pellet geometries; pellet height, H, number of
thermocouples, N, pellet cross sectional area, A P ; were
predicted by solving the TE model; see (1) to (10). The
solutions were obtained for N ranging from 25 to 2500 and H
ranging from 0.01mm to 10 mm under q tot ranging from 20W
to 100W, θ ca of 0.1K/W and 1K/W and R L of 5Ω and 100Ω.
Consequently, the TE model determined maximum power
generations, P max , and generation efficiencies, η max associated
with the optimized pellet geometries. . The junction
temperatures, T j , of PA transistors operating at nominal
conditions of wireless access network equipments range from
150˚C to 200˚C. In this study the arithmetic mean value; i.e.
175˚C was used for all the cases.
The material properties of Bi 2 Te 3 were used. The used
properties are Seebeck coefficient of 4×10 -4 V/K, electrical
resistivity of 1×10 -5 Ω-m, thermal conductivity of 1.5 W/m-K,
and electrical contact resistivity of 1 × 10 -9 Ω-m 2 . Thermal
resistance between the junction and the TEG hot side, i.e., θ jh
was estimated considering interfacial resistances as well as the
resistance through the heat spreader, and the estimated value
was 0.3K/W. A typical air temperature in the enclosures of
the electronic equipments is 35ºC , and thus the ambient
temperature was assumed to be 35ºC. The used parameters for
the analysis are summarized in Table 1.
B. Results with θ ca of 0.1K/W
The results associated with θ ca of 0.1K/W are presented in
Figs. 4a to 4c. Figs. 4a and 4b show optimized pellet
geometries (N opt , H opt , and A Popt ) for q tot ranging from 20W to
100W associated with R L of 5Ω and 100Ω. Fig. 4c shows P max
and η max corresponding to N opt , H opt , A Popt for various q tot . H opt
was determined to be 10mm for all q tot and R L . It is useful to
note again that the used H for the calculation range from 0.01
to 10 mm. This interesting result is mainly due to the fact
tot
7-9 October 2009, Leuven, Belgium
TABLE 1
PARAMETER VALUES FOR ANALYSIS
Parameter Symbol Value
Seebeck coefficient α 4 × 10 -4 V/K
Electrical resistivity ρ 1 × 10 -5 Ω-m
Thermal conductivity k 1.5 W/m-K
Electrical contact resistivity R c-ρ 1 × 10 -9 Ω-m 2
Thermal resistance between
junction and TEG hot side
that maximum temperature difference across pellets occurs at
the maximum height in the parametric range. The effect of the
temperature difference across pellets is seen to be a dominant
effect to the power generation.
The results associated with both R L show that both N opt and
A Popt increase with the increase of the q tot ; N opt increases from
95 to 250 with R L of 5Ω and 435 to 1125 with R L of 100Ω and
A Popt increases from 4.6 to 11.5mm 2 with R L of 5Ω and from 1
to 2.6mm 2 with R L of 100Ω as q tot increases from 20 to 100W.
To maintain T j consistently, i.e., 175ºC against the increase of
q tot , the thermal resistance across the TEG, θ TEG , should be
reduced. The product of N and A P determines the effective
pellet area of the TEG, A e and the increase of A e reduces θ TEG .
Hence, both N opt and A Popt increase with the increase of q tot .
η max was found to decrease with the increase of q tot ; e.g.,
7.4% at 20W and 5.7% at 100W; see Fig. 4c. It is mainly due
to the reduction of the temperature difference across the TEG
induced by the decrease of θ TEG to consistently maintain the T j
against the increase of q tot . η max strongly depends on the product
of N opt and A Popt . N opt with R L of 100Ω is found to be about 4.5
times greater than that with R L of 5Ω whereas A Popt with 100Ω
is about 4.5 times smaller than that with 5Ω. The result
suggests that the value of the product of N opt and A Popt for each
R L is very similar to each other. Consequently, the similar
product values may explain the similar efficiencies despite 20
times difference between two R L .
C. Results with θ ca of 1K/W
Optimized pellet geometries, maximum power generations
and generation efficiencies were further explored associated
with θ ca of 1 K/W. Figs. 5a and 5b show N opt , H opt , A Popt for
various q tot ranging from 20W to 100W associated with R L of
5Ω and 100Ω. Fig. 5c shows P max and η max corresponding to
N opt , H opt , A Popt for various q tot . Similar to the previous result
with 0.1K/W, H opt was found to be 10mm and the result
supports again that a dominant parameter affecting η max and
P max is T h -T c .
Similar to previous cases, N opt and A Popt increase with the
increase of q tot to consistently maintain the junction
temperature; N opt increases from 105 to 765 with R L of 5Ω and
465 to 2500 with R L of 100Ω and A Popt increases from 4.7 to
37.2 mm 2 with R L of 5Ω and from 1.1 to 12.1mm 2 with R L of
100Ω as q tot increases from 20 to 100W. T h -T c should be
reduced to consistently maintain the junction temperature
against the increase of q tot . Consequently, η max was found to
decrease with the increase of q tot ; e.g. 6.4% at 20W and 0.5% at
100W.
θ jh
0.3 K/W
Ambient temperature T a 35 ºC
©EDA Publishing/THERMINIC 2009 77
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7-9 October 2009, Leuven, Belgium
Nopt
Nopt
300
250
200
150
100
1200
1000
800
600
400
200
Pmax(W), ηmax(%)
50
0
0
8
7
6
5
4
3
2
1
0
N opt
A Popt
H opt
0 20 40 60 80 100 120
N opt
A Popt
H opt
q tot (W)
0 20 40 60 80 100 120
q tot (W)
η max
P max
5Ω
100Ω
5Ω
(a)
(b)
(c)
100Ω
20
15
10
5
0
0 20 40 60 80 100 120
q tot (W)
20
15
10
Fig. 4. (a) and (b) are optimized number of thermocouples (N opt), pellet cross
sectional area (A Popt), pellet height (H opt) versus various heat flows from the
source (q tot) associated with R L of 5Ω (a) and with R L of 100Ω (b). (c) is
maximum power generations (P max) and generation efficiencies (η max) versus
various heat flows from the source (q tot) associated with both R L of 5 and 100Ω.
θ ca is 0.1K/W for all the cases.
Fig. 5c shows that η max associated with two R L is very similar to
each other despite 20 times difference between two R L . The
similar η max can be explained by the fact that the value of the
product of N opt and A Popt for each R L is very similar to each
other. The calculated results show that η max considerably
decreases, 7.4% to 6.4% at q tot of 20W and 5.7% to 0.6% at q tot
of 100W, as θ ca increases from 0.1 to 1K/W. The deteriorated
η max can be explained by the decrease of T h -T c induced by the
increase of the net thermal resistance of the module.
5
0
APopt(mm 2 ), Hopt(mm)
APopt(mm 2 ), Hopt(mm)
Nopt
Nopt
800
600
400
200
0
3000
2500
2000
1500
1000
500
Pmax(W), ηmax(%)
0
8
7
6
5
4
3
2
1
0
N opt
A Popt
H opt
0 20 40 60 80 100 120
q tot (W)
N opt
A Popt
H opt
0 20 40 60 80 100 120
q tot (W)
η max
P max
5Ω
(a)
(b)
100Ω
5Ω
100Ω
(c)
0 20 40 60 80 100 120
q tot (W)
50
40
30
20
10
0
50
40
30
20
10
Fig. 5. (a) and (b) are optimized number of thermocouples (N opt), pellet cross
sectional area (A Popt), pellet height (H opt) versus various heat flows from the
source (q tot) associated with R L of 5Ω (a) and with R L of 100Ω (b). (c) is
maximum power generations (P max) and generation efficiencies (η max) versus
various heat flows from the source (q tot) associated with both R L of 5 and 100Ω.
θ ca is 1K/W for all the cases.
V. CONCLUSION
A thermoelectric (TE) energy scavenging module was
proposed to generate the electricity from the waste heat of PA
transistors. A fully-coupled TE model was developed
combining TE physics and heat transfer physics. The TE model
optimized pellet geometries such as pellet height, number of
thermocouples, pellet cross sectional area to maximize power
generations and efficiencies under various thermal and
electrical conditions; heat dissipations of a PA transistor, heat
0
APopt(mm 2 ), Hopt(mm)
APopt(mm 2 ), Hopt(mm)
©EDA Publishing/THERMINIC 2009 78
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7-9 October 2009, Leuven, Belgium
sink performances, and load resistances. The TE model was
used to determine the maximum power generations and
efficiencies associated with the optimized pellet geometries.
Optimized pellet height was found to be 10mm. The result
suggests that the temperature difference across pellets is a
dominant parameter affecting power generations and
efficiencies. The parametric study showed that generation
efficiencies associated with different load resistances are very
similar to each other despite 20 times difference between two
load resistances. The study showed that generation efficiency
decreases, e.g. 7.4% to 6.4% at a source heat flow of 20W, as
the thermal resistance between the TEG cold side and the
ambient increases from 0.1K/W to 1K/W. The decrease of the
temperature difference across the TEG induced by the increase
of the net thermal resistance of the module can explain the
degradation of the generation efficiency.
ACKNOWLEDGMENT
We would like to thank Todd Salamon in Bell Labs, Alcatel-
Lucent for the constructive discussion regarding this work.
This work was supported by IDA Ireland.
REFERENCES
[1] G. Fischer, “Next-generation base station radio frequency architecture”,
Bell Labs Tech. J., vol. 12, no. 2, pp. 3–18, 2007
[2] K.Ikoma, M.Munekiyo, K.Furuya, M.Kobayashi, T.Izumi, and
K.Shinohara, “Thermoelectric module and generator for gasoline engine
vehicles”, Proc. 17th Int. Conf. on Thermoelectrics, Nagoya, Japan, May
1998, pp. 464-467
[3] J. G. Haidar, J. I. Ghojel, “Waste heat recovery from the exhaust of lowpower
diesel engine using thermoelectric generators”, Proc. 20th Int.
Conf. on Thermoelectrics, Beijing, China, June 2001, pp. 413-417
[4] T. Kajikawa, “Status and future prospects on the development of
thermoelectric power generation systems utilizing combustion heat from
municipal solid waste”, Proc. 16th Int. Conf. on Thermoelectrics,
Dresden, Germany, August 1997, pp. 28-36
[5] G. L. Solbrekken, K. Yazawa,A. Bar-Cohen, “Heat driven cooling of
portable electronics using thermoelectric technology”, IEEE T. Adv.
Packaging, vol. 31, no. 2, pp. 429-437, May 2008
[6] S. Maneewan, J. Khedari, B. Zeghmati, J. Hirunlabh and J.
Eakburanawat, “Experimental investigation on generated power of
thermoelectric roof solar collector”, Proc. 22nd Int. Conf. on
Thermoelectrics, Montpellier, France, August 2003, pp. 574-577
[7] Suski and D. Edward, “Method and apparatus for recovering power from
semiconductor circuit using thermoelectric device,” U.S. Patent 5 419
780, May 30, 1995.
[8] K. Yazawa, G. L. Solbrekken, and A. Bar-Cohen, “Thermoelectric
powered convective cooling of microprocessors,” IEEE T. Adv.
Packaging, vol. 28, no. 2, pp. 231–239, May 2005.
[9] T. C. Harman, P. J. Taylor, M. P. Walsh, B. E. LaForge, “Quantum dot
superlattice thermoelectric materials and devices”, Science, vol. 297, pp.
2229-2232, September 2002
[10] R. Venkatasubramanian, E. Siivola, T. Colpitts, B. O'Quinn, “Thin-film
thermoelectric devices with high room-temperature figures of merit”,
Nature, vol. 413, pp. 597-602, October 2001
[11] K. F. Hsu, S. Loo, F. Guo, W. Chen, J. S. Dyck, C. Uher, T. Hogan, E.
K. Polychroniadis, M. G. Kanatzidis, “Cubic AgPb mSbTe 2+m: Bulk
thermoelectric materials with high figure of merit”, Science, vol. 303,
pp. 818-821, February 2004
[12] A. I. Hochbaum, R. Chen, R. D. Delgado, W. Liang, E. C. Garnett,
M. Najarian, A. Majumdar, P. Yang, “Enhanced thermoelectric
performance of rough silicon nanowires”, Nature, vol. 451, pp. 163-167,
January 2008
[13] A. I. Boukai, Y. Bunimovich, J. Tahir-Kheli, J.-K. Yu, W. A. Goddard
III ,J. R. Heath , “Silicon nanowires as efficient thermoelectric
materials”, Nature, vol. 451, pp. 168-171, January 2008
[14] D. M. Rowe, Thermoelectrics Handbook: Micro to Nano, CRC, 2006
©EDA Publishing/THERMINIC 2009 79
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7-9 October 2009, Leuven, Belgium
Practical Realization of PTAT Sensor
for ASIC Overheat Protection
M. Szermer, M. Janicki, Z. Kulesza, A. Napieralski
Department of Microelectronics and Computer Science, Technical University of Lodz
Wolczanska 221/223, 90-924 Lodz, POLAND
Tel. +48 42 631 2722
e-mail: szermer@dmcs.pl
Abstract-This paper presents simulations and measurements
of an integrated PTAT sensor. The sensor is equipped with an
overheat protection circuit and was implemented in an ASIC
containing matrices of heat sources and junction temperature
sensors. The PTAT sensor is used for temperature monitoring
and it is responsible for issuing warning signals in a case of chip
overheat. Particular attention is paid to the discussion of sensor
design and the presentation of simulated circuit operation.
I. INTRODUCTION
The constant increase of dissipated power density in the
state-of-the-art integrated circuits quite often requires realtime
chip temperature monitoring. The idea of temperature
monitoring system is not new and it was already presented
in [1]-[2]. One of the methods to realize such a monitoring
system is to place temperature sensors inside circuit layout.
Just simple p-n diodes could serve for this purpose.
Another possible solution is to use dedicated temperature
sensors, such as the Proportional To Absolute Temperature
ones (PTATs). The main advantage of this sensor is that it
has the linear dependence of output voltage on temperature.
This allows high precision temperature measurements.
Another advantage is that this sensor usually consists of a
small number of transistors; hence the area occupied by the
sensor is very small. Moreover, PTAT sensors can be
designed using standard transistors available in a particular
design technology, so no additional process steps are
required. The PTAT sensors can be used as temperature
warning elements only after minor modification of a circuit.
This is a very desired feature in modern chips.
The following section presents in detail the design of our
sensor. Then, the simulated characteristics of the sensor are
presented and compared with the measured ones. Finally
separate section discusses the details of sensor layout design
in the particular technology chosen for a practical ASIC
realization.
II. PTAT SENSOR DESIGN
However the idea of PTAT sensor is well known but
detailed description of it is written in this section [3]-[5].
First the conception of the PTAT sensor with other blocks is
discussed. After this the PTAT sensor is described in more
details. The description of it reveals the conception of the
overheat protection circuit.
The block schematic of designed temperature monitoring
system, placed in the ASIC, is shown in Fig. 1. This system
consists of a sensor, a comparator, a voltage divider and
current mirrors. The mirrors provide the proper bias currents
to the other circuits and are not described in the paper. One
input of the comparator is connected to the constant voltage
from the voltage divider. The second input is connected to
the output voltage from the PTAT sensor. This allows
triggering the warning signal by the comparator. In case of
emergency, this output signal from the comparator is
responsible for switching off the transistors delivering
current to the bipolar transistor inside the sensor. This action
is described in more detail in the following paragraph. The
practical realization of this system, its simulations and
measurements are discussed in the next two sections.
The designed PTAT sensor consists of 9 MOS transistors,
3 bipolar transistors and 1 resistor (see Fig. 2). The MOS
transistors create current mirrors which inject the desired
current to the sensor. In order to explain properly the
principle of sensor operation it is necessary to describe these
current mirrors in more detail. This circuit consists of 7
MOS transistors. Transistors M0 and M1 are the circuit
inputs to which current is delivered. Transistors M4 and M5
are used as outputs of the mirror. They deliver current to the
bipolar transistor used in a sensor. From the operation point
of view the pair of transistors M2 and M3 is very important.
They constitute an additional output of the mirror.
The transistor M6 is used as a switch which is responsible
for turning on and off the additional current mirror output.
The gate of this transistor is connected to the overheat
warning signal. In absence of the warning, the current is
flowing through the mirror and the voltage drop at the output
is higher than in the case when the current is not flowing
through the additional mirror (the warning signal high).
Owing to this, the output voltage reaches its critical value at
150 °C and the warning signal is issued.
The sensor was designed so that it has a hysteresis in the
output characteristics. This means that the warning signal is
cancelled when the temperature decreases below 130 °C.
This phenomenon is clearly visible in Figs. 3-4. The desired
output signal hysteresis size and the low power consumption
of the sensor were attained owing to the proper dimensioning
of the transistors.
©EDA Publishing/THERMINIC 2009 80
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7-9 October 2009, Leuven, Belgium
Fig. 1. Schematic of overheat protection circuit.
Fig. 2. Detailed schematics of PTAT sensor.
©EDA Publishing/THERMINIC 2009 81
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7-9 October 2009, Leuven, Belgium
0.8
0.75
Voltage [V]
0.7
0.65
0.6
Sensor
Localization
0.55
0.5
0.45
0 20 40 60 80 100 120 140 160
Temp [C]
Fig. 3. Simulations of the output signal from the sensor.
III.
SIMULATIONS
The whole system containing the PTAT sensor, as already
mentioned in previous section, was simulated in the
CADENCE environment. In order to simulate this circuit,
the transistor models from the austriamicrosystems ® (AMS)
0.35 μm high voltage technology were used. This technology
was chosen for the practical realization of the ASIC. The
simulations confirmed that the behavior of the sensor
conforms to the design specifications. With increasing
temperature, the sensor output voltage decreases with the
negative slope of –1.72 mV/K. When temperature reaches
150 °C, the additional current mirror is switched off and the
current delivered to the bipolar transistor is twice smaller.
This means that the output voltage rapidly drops down by
some 25 mV what allows the generation of logic one at the
overheat warning pin, which is clearly visible in Fig. 3.
When temperature decreases, the output voltage increases
again. When the temperature reaches 130 °C, the output
voltage rapidly grows and the warning signal is switched off,
which can be observed in Fig. 4.
Fig. 5. Photo of a die.
IV. ASIC REALIZATION
The presented overheat protection circuit containing the
PTAT sensor, as already mentioned, was manufactured in
the thermal test ASIC designed in the Department of Microelectronics
& Computer Science at the Technical University
of Lodz, Poland. The location of the sensor in the circuit
layout is shown in Fig. 5. For full description of the test
ASIC, refer to [6]-[7].
The sensor layout, presented in Fig. 6, consists of 9 PMOS
transistors which are connected as current mirrors. Besides,
there are 3 bipolar transistors and 1 polysilicon resistor. All
the devices are placed so as to obtain the minimal area in the
ASIC. Because the circuit contains 9 large power transistors
acting as heat sources, the total area of the whole ASIC
amounts to almost 20 mm 2 . The dimensions of the PTAT
sensor alone are 125 μm × 90 μm, so it is a very small sensor
which can be used in different integrated circuits, where
precise temperature measurements are necessary. Obviously,
the PTAT sensor together with the overheat warning system
occupies slightly bigger area.
Voltage [V]
3
2.5
2
1.5
1
0.5
MOS
Transistors
Bipolar
Transistors
Resistor
0
0 20 40 60 80 100 120 140 160
Temp [C]
Fig. 4. Simulations of the overheat warning signal.
Fig. 6. Layout of PTAT sensor.
©EDA Publishing/THERMINIC 2009 82
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Voltage [V]
0.8
0.78
0.76
0.74
0.72
0.7
0.68
0.66
0.64
0.62
Meas. - Observed
Meas. - Fitted
Simulations
0.6
20 30 40 50 60 70 80 90 100
Temperature [C]
Fig. 7. Simulations vs. measurements.
Unfortunately, the use of high voltage technology required
the placement of additional guard rings between transistors
and resistors. This was necessary because inside the chip
also high voltage transistors are used as the heat sources.
Therefore, the PTAT sensor, as an analog circuit, should be
isolated, otherwise other circuits could disturb its operation.
The sensor operation was tested on a measurement stand
with forced water cooling in the temperature range from
30 °C to 95 °C. The measurements of the manufactured
PTAT sensor are compared with the earlier simulations in
Fig. 7. As can be seen, the measured output characteristic is
almost linear and has a negative slope of –1.74 mV/K, which
is almost the same as the simulated one. However, the
measurements reveal a small voltage offset of 20 mV. The
most probably this offset is caused by the polysilicon
resistor, whose resistance could be different than the one in
the design, due to technological parameter scattering.
Because so far only water cooling was used, the operation
of the sensor was investigated only under 100 °C, so the
verification of the overheat warning circuit could not be
carried out. Currently the measurement stand is being
7-9 October 2009, Leuven, Belgium
modified through the introduction of Peltier thermo-electric
modules and the dual cold plates. Then, such a verification
and further sensor calibration in higher temperatures will be
possible.
V. CONCLUSIONS
The design and the simulations of a PTAT sensor were
presented in this paper. The measurements of the
manufactured circuit confirmed the proper sensor operation.
This sensor, integrated with the overheat protection circuit,
can be reused as a stand-alone device. Through the proper
dimensioning of MOS transistor channels the triggering
temperature of the protection circuit and the hysteresis size
can be adjusted.
ACKNOWLEDGMENT
This work was supported by the Ministry of Science and
Higher Education grant No. N515 008 31/0331.
REFERENCES
[1] V. Szekely, “Thermal Monitoring of Microelectronic Structures”,
Microelectron. J., Vol. 25, pp. 157-170, May 1994
[2] W. Wojciak, A. Napieralski, “Thermal monitoring of a single heat
source in semiconductor devices – the first approach”
Microelectron. J., Vol. 28, No 3, pp. 313-316, March 1997
[3] Chih-Ming Chang, Herming Chiueh, “A CMOS Proportional–To–
Absolute Temperature Reference for Monolithic Temperature
Sensors”, THERMINIC 2004, Sophia Antipolis, Cote d’Azur,
France, 29 September – 1 October 2004
[4] M. Szermer and A. Napieralski, “The PTAT Sensors in CMOS
Technology”, 2005 International Semiconductor Conference, 28th
Edition, Sinaia, Romania, 3-5 October, 2005, Vol. 1, pp.197-200
[5] W. Wojciak, A. Napieralski, M. Zubert, M. Janicki “Thermal
monitoring in integrated power electronics – new concept”, EPE’97,
Trondheim, Norway 8–10 September 1997, pp. 2.906-2.910.
[6] M. Szermer, Z. Kulesza, M. Janicki, A. Napieralski, “Test ASIC for
Real Time Estimation of Chip Temperature”, NSTI Nanotech 2008,
Hynes Convention Center, Boston, Massachusetts, USA, 1-5 June
2008, Vol.3, pp. 529-532
[7] M. Szermer, Z. Kulesza, M. Janicki, A. Napieralski, “Design of the
Test ASIC for on-line Temperature Monitoring and Thermal
Structure Analysis”, 15th International Conference Mixed Design of
Integrated Circuits and Systems MIXDES 2008, Poznan, Poland,
19-21 June 2008, pp. 317-320
©EDA Publishing/THERMINIC 2009 83
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7-9 October 2009, Leuven, Belgium
Thermo-Mechanical Reliability Loop
In Device Modeling
T. Bieniek, G. Janczyk, P. Grabiec, J. Szynka
Institute of Electron Technology
Al. Lotnikow 32/46
02-668, Warsaw, POLAND
Abstract- 3D device integration faces the designers with new
thermo-mechanical design and device exploitation problems.
Temperature dependent mechanical stress spreading across the
device affects its performance. This paper discusses selected
performance and reliability issues related device the
mechanical stress and temperature influence.
Keywords: Thermo-mechanical modeling, device reliability,
integrated modeling, stress affection
I. INTRODUCTION
Evolving demands on device functionality, reliability and
performance result in various paths of engineering technology
development and handle with Moore’s law. Fundamental
constrains of physics are getting closer and more important as
devices are continuously downscaled. Therefore to make
devices more robust and powerful architecture tricks and 3D
integration technologies have to be exploited. Several research
projects like e-Cubes [1] or Corona [2] and many other
stimulate R&D efforts in such fields as design-flow speed-up
accompanied by development of integration technology.
The main idea of the e-Cubes project consists in assemble of
the particular number of chip-modules into the one
heterogeneous MEMS/MOEMS device assembled as a vertical
stack of the electrically, thermally and mechanically connected
modules. It is a 3D integration technique developed to make
device as universal and robust as possible. Another aim is to
reach the best device performance by means of applying the
technology perfectly fitting customer device requirements. It is
close to Corona project ideas to reduce time-to-market by
optimizing the product engineering flow from an idea through
the design to the final device fabrication. Knowledge based,
spread cooperation designers and manufacturers framework
should be ready to incorporate customer feedback and active
cooperation in field of their idea hardware implementation. The
Corona project research area covers innovations in integrated
design methodology and production flow. Methodology and
tools used for multidomain modeling and simulation are
especially important for the product development process and
device reliability control. From the economic point of view it is
necessary to reduce costs by means of time and redundant
design efforts reduction now necessary before the final
technological run.
II. MODELING AND SIMULATIONS
Selected reliability issues like thermo-mechanical behavior
of the whole integrated MEMS/MOEMS device and
mechanical stress which spreads through the device substrate
have been discussed in this paper. 3D device integration
techniques relies on multi module stack formed of silicon
slices, mechanically assembled by vertical connections [3, 4]
that support mechanical integrity of 3D integrated device and
provide both: electrical and thermal connections between
stacked modules. Semiconductor memories, microprocessors,
CMOS image sensors and various heterogeneous systems are
the main application for 3D integration technologies
incorporating vertical integrating elements supporting
electrical, thermal and mechanical connections. Among several
solutions developed in frames of eCubes project – though
silicon via (TSV) formed from conducting materials like Cu,
W, TiN can be applied for 3D heterogeneous integration.
Single TSV is inserted as a nail into deep, narrow holes (high
aspect ratio) etched through the silicon wafer substrate. Each
TSV goes through the whole substrate. The quality of TSV
affects the device reliability and performance. As the
temperature distribution is dependent on heat dissipation in the
device it is affected by TSV thermal parameters. It also
introduces additional mechanical stress into the device and
affects device reliability and performance. Fundamental
parameters of semiconductor device like silicon
crystallographic orientation, carrier density, band-gap width
and carrier mobility affect the device performance. As the
device reliability is dependent on mechanical stress
distribution, it should be accurately modeled to predict and
control the device performance. All above mentioned
fundamental device physical parameters are affected by
temperature and depend on mechanical stress distribution,
which is yet another parameter to be taken into account for
estimation of the device reliability.
Fig. 1. Mechanical stress value spreads across the wafer. Affection on
transistor parameters and performance varies in dependence of transistor
and stress source locations.
©EDA Publishing/THERMINIC 2009 84
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7-9 October 2009, Leuven, Belgium
Devices fabricated on wafers with TSV interconnecting
elements are exposed to additional mechanical stress related to
the IC layout and wafer shape (Fig. 1). This paper discusses
various cases of stress distribution based on simulation results
performed by Coventor [5] and TCAD [6] packages.
A
Fig. 3. Mechanical design drawing (3D model), without and with
encapsulation [7].
Even if all standalone (non 3D) modules have been correctly
designed, simulated and would perfectly operate if assembled
as standalone devices, if the device profits from 3D integration
technique its functionality may be affected by various side
effects not taken into consideration during design. Such a
device not optimized for 3D integration during design process
– may fail. 3D integrated device comprises various modules.
Fig. 2. a) V T(P) - Threshold Voltage (V T) on Stress Tensor (P) sensitivity for
various Stress Tensor-Channel Angle (α). NMOS; L=130[nm]; Shallow S/D;
UDS=0.05[V] b) Threshold voltage variation for 350nm technology for
various mechanical stress levels and various angles between mechanical
force and source-drain direction
It is especially important for analogue blocks and low noise
amplifiers. Electrical simulations performed in TCAD show
that digital blocks are more resistant to the mechanical stress
then analogue ones. Sample simulations performed in TCAD
for MNOS and PMOS transistors show that mechanical stress
relative sensitivity of complementary MOS devices is
complementary as presented on Fig. 2b. Selected results of
TCAD simulations performed for simple digital blocks like
inverters and NAND digital gates also have been performed.
Simulated gates have been modeled for AMS 350nm
technology. Simulation results confirm that for moderate levels
of mechanical stress (mechanical stress level should not exceed
the level of 500MPa) parasitic stress does not significantly
affect transfer function of digital circuits.
Modeling and simulation results of the integrated, intelligent
health monitoring system 3D model [7] have been presented.
Such a system is the e-Cubes project demonstrator sample.
General idea is shown on the Fig. 3. Significant speedup and
improvements of product development stages will be the profit
of the project. From the reliability point of view thermomechanical
behavior of the whole system is the most important
parameter to be taken into consideration.
B
Fig. 4. 3D model of the e-Cubes demonstrator for health monitoring
designed in CoventorWare with the mesh ready for multidomain modeling
and simulation by FE methods.
Each of them affects neighboring modules in thermal,
mechanical, electrical, electromagnetic way. Probability that a
single module affects another in its neighborhood (e.g. by high
temperature transfer) is quite high. Therefore the module
arrangement and its complex multidomain simulation are so
important on each design stage.
For this simulation 3D model designed in CoventorWare have
been used (Fig. 4). 3D integration technique has been
simulated along with applied, real thermo-mechanical
boundary conditions like power dissipation present in different
modules. Also selected mechanical issues regarding the
encapsulation methodology have been done. Thermal
simulations results show that under assumed boundary
conditions temperature does not increase too much across the
whole demonstrator device structure Sample results of the
thermal investigation are shown on the Fig. 5.
The aim of this part of the simulation was verification of the
temperature distribution under high and low power operating
modes. 300 K ambient temperature has been assumed as one of
boundary conditions applied for this simulation as well as
convection and radiation on the bottom and upper surfaces. For
applied boundary conditions in the worst case temperature
increases to 325 K for high power mode and 310 K for low
power mode.
Apart from the thermal phenomena mechanical properties of
the device and used materials are important from reliability
point of view, especially under higher range device
temperatures. The main goal of performed simulation was to
©EDA Publishing/THERMINIC 2009 85
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7-9 October 2009, Leuven, Belgium
check if and how big is mechanical displacement observed
within the device for particular modes of the device fixing.
Fix
Applied boundary conditions have been the same as for high
power mode. Analysis of displacement simulation results (see
Fig. 6) lead to a following major conclusion: displacement and
mechanical stress distribution are much lower if there are more
fixed points applied inside the device.
Fix
A
Temperature [K]
High Power A Low Power
Temperature [K]
325,1
325,0
324,9
324,8
324,7
324,6
324,5
324,4
324,3
324,2
0 5000 10000 15000 20000
Distance [um]
Temperature [K]
310,4
310,4
310,4
310,4
310,4
310,4
310,4
310,4
0 5000 10000 15000 20000
Distance [um]
B
Fig. 5.Temperature distribution in high and low power modes: a) 3D
model view; b) temperature distribution on the top-center surface of the
3D model
III. CONCLUSIONS
Semiconductor devices are sensitive to the mechanical stress
(Fig. 1, Fig. 2, Fig. 3). As it is dependent on the device
temperature additional simulations it should be performed
whether device will operate or fail due to the direct temperature
parameters variation or indirect dependence accompanied by
mechanical stress (Fig. 2). The complete design, verification,
fabrication circle has been elaborated and is still under
development. Several software loop components are still under
research, development or testing. Finally it should improve the
device fabrication field affected by deterministic and non
deterministic environmental factors. One of deterministic is
mechanical stress dependent on the device temperature.
Complex multi domain simulation technique is a must for
contemporary electronic design.
ACKNOWLEDGMENT
This work has been partially supported by the European
Commission under support-number IST-026461 (European
project: 3D Integrated Micro/Nano Modules For Easily
Adapted Application, acronym e-CUBES [1]) and CP-FP
213969-2 (European project: Customer-Oriented Product
Engineering of Micro and Nano Devices, acronym
CORONA [2]). We would like to thank e-Cubes project and
CORONA project Partners for the excellent and fruitful
collaboration.
Displacement [µm]
B
Fig. 6. View of the two different fixation types (a) and view of the
plastic deformation (plastic deformation factor x100! – b) and
displacement [µm].
REFERENCES
[1] More information available at www.ecubes.org
[2] More information available at www.corona-mnt.eu
[3] P.Schneider, S.Reitz, A.Wilde, G.Elst, P.Schwarz, “Towards a
Methodology for Analysis of Interconnect Structures for 3D-
Integration of Micro Systems”, Proc. Symposium on Design, Test,
Integration and packaging DTIP’07, Stresa, Italy (2007).
[4] Bernhard Wunderle, Eberhard Kaulfersch, Peter Ramm, Bernd
Michel and Herbert Reichl, “Thermo-Mechanical Reliability of 3Dintegrated
Microstructures in Stacked Silicon”, Proc. 2006 MRS
Fall Meeting, November 27 - December 1, 2006, Boston.
[5] More information available at www.coventor.com
[6] More information available at http://www.synopsys.com
[7] Piet van Engen, Ric van Doremalen, Wouter Jochems, Ad
Rommers, Shi Cheng, Anders Rydberg, Thomas Fritzsch, Jürgen
Wolf, Walter De Raedt, Philippe Müller, Eduardo Alarcon, Mihai
Sanduleanu, “3D Si-level integration in wireless sensor node”,
Proceedings of the Smart Systems Integration 2009 conference,
page 150-157, 10/11 March 2009, Belgium Brussels.
©EDA Publishing/THERMINIC 2009 86
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7-9 October 2009, Leuven, Belgium
A Temperature-Dependent POWER MOSFET Mode1 for Switching Application
H. DIA 1,2 , J.B. Sauveplane 1 , P. Tounsi 1,2 , J-M. Dorkel 1,2
1 CNRS; LAAS; 7 avenue du Colonel Roche, F-31077 Toulouse, France
2 Université de Toulouse; UPS, INSA, INP, ISAE; LAAS; F-31077 Toulouse, France
dia@laas.fr
Abstract- in this paper, an electrical model of a power vertical
MOSFET sensitive to temperature is proposed using VHDL-AMS
code. Our modeling approach is based on basic physical MOSFET
effect and on its technological structure. Thermal sensitivity of
MOSFET parameters is discussed and characterized. Validation
of the model accuracy is presented by comparison between
simulations and experimental results. Among the benefits of this
technique are fast simulation, good agreement between
simulations and measurements and useful insights into thermal
sensitivity of MOSFET performance in switching applications.
This work is the first step to electro-thermal simulation of power
device by simulator coupling.
studies of the device [4] addressing basic equations in the
semiconductor. Each area of the MOSFET structure shown on
“Fig.1.”((1) Channel, (2) access, (3) PN - junction, (4) drift and
(5) substrate) is described taking into account the main
characteristics of the power device: linear, saturated behavior
and non linearity of the gate-drain and drain-source
capacitances.
Keywords-modeling, power MOSFET, power diode, VHDL-AMS.
I. INTRODUCTION
Continuous improvement in power devices performances
involves the reduction of their sizes which increases power
losses density even in a same application context. As reliability
relies most of the time on maximum temperature variation of
the chip, electro-thermal simulation of a power device within
its environment becomes a key tool to avoid re-design of a
chip. In this context electro-thermal model has already been
presented in literature [1]-[2], but the major drawbacks of
previous model is that power device is assumed to be “ON
state” during the simulation. This assumption is valid only if
power switching losses are negligible or if switching behavior
is not relevant to the application. To overcome these limitations
a new approach has been developed based on simulator
coupling to accurately simulate the electro-thermal behavior of
the power device [3]. This paper is the first step toward this
modeling approach as it presents an electrical model of a power
vertical MOSFET, sensitive to temperature, using VHDL-AMS
code. The power device studied is a low voltage vertical power
MOSFET with ultra low on state resistance. The paper is
divided in two parts. First the electrical model of the power
device sensitive to temperature is detailed, based on basic
physical MOSFET effect and on its technological structure.
Then the extraction procedure to obtain the model parameter is
presented and at the end a comparison between simulations and
experimental result are shown for a power device in a
switching application.
II. THE POWER MOSFET MODEL
A. The Electrical Model
The modeling approach relies on experimental and simulation
Fig. 1. Cross section of power MOSFET
The body diode, P (body)/ N- (epitaxial layer) junction has also
been implemented in the model. This diode allows the
simulation of the transistor's reverse bias behavior. The model
of the body diode is based on a previous work on the power
PIN diode [5].
Fig. 2. The body diode model
This model “Fig.2.” takes into account the forward and reverse
behavior of a diode and also the reverse recovery current
phenomena caused by the charge stocked in the intrinsic region
during the forward polarization. The forward phase is modeled
by a resistor R on , which means that the forward polarization
phase is a simple one “Fig.3.” And it’s sufficient enough to
address the thermal issues, a conductance G off for the reverse
phase and to model the leakage current; all this is compact in
the IdealDiode model. The voltage depended current source Jc
©EDA Publishing/THERMINIC 2009 87
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is used to model the forward polarization capacitor.
7-9 October 2009, Leuven, Belgium
The current source I ds is responsible of the linear and saturation
state of the transistor,
I
I
DS
DS
⋅ ( Vcom
− Vth
) − ⋅VI DS
) ⋅VI
DS
( V −V
) 2
= Kp
1 (2)
2
= ⋅
(3)
Kp
2 com th
Fig. 3. The forward polarization of the body diode
I
J c
= K.
V L
(1)
This current “(1),” depends of the drop voltage of the
inductance L and magnified by a constant K, during the
transient blocking stage of the diode the inductance L energy
will discharge in the resistor R L , and the current source Jc will
deliver a reverse current simulating the reverse state current of
this diode, an example of this reverse current simulation is
shown on “Fig.4.”, in this paper we will show only a
simulation of the reverse current because the body diode of our
MOSFET DUT is a very fast one, it have a very low reverse
current, and it doesn’t vary in a significant matter with
temperature.
Fig. 4.Simulation of the diode current during commutation for two given
temperature, the dotted curve(blue) is at 150°C and the normal one is at
25°C
By using this model as a body diode we have a complete power
MOSFET electrical model “Fig.5.”. We should mention that
the C ds capacitor is the reverse polarization capacitor of the
diode model play the role of the drain-source capacitor and this
capacitor is a non linear with voltage as mentioned above.
Fig. 5. Power MOSFET electrical & thermo-sensible model for switching
circuits.
“(2),” describe the linear phase knowing that
I DS
is the drop
voltage of the current source Ids and V com is the command
voltage. “(3),” describe the saturation phase
B. Temperature dependents parameters
The expansion of the electrical model into a thermal sensible
one is done by introducing the temperature as a variable into
the equations of the electrical parameters in the electrical
model. The first step is to identify the electrical parameters
influenced by the temperature in a way that the electrical
behavior of the MOSFET is changed. These parameters are
(Kp, V th , R sub , R g , R s , R on , I ss , V knee ) where Kp is the
transconductance parameter and V th is the threshold voltage,
R epi , R sub , R g , R s are the epitaxial resistor, substrate resistor,
gate resistor, source resistor of the MOSFET. Ron is the
forward phase resistor, I ss is the leakage current, and V knee is
the threshold voltage of the diode. We don’t need to include
the capacitors as temperature dependent because it doesn’t
vary much with temperature [6]. The extraction of the
temperature dependent parameters has been done by
electrical characterization of a power MOSFET and the body
diode under different temperature imposed by the air flux of
the thermo stream.
III. MODEL’S PARAMETER EXTRACTION AND VALIDATION
A. Parameter extraction
The model parameters were carefully identified based on
simulations and an automatic experimental acquisition method
developed in our laboratory which is sufficiently general to be
applied to Power MOSFET devices. The experimental
measurements are done under different temperature using the
thermo-stream (25°C, 50°C, 75°C…175°C), We faced a
serious problem for temperature above 175°C; the
experimental dispositive melted down cause’s short circuit, so
the temperature dependent equations are valid between 25°C
and 175°C. The determination of the static parameters Kp
“(4),” transconductance parameter, the threshold voltage V th
“(5),” and the series resistor R ON “(6),” is done by measuring
the transfer characteristics and the output characteristics using
the Agilent HP4142.
Kp = 244 − 0.7( T − 25) (4)
−3
V th
= 2.6 − 3.3e
( T − 25) (5)
−6
3 −4
2 −4
R on
= 1.0e
( T −25)
−2.0e
( T −25)
+ 1.9e
( T −25)
+ 1.97 (6)
For the diode parameters, they are represented by the following
equations,
−3
V Knee
= 0.7 − 2.0e
( T − 25) (7)
V
©EDA Publishing/THERMINIC 2009 88
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−2
−11
7.7e
( T −25)
I
ss
= 4.0e
Exp
(8)
7-9 October 2009, Leuven, Belgium
All the equations mentioned above are the result of the
polynomial interpolation of the extracted different parameters
points from measurement under different temperature.
Values of the dynamic parameters (capacitance) are
experimentally obtained by measuring the input (C iss = C gs +
C gd ), output (C oss = C ds + C gd ) and reverse transfer (C rss = C gd )
capacitances. Drain-source capacitance is then obtained by
calculating (C oss - C rss ). Gate-Source capacitance is obtained by
calculating (C iss - C rss ): this capacitance is kept constant due to
the negligible variation by comparing it with the variation of
C gd and C ds . We used the equation of the variation of a transient
diode capacitor “(9),” as a model for C gd and C ds .
V −m
CT
= CJ
(1 − )
(9)
0 VJ
C J0 is the capacitance values at zero polarization, V J is diffusion
voltage of the junction and m is the coefficient of graduality.
But for the current equation of the capacitor we don’t use the
conventional equation “(10),” that has been used in spice and
other kind of non linear MOSFET capacitor modeling, we use
an equation of a variable capacitor “(11),” with Q “(12),” is the
charges of the capacitor.
i = CT
dv dt (10)
i =
dQ
(11)
dt
Q = C V (12)
T
With “(11),” we gain a lot in precision and we could fit almost
perfectly our simulation with the measurement we made.
“Fig.6” shows a comparison between two simulations, the
dotted curves shows a commutation using “(10),” and the
normal curves shows a more rapid commutation using “(11),”
Fig.7. the influence of the non linear capacitor equation(zoom)
The Blue curves are the current of the MOSFET, the green
curves are the gate to source voltage and the red curves are the
drain to source voltage.
B. Validation of the approach
The best way to validate our model is to compare our
simulations with measured data obtained from the power
device in a switching circuit. This circuit is shown on “Fig.8.”
Fig.8. Experimental circuit for switching application
This circuit consists of a V bat : DC power supply “HP6671A”,
pulse: 13V, delay(10µs), width (50µs), the gate resistor R g
(100Ω), a limiting current resistor R ch (0.33Ω), a pull down
resistor R pulldown (10kΩ) and an inductor L (1µH). The circuit is
exposed to the hot air flux of the thermo-stream and the data
are collected for each temperature, starting at 25°C ending at
175°C, with 25°C as a step. The simulation has been done
using System Vision professional 5.0 simulator.
Comparison between simulation and measurement are shown
on “Fig.9.” and “Fig.10.”. One can see that there is a nearly
perfect match between them.
Fig.6. the influence of the non linear capacitor equation
A Further zoom “Fig.7” shows in a clear way the delay to cut
off the current of the MOSFET device, which will affect the
power and the energy dissipated in the device. Furthermore we
see that the overvoltage phenomena is affected also because the
real variable capacitor equation“(11),” is more rapid than the
conventional one“(10),” Finally, the simulation time for the
two capacitor equations isn’t the same, the simulation time is
doubled when we use“(11),” .
Fig.9. Commutation simulation (dotted) vs. measurement across MOSFET at
25°C
©EDA Publishing/THERMINIC 2009 89
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7-9 October 2009, Leuven, Belgium
IV.
CONCLUSION
Fig.10. Commutation simulation (dotted) vs. measurement across MOSFET
at 150°C
Although the two figures look identical there is a subtle
difference between them, this difference is illustrated on
“Fig.11.” a Comparison between measurement at 25°C and
150°C are shown, using the drain to source voltage at the end
of the MOSFET commutation.
In this paper, an electrical model using VHDL-AMS code of a
power vertical MOSFET sensitive to temperature has been
shown. The modeling approach and the thermal sensitivity of
MOSFET parameters have been discussed. This model is
simple one, the equation used to model the electrical and the
thermal issues are easy to code with any simulator, the non
linear capacitor equation used is more accurate and rapid than
the conventional one used with other models. Finally this
model will be used as a unit for a distributed electro-thermal
simulation, and each unit will give us the image of the local
temperature of the modeled device, which will give us an idea
for the current distribution in the ship and hotspots. Validation
of the model accuracy has been shown. So this work is the first
step to electro-thermal simulation of power device by simulator
coupling.
Fig.11. Drain to source voltage measurement across MOSFET at 25°C and
150°C (dotted)(zoom on oscillations)
The only significant difference between simulation and
measurement is on the final phase “Fig.12.” it’s clear that the
measurement oscillations are more rapidly damped, this is due
to the skin effect.
REFERENCES
[1] JB.Sauveplane et al., “Smart 3-D Finite-Element Modeling for the
Design of Ultra-Low On-Resistance MOSFET”, IEEE Transactions
on Advanced Packaging, Nov. 2007, V30-4,pp 789-794.
[2] JB.Sauveplane et al., “3D electro-thermal investigations for
reliability of ultra low ON state resistance power MOSFET”,
Microelectronics Reliability, V48 - 8-9, Sep. 2008, pp 1464-1467
[3] S.Wünche, “Simulator Coupling for Electro-Thermal Simulation Of
Integrated Circuits”, Therminic’96, 1996, pp 89-93.
[4] F.Morancho, “Modling and performance of vertical trench
MOSFET in power electronics”, Semiconductor Conference, 1995.
CAS'95 Proceedings.
[5] C.Batard ;T.MEYNARD ;H.FOCH ;J.L.MASSOL
“Circuit oriented simulation of power semiconductor using
success.Application, to diodes and bipolar transistors”. EPE’91,
Florence.
[6] David Divins, “Using Simulation to Estimate MOSFET Junction
Temperature in a Circuit Application”. International Rectifier,
October 2007.
Fig.12. Drain to source voltage across MOSFET at 150°C (zoom on
oscillations)
The skin effect causes the effective resistance of the conductor
to increase with the frequency of the current. We used between
35 to 40 cm of a copper conductor cable for the connections
between the circuit elements, that’s mean there is enough cable
length in our circuit that the effective resistance change in the
cables affect the hall circuit performance. The oscillations
frequency is high (more than 1 MHz), so it’s normal that the
resistor increase, and the measured oscillations are damped
than the simulation due to this effective resistor, which had not
been taken into consideration in the simulation circuit .
©EDA Publishing/THERMINIC 2009 90
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Crack Tip Localization of Sub-critical Crack Growth
by Means of IR-Imaging and Pulse Excitation
D. May 1 , B. Wunderle 1,3 , R. Schacht 1,2 , B. Michel 1
1 MicroMaterials Center Berlin, Fraunhofer IZM, Berlin, Germany Email: daniel.may@izm.fraunhofer.de
2 Hochschule Lausitz (FH), Senftenberg, Germany
3 TU Chemnitz, Germany
Abstract- Taking the advantage of the thermo-elastic effect, while
using an infrared camera system, the mechanical stress could be
made visible. The stress concentrations at the tip of a subcritical
crack growth could clearly be detected. Through the observation
during the periodic loading of a CT-specimen the crack growth
rate can be determined. For this purpose, a specially developed
loading stage will be presented. It is now possible to have further
investigation in material class of polymers, which is very
important in the field of system integration. First promising
results will be presented.
I. INTRODUCTION
Today’s need for fast and reliable technology development
including further miniaturization, functionality and complexity at
lower cost is a trend that will continue [1]. To assure reliability for
advanced packages presupposes the understanding and description
of failure mechanisms and to be able to apply them to large models
[2]. For e.g. power packages delamination of the die-attach or
encapsulant is known to be a problem which needs optimization
[3]. Then for e.g. System-in-Package solutions, the number of
interfaces and thus possible delamination sites has increased a
situation where numerical lifetime prediction methods also face the
challenge of availability of critical parameters for materials and
material pairings. These parameters in general are given as energy
release rates for fracture-mechanical treatment and depending on
process conditions, moisture and temperature. These values are
usually had to be measured because they are not readily available
from manufacturer’s datasheets.
Modern Finite Element (FE) tools allow the programming of
routines to calculate energy release rates as failure criterion for a
possible crack in a rather short time [4]. However, the bottle neck is
a rapid and yet accurate determination of critical and undercritical
data for crack growth.
In the past, many different setups have been proposed to study
crack growth ([5,6]). Most of them need complicated methods to
determine the crack length under external loading conditions in
respect to the specimen geometry and the real process conditions.
As for most designs the precise crack length is needed for an
energy release rate and phase angle determination from finite
element simulations, here a new method is proposed using the
transient thermal response of the specimen under different loading
conditions by infrared thermography [7].
The IR thermography is becoming increasingly important for
non-destructive testing of microelectronic components and
structures on the chip, package and board level. Besides the use of
pulse thermography for determining the temperature of thermal
conductivity according to Parker [8] or for detection of
delaminations in micro-electronic thin-film assemblies, and the
degradation of electrical vias in printed circuit boards [9,10] the
lock-in thermography is also used to detect shorts in integrated
circuits. Müller [11] has shown that the lock-in thermography can
be used in investigation of fracture and cracking behavior of steel
components using the thermo-elastic effect [12]. To investigate in
crack propagation in solids, among others, a so called Compact
Tension (CT) specimen is used. If the subcritical crack growth is
examined the sample with strain amplitude less than the critical has
to be loaded periodically. During the experiment the length of the
growing crack must be measured by appropriate methods.
These experiments are carried out, in specially designed testing
equipment. Due to the high costs often only a few of such
machines are available. Therefore long experimental periods are
being developed for a material such as to be characterized under
different temperatures and loads.
To gain even more quickly usable material parameters, e.g. at an
early product development phase and to make a choice of materials
a design of a novel strain apparatus should be as simple and yet as
precise as necessary to carry out several parallel investigations.
This work focuses on the adaptation of the stress analysis on
materials of micro-electronics (e.g. in the system integration very
important material class of polymers).
A. Theoretical Basics
In the early 19th Century, J. Gough [13] observed that the
temperature of a polluted materials changes. The correlation
between mechanical stress and temperature change has J. Thomson
[12] in 1853 first recognized in theory and published. According to
Stanley Chan and Biot [14, 15] the link between material
parameters, state of stress of the sample and the temperature change
can be described as follows:
∆
·
··∆ (1)
where T is the absolute temperature, α is the coefficient of
thermal expansion, ρ the density, c p , heat capacity (at constant
pressure) and Δ (σ1 + σ2 + σ3) the change in the sum of principal
stress (hydrostatic stress).
Here with positive values of the principal stresses (tensile stress)
a cooling and with negative values (compressive load) a warming
take place in the material.
With the development of modern infrared measurement in the
©EDA Publishing/THERMINIC 2009 91
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
1960s it became possible to measure temperature changes C. Experimental Setup
contactless and without feedback on the specimen. With currently To investigate the stress field near the crack tips a suitable
available IR detectors high geometric (

7-9 October 2009, Leuven, Belgium
electromagnetic actuator (B) is connected to modulate driving
DC-Mean value (M)
force. The point of force application is variable, so that a scaling of
force is adjustable from 1 / 10 to 1 / 3.
The driving force can be measured with a load cell placed in the
load path and also by measuring the electrical current of actuator.
30 µm
To measure the strain amplitude directly at the sample a
1 mm
displacement transducer (C) is placed.. With this setup it is possible
to load the sample (A) mechanically and observe the specimen by
IR-camera (E) at a narrow working distance of about 20 mm. An
external PC controls and measures all important values. Both force
and displacement controlled experiments can be conducted.
120 µm
Dynamic loads (triangular, sinusoidal and pulsed) with frequencies
1 mm
up to 5 Hz and forces to 450 N on the sample can be realized.
So it is possible to build a cost burden system.
In a laser safety enclosure this design enables crack tracing by
means of laser pulse excitation.
150 µm
II. EXPERIMANEL RESULTS
Loading amplitude
1 mm
Phase image(P)
1 mm
1 mm
1 mm
In an initial investigation CT-specimen of PMMA were loaded
sinusoidal, with different amplitudes (30, 120, 150 and 250
microns) at a frequency of 0.5 Hz. In figure 4 the observed
(correlation of reference signal and image signal) uniform surface
cooling at the notch groove is shown. There are blue to white areas
of cooling and red to bright yellow areas of warming. The result is
similar in quality as the estimation given in figure 1 (right).
250 µm
1 mm
1 mm
Fig. 5 Phase images and DC-mean value image for different loadings
Figure 5 shows a summarized comparison of results of initial
investigation. The load amplitude was varied from top to bottom
(30 ... 250 microns). The respective left-hand images show the DC
average images. They show qualitatively similar results except of
the smallest load amplitude. Lower DC values are founded with
increasing load. This is expected
by increasing the stresses (σ 1 , σ
2 , σ 3 ) and consequently an improved cooling too. Much more
sensitive are the phase images shown on the right. They are from+
π to - π (3.12 ...- 3.13). Negativee values mean a lagging signal with
respect to the reference signal (here, the sinusoidal stress
amplitude). This behavior is by
equation (1) expected. In tensile
(positive reference signal is the sum of principal stress is positive
and thus results in a negative Δ T. This means a negative surface
signal. Both signals are phase-shifted by 180 ° (-π). This
relationship is clearly seen in the
diagram in Figure 6.
Fig. 4 CT-specimen of PMMA loaded with 30 µm
(without pre crack)
To increase the stress concentration a crack
was introduced with
an industrial razor blade. Taking into account the resulting pixel
resolution of approximately 5.2 microns / pixel of IR-images
a ~ 420 microns crack length can estimate.
surface signal
6450
6440
6430
6420
6410
6400
0,04
0,02
0,00
reference signal
6390
0 100 200
index
300 400 500
of image
Fig. 6 Phase shift between reference signal (displacement transducer)
and surface signal (250 µm load amplitude)
©EDA Publishing/THERMINIC 2009 93
ISBN: 978-2-35500-010-2

III. SUMMARY
In this study it was shown that the temperature changes caused
by the use of thermo-elastic effect can be used to locate areas of
tension in order to localize crack tips. A specially designed loading
device was developed and its suitability was demonstrated.
In the next step the limits and the precision of this method has to
be determined. An automated algorithm to locate the crack tip must
be implemented to perform a full crack propagation experiment.
To assess the competing of elastic/ inelastic effects, a field coupled
FE-simulation has to be performed, to take the transient
temperature behavior into account.
ACKNOWLEDGMENT
The authors appreciate the support of the EU FP 7 Integrated
Projekt “Nanopack”. The authors would also like to acknowledge
the Federal Ministry of Education and Research for financial
support (Program: Entrepreneurial Regions 03IP510). Special thank
to Mr. A. Sattelmayer from TU-Berlin and his team, who ensured
the high quality implementation of the load stage.
REFERENCES
[1] Semiconductor Industry Association, “The
international technology roadmap for semiconductors,” Dez.
2007.
[2] S. Deplanque, W. Nuchter, B. Wunderle, R. Schacht,
und B. Michel, “Lifetime Prediction of SnPb and SnAgCu
Solder Joints of Chips on Copper Substrate Based on Crack
Propagation FE-Analysis,” Proc. 7th International Conference
on Thermal, Mechanical and Multiphysics Simulation and
Experiments in Micro-Electronics and Micro-Systems
EuroSime 2006, 2006, S. 1–8.
[3] B. Wunderle und B. Michel, “Lifetime modelling for
microsystems integration: from nano to systems,” Microsystem
Technologies, vol. 15, 2009, S. 799-812.
[4] J. Auersperg, M. Klein, und B. Michel, “Optimization
of Electronics Assemblies towards Robust Design under
Fracture, Delamination and Fatigue Aspects,” Electronic
Packaging Technology, 2007. ICEPT 2007. 8th International
Conference on, 2007, S. 1-7.
[5] L. Ernst, A. Xiao, B. Wunderle, K. Jansen, und H.
Pape, “Interface Characterization and Failure Modeling for
Semiconductor Packages,” Electronics Packaging Technology
Conference, 2008. EPTC 2008. 10th, 2008, S. 808-815.
[6] G. Schlottig, H. Pape, B. Wunderle, und L.J. Ernst,
“Induced Delamination of Silicon-Molding Compound
Interfaces,” Delft: 2009.
[7] D. May, B. Wunderle, M. Ras, W. Faust, A. Gollhard,
R. Schacht, und B. Michel, “Material characterization and nondestructive
failure analysis by transient pulse generation and
IR-thermography,” Thermal Inveatigation of ICs and Systems,
2008. THERMINIC 2008. 14th International Workshop on,
2008, S. 47-51.
7-9 October 2009, Leuven, Belgium
[8] W.J. Parker, R.J. Jenkins, C.P. Butler, und G.L.
Abbott, “Flash Method of Determining Thermal Diffusivity,
Heat Capacity, and Thermal Conductivity,” Journal of Applied
Physics, vol. 32, 1961, S. 1679-1684.
[9] R. Schacht, M. Abo Ras, D. May, B. Wunderle, und
B. Michel, “Non-Destructive Tests for Via
Structures in Organic Multi Layer PCBs,” Brussels, Belgien:
2009.
[10] R. Schacht, B. Wunderle, D. May, B. Michel, und H.
Reichl, “Modelling guidelines and non-destructive analysis for
thermal and mechanical behaviour of via-structures in organic
boards,” Proc. 11th Intersociety Conference on Thermal and
Thermomechanical Phenomena in Electronic Systems ITHERM
2008, 2008, S. 441–449.
[11] Müller, L., ThermoStrain: Entwicklung eines neuen
Verfahrens zur Dehnungsanalyse beanspruchter Stahlbauteile,
Der Andere Verlag, 2005.
[12] W. Thomson, “On the dynamical theory of heat,”
Trans. Roy. Soc. Edinburgh, vol. 20, 1853, S. 261–283.
[13] J. Gough, “A description of a property of Caoutchouc,
or India rubber; with some reflections on the cause of the
elasticity of this substance,” Memoirs of the Literary and
Philosophical Society of Manchester, 1805, S. 288-295.
[14] M.A. Biot, “Thermoelasticity and Irreversible
Thermodynamics,” Journal of Applied Physics, vol. 27, März.
1956, S. 240-253.
[15] P. STANLEY und W. CHAN, “Quantitative stress
analysis by means of the thermoelastic effect,” The Journal of
Strain Analysis for Engineering Design, vol. 20, Juli. 1985, S.
129-137.
©EDA Publishing/THERMINIC 2009 94
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Thermal matching of a thermoelectric energy
harvester with the environment and its application in
wearable self-powered wireless medical sensors
V. Leonov 1 , P. Fiorini 1 , T. Torfs 1 , R. J. M. Vullers 2 , C. Van Hoof 1
1
IMEC
Kapeldreef 75
3010 Leuven, Belgium
2
Holst Centre / IMEC
High Tech Campus 31
Eindhoven 5656 AE, The Netherlands
Abstract-In this work, we discuss why classical thermoelectric
theory is not enough to design an optimized energy harvester.
Then, the general conditions are defined, which are required to
make a thermoelectric converter effective in such application.
The necessity of the work has been prompted by the fact that
while modeling the harvesters neither the constant temperature
difference, nor the heat flow cannot be assumed. We show that
simple equations obtained using electro-thermal analogy allow
optimization of energy harvesters to reach their top
performance characteristics. Thermal matching in MEMS
thermopiles is discussed then. The examples of application
thermally matched thermopiles for powering state-of-the-art
wearable wireless sensors are discussed in the end.
I. INTRODUCTION
Powering wireless autonomous sensors by using energy
harvesters could move such devices into mass production.
Batteries and wiring are excluded as unrealistic ways. One
thousand wireless sensors per each person is a current vision
of the future wireless sensor network called “ambient
intelligence”. These should be self-powered, preferably
using photovoltaic cells. The thermoelectric conversion of
wasted heat from low temperature sources however is the
best way to provide power autonomy to the devices in
locations, where no daylight and indoor illumination take
place. However, because of energy saving reasons, wasted
heat flows are usually minimized with the use of thermally
isolating materials. Thermoelectric conversion of waste heat
is complicated by the high thermal resistance of the heat sink
(air) and, frequently, of the heat source (e.g., walls of
buildings, plastic pipes, or living beings). The remaining
heat flows and temperature differences available for energy
harvesting are therefore relatively small. However, these
wasted heat flows can be used for eliminating the need of
primary batteries in most of autonomous devices placed
inside buildings, machinery, or in closed compartments, and
forming smart self-organizing autonomous networks. This
paper discusses the principles of designing thermoelectric
generators optimized for energy harvesting on lowtemperature
sources of waste heat. As a proof of concept,
the examples of fully self-powered wearable medical devices
are designed, fabricated and briefly described.
II. THERMOELECTRIC THEORY AND OPTIMIZED
THERMOPILE
In the thermoelectric theory, the optimization of a
thermopile in power generation mode is discussed for two
basic regimes of operation: (i) the heat flow through the
thermopile, W, is constant, i.e., independent of its thermal
resistance R tp
and (ii) the temperature drop on the thermopile,
ΔT, is constant, solid lines in Figs. 1a and 1b, respectively.
There are also the second-order effects that discussed in the
theory. These are Joule heating of thermopiles due to
generated current and Peltier effect. However, these effects
are minor and become important only in case of hightemperature
operation (more than 100°C) and low serial
thermal resistance of the environment, R env , therefore in the
following discussion of energy harvesters we omit these
effects for the sake of simplicity. The power generated by a
thermopile on the matched load in this case is
P = V 2 /4r el = α 2 ΔT 2 /4r el , (1)
Fig. 1. Two regimes of a thermopile operation in power generation mode:
(a) constant heat flow; R tp > R env .
©EDA Publishing/THERMINIC 2009 95
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where V is open-circuit voltage, r el is the resistance of the
thermopile and load, and α is Seebeck coefficient. The
Figure Of Merit, Z, that quantifies thermoelectric quality of
the material is defined as
Z = α 2 σ / k = α 2 R th /r el , (2)
where σ is conductivity, k is thermal conductivity, and R th is
thermal resistance. By substituting (2) in (1) and introducing
a heat flow as W = ΔT/R th , (1) can be rewritten as
P = WZΔT/4 , (3)
where ZΔT/4 is thermodynamic efficiency. The best
thermoelectric materials for low-temperature energy
harvesting show a Z of about 0.003 K -1 . Therefore,
conversion efficiency of thermoelectric generators is at least
by a factor of 4 less than the Carnot efficiency. Equation (3)
is useful for the analysis of two basic regimes of operation of
a thermopile, Figs. 1a, 1b. In Fig. 1a, W is constant, so the
only ΔT in (3) is variable. As a result, the power is
proportional to R th and there is no optimum unless R th → ∞.
When ΔT is constant, Fig. 1b, the power is proportional to
R -1 th . Again, no optimum can be found except R th → 0. The
two limits contradict to each other therefore there must be a
kind of transitional regime between the regimes illustrated in
Figs. 1a, 1b. Because no optimum can be found, the
practical aspects affect the design choice instead of pure
theory, i.e., technological limitations, material properties,
required and feasible dimensions of the device, irreversible
losses and parasitic effects.
While optimization is conducted in case of W = const.
(Fig. 1a), thermal resistance can be increased either by
increasing the length of thermopile legs, l, or decreasing
their lateral dimension, t, Fig. 2. In both cases, the
technology becomes the barrier. In case of optimization at
ΔT = const. (Fig. 1b), thermal resistance can be decreased
either by decreasing the length of thermopile legs or
increasing their lateral dimension. In both cases, the
interfaces start to dominate, e.g., the contact resistance
between metal interconnects and semiconductor legs, and the
thermal resistance of interfaces to the heat source and sink.
7-9 October 2009, Leuven, Belgium
Furthermore, certain variations are observed on practice at
“constant” either heat flow or temperature difference due to
(i) above practical limitations and (ii) non-perfect both heat
sources and heat sinks. The effect is qualitatively shown in
Figs. 1a, 1b as dashed lines. Suspecting that a smooth
transition must take place from Fig. 1a to Fig. 1b, one may
qualitatively connect these Figs. as shown in Fig. 1 (dotted
lines). This area between Figs. 1a and 1b seems to be the
most interesting regime. Indeed, the optimization at W =
const. takes place to the right of Fig. 1a while optimization at
ΔT = const. takes place to the left of Fig. 1b. The reader
may also pay an attention at (3), which states that power is
proportional to the product of W by ΔT. Therefore, not
much power is produced at maximum thermodynamic
efficiency, Fig. 1b, while maximum power is not produced at
maximum heat flow either.
III. THERMOPILE AT VARIABLE BOTH HEAT FLOW AND
TEMPERATURE DIFFERENCE
Basing on above discussion, Figs. 1a and 1b are combined
in one Fig. 3. X-axis is replaced with the ratio of the thermal
resistance of thermoelectric generator (TEG), R TEG
, to the one
of the environment, R env
. Indeed, not the absolute value of
the thermal resistance of thermopile allows constant either
heat flow or temperature difference, but the ratio R TEG
/R env
.
The heat flow is constant in Fig. 1a because it is fully limited
by R env
(in case of energy harvesters). In Fig. 1b, constant
ΔT is provided by the environment with very low thermal
resistance. Once R TEG
approaches from either side to R env
,
neither W nor ΔT can remain constant and change as shown
by dashed lines in Figs. 1a, 1b. Using (3), the reader can
already qualitatively plot the dependence of power, Fig. 3.
According to the thermal circuit, Fig. 2, the ΔT observed
between the heat source and heat sink cannot appear on the
thermopile because of non-zero value of R env
. The task of
this Section is to find the temperature difference on the
thermopile, ΔT tp , corresponding to the power maximum.
Based on electro-thermal analogy, Fig. 2, R TEG
must be
comparable to or larger than the one of the serial thermal
resistor R env
. (This is to obtain large voltage on R tp
in an
electrical circuit, or to obtain large ΔT tp in a thermal circuit.)
This also means that while optimizing the device, i.e.,
changing its thermal resistance, neither constant temperature
metal
n
l
R cold R TEG R hot
p
t
Fig. 2. Thermoelectric generator (TEG) and its thermal circuit. The thermal
resistance of the environment is composed of a thermal resistance between
(i) the heat sink or (ii) the point where heat is generated and corresponding
metal-semiconductor p-n junction plane of a thermopile. Any additional
TEG elements (such as screws or a sealing sidewall on the perimeter of
thermopile) thermally interconnecting the two plates, as well as air between
them and radiation, are denoted as R pp (parallel parasitic thermal resistance).
ΔT/ΔTmax; W/W max; P/Pmax
1
0.8
0.6
0.4
0.2
0
W tp P
ΔT tp
0.01 0.1 1 10
R TEG /R env
Fig. 3. Normalized heat flow through a thermopile (R tp), the temperature
difference on it, and the power. Location of maxima can be at the other
R TEG/R env. The curves end on the left at complete filling of a TEG (fixed
size) with thermocouples, and on the right, with the only one thermocouple.
©EDA Publishing/THERMINIC 2009 96
ISBN: 978-2-35500-010-2

difference on the TEG, nor constant heat flow through the
TEG can be assumed. Let us consider a simplified case of a
TEG, assuming that R env
is independent of temperature (e.g.,
in case of small ΔT) and that only air contributes to R pp
, so
that R pp
= R air
= const. We assume that hot and cold plates
have the area A. The two resistors in a TEG, Fig. 2, are:
l
Rtp = , (4) and
l
Rair
= , (5)
ktpa
kair
( A − a)
where l is also the distance between the plates, k tp
and k air
are
the thermal conductivities of thermoelectric material and air,
respectively, and a is the area of thermoelectric material in
the plane parallel to the plates. The temperature drop on the
thermopile is:
R
Δ , (6)
T
TEG
tp = ΔT
Renv
+ RTEG
which can be re-written using the thermal conductance of the
environment G env
= 1/R env
as:
G l
Δ T T
env
tp = Δ
. (7)
G l + k a + k ( A − a)
env
By substituting (7) into (1), the power on the matched
electrical load is:
2
2
2
env
α ΔT
G l
a
P = ⋅
, (8)
4ρ
2
[( G l + K A)
+ a(
k − k )]
env
where ρ is resistivity. The optimum value of a depends on
the environment and equal to a opt = (G env l + k air A)/(k tp – k air ),
so that the power maximum can be expressed using R env and
R empty = l / k air A as:
P
max
2 2
α ΔT
ρ ( ktp
− kair
tp
air
1
= .
, (9)
16 ) (1 + R / R ) R
env
air
tp
empty
where R empty denotes the thermal resistance of the same TEG,
but with no thermocouples between the plates, i.e., of the
empty TEG; this is its parasitic thermal resistance.
Substituting a opt into (7), the optimal temperature difference
ΔT tp , corresponding to the maximal power, is:
ΔT
Δ Ttp,
opt =
. (10)
2 (1 + Renv
/ Rempty
)
Equation (10) shows that if R env /R empty

V. THERMAL MATCHING IN LOW-DIMENSIONAL
THERMOPILES
Equation (9) states that a thermopile of any size produces
the same power if R env /R empty and R env stay the same. It also
shows two complementary ways to increase power. First,
the thermal resistance of empty TEG must be maximized
thereby providing R env /R empty much less or at least less than
one and, second, the thermal resistance of the environment
must be decreased as much as possible.
An energy harvester is considered to be a small device that
can be attached (glued, screwed) to the heated or cooled
surface. Therefore, at least from one of its sides, either cold
or hot one, the heat must flow into/from the ambient air. In
general, it is typically almost still air, so the heat transfer
coefficient at a small available temperature difference, ΔT, is
very small. The temperature difference between the ambient
air and the outer side of a TEG contacting it will be further
decreased according to (10) even on a heated machine with a
near-zero R hot , Fig. 2. This is because the temperature
difference on the optimized thermopile could reach ΔT/2.
The easiest way to decrease the thermal resistance of a heat
sink in such energy harvester is to provide it with a radiator.
If the latter is considered to be too bulky, e.g., in a thin TEG,
the outer plates of the TEG must be made large enough to
provide low R env .
The parasitic thermal resistance of the air inside the TEG
can be maximized by filling it with a gas having low thermal
conductivity, and at lower pressure, or in a vacuum.
However, the vacuum-tight encapsulation can provide lower
R pp than air-filled thermopile with no such encapsulation.
Furthermore, in mass production, it would adversely affect
the production cost. The microelectronic and film-based
technologies, in principle, could decrease the production cost
of thermopiles. Let us calculate what would happen with
power maximum if a thermopile of the same design as in
Fig. 2 is scaled down. Of course, the body of the TEG with
two large outer surfaces must not be decreased because R env
must be kept as low as possible to maximize the power, (9).
To give a numerical example, we will calculate scaling of
the thermopile down in a wearable TEG. In such a device,
the heat source (human body) with a deep body core
temperature of 37°C is assumed to have a constant (for
simplicity) thermal resistance of 300 cm 2 K/W. The heat
sink (the ambient air) at a temperature of 22°C also has a
constant thermal resistance of 700 cm 2 K/W. Such thermal
resistance can be provided by forced convection (some wind,
a fan, or on a walking person) or in a still air if a cold plate is
replaced with the fin- or pin-featured radiator with a feature
height of a few millimeters. Therefore, ΔT = 15°C and
R env = R hot + R cold = 10 3 cm 2 K/W. For the modeling, the
following characteristics of thermoelectric materials are
taken: a Z of 3 × 10 -3 K -1 , a resistivity of 1 mΩ cm and a
thermal conductivity of 0.015 W/cm K. We assume a size of
3 cm × 3 cm for the plates of a TEG located at 1.5 cm
distance from each other. Then, on the TEG area, R env = 110
K/W and R empty = 640 K/W, so that R env /R empty = 0.17 and the
both power and ΔT tp reach about 85% of theoretically
possible maxima, (9) and (10). The distance between
7-9 October 2009, Leuven, Belgium
adjacent thermocouples is assumed to be equal to the lateral
dimension of legs, t, so that the thermocouple leg occupies
an area of 2t × 2t. While the thermopile is scaled down, it
occupies smaller area on the hot plate. To provide effective
heat transfer to the cold plate, the thermopile is connected to
the cold plate through the thermally conducting pillar with a
cross section of 2 mm × 2 mm, Fig. 4. The thermopiles with
l ≤ 0.1 mm occupy area less than the cross section of the
pillar. Therefore, for such thermopiles, the pillar end is
made of pyramid shape. At last, it is assumed in the
modeling that a thermopile must produce 1 V on the
matched load.
The results of scaling the thermopile in the TEG are
shown in Figs. 5, 6. After initial drop of R pp caused by
decreased distance between the tip of the pillar and the
opposite plate, Fig. 5, R pp stays practically the same. Ideally
it would stay constant even at l = 1 μm [1] however in our
calculations, we have assumed a metal-semiconductor
contact resistance of 100 Ω μm 2 . As a result, at l < 300 μm,
the resistance of the thermopile rapidly increases, Fig. 5.
According to modeling results, at l = 1 μm, it would increase
to 90 kΩ, i.e, by a factor of 30 as compared with 1.5 cm-long
thermopile (dotted line in Fig. 5), and the power would
decrease by the same factor. To prevent this power loss, in
the thermocouples with l < 30 μm, a metal-semiconductor
a b c
Fig. 4. Scaling of a thermopile in a TEG: (a) classic thermopile with high
l/t ratio to be scaled down, (b) a pillar interconnects the outer TEG plate
with one of the plates of a thermopile (medium l/t ratio), (c) at the end of
scaling, microelectronics technology can be used because l/t ratio is small.
Thermal resistance (K/W)
1000
100
10
R pp
R tp
ΔT tp
0.001 0.01 0.1 1 10 100
Length of thermocouple legs (mm)
100
Fig. 5. Optimum values of thermal resistances in the TEG and the
temperature drop on the thermopile, and its resistance in a wearable TEG
of 3 cm × 3 cm × 1.7 cm size at a contact resistance of 100 Ω μm 2
between semiconducting legs and metal interconnects.
r
10
1
r (kΩ); ΔTtp ( o C)
©EDA Publishing/THERMINIC 2009 98
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Power (μW);
Number of thermocouples .
1500
1000
500
0
n/2
l /t
0.001 0.01 0.1 1 10 100
Length of thermocouple legs (mm)
interface area of 10 × 10 μm 2 is assumed (fixed) while t
decreases to 2 μm at l = 1 μm. (On practice, this is done by
using microelectronic technologies [2].) At l = 1 μm, the
resistance still increases by a factor of 4 as compared with
1.5 cm-long thermopile. If the contact resistance could be
decreased to 10 Ω μm 2 , it would allow reaching over 200
μW at l = 10 μm (i.e., about 64% of the power obtainable at
l = 15 mm), and 180 μW at l = 3 μm. Calculations show that
the thermal resistance of the thermopile and the temperature
drop on it stay almost the same over the whole range for a
thermocouple length, Fig. 5, unless the enlargement of
electrical contacts is performed at l < 10 μm. This
enlargement also adversely affects the parasitic thermal
resistance R empty at l < 10 μm, Fig. 5, and demands reoptimizing
the thermal resistance of a thermopile using the
equation of thermal matching. To compensate for some
decrease of ΔT at l < 10 μm due to enlargement of electrical
contacts, a number of thermocouples, equal to n/2, is
increased, Fig. 6. The ratio l / t shown in Fig. 6 demonstrates
that the length of thermocouple legs in the range of 5-10 μm
allows reaching relatively high power using microelectronic
technologies. The related research is ongoing and 6 μm-tall
structures have been already fabricated, Fig. 7 [3]. However,
the structures are based on poly-SiGe that shows far worse
thermoelectric properties than BiTe used in the modeling
above, i.e., its factor Z is about 0.05-0.1, at least by a factor
of 10 less. Therefore, one more step is required for reaching
the calculated targets, i.e., development of the similar
technological process, but based on materials with higher Z.
P
7-9 October 2009, Leuven, Belgium
100
VI. APPLICATION OF THERMAL MATCHING IN
WEARABLE MEDICAL DEVICES
10
1
0.1
Fig. 6. Optimum number of thermocouples, l / t ratio and maximum power
in a wearable TEG of 3 cm × 3 cm × 1.7 cm size at a contact resistance of
100 Ω μm 2 between semiconducting legs and metal interconnects.
Al
p-SiGe
n-SiGe
3 μm
Fig. 7. Arcade thermopile: the design and fabricated thermopile-like test
structure with 6 μm-tall released air bridges [3].
l / t ratio
Small-size thermopiles available on the market do not fit
the requirements for the thermocouple leg length coming out
of the modeling of an optimal thermopile because their l / t
ratio is much smaller than needed. An appropriate aspect
ratio then can be obtained by stacking thermopiles on top of
each other [4, 5]. This increases R TEG
to the required R TEG,opt
and hence allows reaching the maximum of output power.
Before fabricating prototypes of body-powered medical
devices, the principles of thermal matching have been
verified on watch-size wrist TEGs [4, 5]. Then, one of such
TEGs has been used for powering a wireless pulse oximeter
(SpO 2
sensor) [6], Fig. 8a. The device non-invasively
measures oxygen content in arterial blood. A TEG used in
this device provides a power of about 200 µW on average
with usual variations within the 100-600 µW range.
Typically, battery-powered pulse oximeters existing on the
market consume above 10 mW. Therefore, before making it
powered from the human body, a power consumption of
electronics has been reduced by a factor of 10 3 . As a result,
the electronics module and 2.4 GHz wireless link together
consume 62 µW. The device is battery-less and operational
up to 25-26°C. At higher ambient temperatures, the power
shortages are expected. If this happens, the device switches
into a sleeping regime for a while. During sleep, its power
consumption is extremely low and the device wakes up again
upon collecting enough charge in the supercapacitor.
Another example of body-powered battery-less devices is
an electroencephalography (EEG) system-in-a headband [7]
consuming 0.8 mW. The main challenges in creation such
complex system powered by the wearer’s heat are (i)
lowering power consumption of biopotential readout while
maintaining the signal quality and (ii) real-time data
transmission. In the above pulse oximeter, the signal
processing is performed onboard, so that power consumed
by the transceiver is minimal. In EEG, on the contrary, realtime
brain waveform should be transmitted, so the radio
consumes large power, and a large-size TEG is required.
Therefore, it is designed as 10 sections of 2×4 cm 2 size on a
stretchable headband, Fig. 8b. Radiators on the outer side of
thermopiles ensure effective thermal matching of the TEG
with the environment. The TEG is designed for indoor use at
typical ambient temperatures maintained in hospital wards.
At 22°C, it produces about 30 µW/cm 2 , i.e., close to the limit
of power on people at this temperature. There is however a
drawback of such high power generation: at lower ambient
temperatures, the heat flow rapidly exceeds the sensation of
discomfort and the device turns into uncomfortably cold
object. (For example, at 19°C, the TEG already produces
3.7 mW, but sensation of cold becomes too annoying.)
To avoid sensation of cold, another version of the EEG
system, a headphone-like EEG diadem, Fig. 8c, has been
provided with a hybrid thermoelectric-photovoltaic energy
harvester, [7]. This device is comfortable down to 7°C.
The electrocardiography (ECG) system-in-a-shirt, Fig. 8c,
unlike above devices, is powered from a secondary battery
[8]. The battery is constantly recharged using the wearer’s
body heat. The power consumption is 0.5 mW, so about
0.7 mW are required from the TEG. Fourteen 6.5 mm-thin
©EDA Publishing/THERMINIC 2009 99
ISBN: 978-2-35500-010-2

Fig. 8. Low-power wireless medical sensors powered by thermally matched
thermoelectric generators: (a) a pulse oximeter, (b) EEG headband with 2.5
mW-TEG, (c) a person wearing an EEG diadem with hybrid power supply,
an SpO 2 sensor, ECG system-in-a-shirt, and a TEG with micromachined
poly-SiGe thermopile (still produces very small power).
TEG modules of 3 cm × 4 cm size have been integrated into
the front side of shirt. The radiators of TEG modules have
been painted like chameleon into the shirt colors, except one
module that is to show the module size. The wiring and the
other modules of ECG system are located on the inner side
of the shirt. In the office, the TEG typically generates the
power of 0.8-1 mW. Because of high thermal resistance of
thermally matched TEG modules, they are never cold. In
cold weather, the other pieces of clothing are worn on top of
shirts. However, as measured at about 10°C outdoors on a
person wearing a thick jacket, the power typically does not
decrease. The power management module contains a fully
integrated DC/DC upconverter that charges a 2.4 V NiMH
battery. The converter contains a charge pump with variable
number of stages and switching rate, and therefore operates
with near-maximum efficiency. In parallel to the TEG
power circuit there is a secondary parallel circuit that allows
charging the battery directly from solar cells. Two
amorphous silicon solar cells of 2.5 cm × 4 cm size each
have been integrated into the shirt on its shoulders. Solar
cells are added to the system because if the shirt is not worn
for months, the battery can be discharged. Therefore, when
the shirt is taken off and not used for a long time, it must be
stored in an environment where light is available
periodically, e.g., in a wardrobe with windows. The small
power provided by solar cells is enough to compensate for
the self-discharge of the battery and for the standby power.
In this way, even after months of non-use, the electronics is
maintained in the ready-to-start state, waiting for the
moment the shirt is used again. The system components,
i.e., a TEG, solar cells and electronics in a flex circuit, have
waterproof encapsulation and sustain machine washing with
drying cycle at 1000 rpm. If the voltage from the TEG drops
to near-zero, which happens when the shirt is taken off, the
system switches into a standby regime with 1 μW power
consumption. The self-start of the system takes place within
a few seconds while the shirt is being put on again.
7-9 October 2009, Leuven, Belgium
VII. CONCLUSION
The thermoelectric theory does not describe how to
perform design optimization of a thermopile in energy
harvesters. Therefore, all the works on micromachined
thermopiles for harvesting low-grade heat waste have
resulted in thermopile samples producing power insufficient
for a majority of practical applications. The reasons for that
are relatively high thermal resistance of the environment,
and variable both heat flow and temperature difference on
the thermopile under optimization. However, according to
the literature, the optimizations were always conducted at a
constant ΔT, i.e., in a quite different regime. As discussed in
this work, a new approach based on electro-thermal analogy
helps to find design optimum. This optimum is described by
the thermal matching of a thermopile to the environment.
The optimum is located just between the two regimes
discussed in the thermoelectric theory, i.e., the regime of
constant heat flow and the regime of constant temperature
difference. The latter allows highest thermoelectric
efficiency however as has been shown in this work, the
power maximum takes place at about a half of efficiency.
The method of thermal matching discussed in this paper
has been successfully used in wearable wireless medical
sensors: a pulse oximeter, EEG systems and the ECG system
integrated into a shirt.
ACKNOWLEDGMENT
The work has been performed in 2005-2009 within the
internal Human++ program at IMEC and Holst Centre on
wearable wireless sensor networks.
REFERENCES
[1] V. Leonov, “Thermal shunts in thermoelectric energy scavengers,”
Journal of Electronic Materials, vol. 38, no. 7, pp. 1483-1490,
2009.
[2] Z. Wang, V. Leonov, P. Fiorini, and C. Van Hoof, “Realization of a
wearable miniaturized thermoelectric generator for human body
applications,” Sensors and Actuators A: Physical, 2009, (in press),
DOI: 10.1016/j.sna.2009.02.028.
[3] J. Su, R. J. M. Vullers, M. Goedbloed, Y. van Andel, R. Pellens, C.
Gui, V. Leonov, and Z. Wang, “Process development on largetopography
microstructures for thermoelectric energy harvesters,”
Proc. 8th PowerMEMS + microEMS Workshop, Sendai, Japan,
November 9-12, 2008, pp. 365-368.
[4] V. Leonov, T. Torfs, N. Kukhar, C. Van Hoof, and R. Vullers,
“Small-size BiTe thermopiles and a thermoelectric generator for
wearable sensor nodes,” Proc. 5 th Eur. Conf. on Thermoelectrics,
Odessa, Ukraine, September 10-12, 2007, pp. 76-79.
[5] V. Leonov, T. Torfs, P. Fiorini, and C. Van Hoof, “Thermoelectric
converters of human warmth for self-powered wireless sensor
nodes,” IEEE Sensors J., vol.7, no.5, pp. 650-657, 2007.
[6] T. Torfs, V. Leonov, and R. Vullers, “Pulse oximeter fully powered
by human body heat,” Sensors and Transducers Journal, vol. 80,
no. 6, pp. 1230-1238, 2007; http://www.sensorsportal.com/
HTML/DIGEST/P_151.htm.
[7] M. Van Bavel, V. Leonov, R. F. Yazicioglu, T. Torfs, C. Van Hoof,
N. E. Posthuma, R. J. M. Vullers, “Wearable battery-free wireless
2-channel EEG systems powered by energy scavengers,” Sensors &
Transducers Journal, vol. 94, no. 7, pp. 103-115, 2008;
http://www.sensorsportal.com/HTML/DIGEST/P_300.htm.
[8] V. Leonov, T. Torfs, I. Doms, R. F. Yazicioglu, Z. Wang, C. Van
Hoof, and R. J. M. Vullers, “Wireless body-powered
electrocardiography shirt,” Proc. 3 rd European Conf. Smart Systems
Integration, Brussels, Belgium, March 10-11, 2009, VDE VERLAG
GMBH: Berlin, T. Gessner, Ed., pp. 307-314, 2009.
©EDA Publishing/THERMINIC 2009 100
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Boiling Heat Transfer and Flow Regimes in
Microchannels – a Comprehensive Understanding
Suresh V. Garimella and Tannaz Harirchian
Cooling Technologies Research Center
School of Mechanical Engineering and Birck Nanotechnology Center
Purdue University
West Lafayette, IN 47907-2088 USA
sureshg@purdue.edu
Abstract - Although flow boiling in microscale passages has
received much attention over the last decade, the
implementation of microchannel heat sinks operating in the
two-phase regime in practical applications has lagged due to the
complexity of boiling phenomena at the microscale. This has led
to difficulties in predicting the heat transfer rates that can be
achieved as a function of the governing parameters. From
extensive experimental work and analysis conducted in recent
years in the authors’ group, a clear picture has emerged that
promises to enable prediction of flow boiling heat transfer over
a wide parameter space. Experiments have been conducted to
determine the effects of important geometric parameters such
as channel width, depth, and cross-sectional area, operating
conditions such as mass flux, heat flux and vapor quality, as
well as fluid properties, on flow regimes, pressure drops and
heat transfer coefficients in microchannels. High-speed flow
visualizations have led to a detailed mapping of flow regimes
occurring under different conditions. In addition, quantitative
criteria for the transition between macro- and micro-scale
boiling behavior have been identified. These recent advances
towards a comprehensive understanding of flow boiling in
microchannels are summarized here.
I. INTRODUCTION
Boiling in microchannels and minichannels has been
investigated extensively in recent years. Flow boiling
regimes have been visualized and heat transfer rates and
pressure drops compared to those in larger-scale channels.
Two-phase flow under adiabatic conditions has also been
studied. As noted in the review by Garimella and Sobhan
[1], most of the recent literature on boiling in microchannels
is aimed at electronics cooling applications and is focused on
assessing and correlating the heat transfer coefficient,
pressure drop, and critical heat flux; however, these studies
have not arrived at comprehensive predictive correlations or
design guidelines for microchannels in two-phase operation.
While the dependence of flow characteristics and heat
transfer on channel geometry, operating conditions, and fluid
properties has been investigated in a number of studies, only
limited success has been achieved in generalizing results
from specific studies to a wide range of microchannel
parameters as demonstrated quantitatively in [2]. In a recent
review of flow boiling in small channels by Bertsch et al.
[3], many conflicting trends were observed for dependence
of boiling heat transfer on geometrical and flow parameters.
Garimella and Sobhan [1] noted similar discrepancies
between the results from various single-phase microchannel
studies in the literature and related these conflicting trends to
entrance and exit effects, nonuniformity of channel
dimensions and differences in surface roughness,
thermophysical property variations, nature of the thermal
and flow boundary conditions, and uncertainties and errors
in instrumentation, measurement and measurement locations.
These reviews demonstrate the clear need for systematic
studies which carefully consider different parameters
influencing transport in microchannels, since a reliable
prediction of the heat transfer rates and pressure drops in
microchannels is not possible for design applications such as
microchannel heat sinks due to the diversity in the results in
the literature.
A review of the literature shows that the influence of a
number of the governing parameters, such as microchannel
geometry, mass flux, heat flux, vapor quality and fluid
properties, on flow boiling heat transfer were not clearly
elucidated. In addition, issues such as flow instability, flow
reversal, and large pressure drops were considered as
potential impediments to practical implementation. Also,
despite the large number of empirical correlations proposed
for the prediction of boiling heat transfer and pressure drop
in microchannels, robust design criteria for microchannel
heat sinks are as yet unavailable due to the applicability of
these correlations being limited to narrow ranges of
experimental conditions [3, 4].
Recent experimental investigations and analyses in the
authors’ group [3-17] have led to a more comprehensive
understanding of the physical mechanisms and parameter
dependencies in microchannel flow boiling, which promises
to enable prediction of flow boiling heat transfer over a wide
parameter space. Experiments have been conducted to
determine the effects of important geometric parameters,
operating conditions and fluid properties, on the flow
regimes and thermal performance of microchannels. The
present work summarizes detailed flow regime maps
developed via high-speed flow visualizations.
©EDA Publishing/THERMINIC 2009 101
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7-9 October 2009, Leuven, Belgium
Nondimensional parameters which govern the occurrence
and extent of flow confinement, as well as quantitative
criteria for the transition between macro- and micro-scale
boiling behavior are presented. These recent advances
towards a comprehensive understanding of flow boiling in
microchannels are summarized here. Flow instability and
flow reversal, as well as means for their mitigation, are also
discussed.
II. EXPERIMENTS
Several different substrates and fluids have been
investigated in the experiments in the authors’ group. The
experiments conducted with a perfluorinated dielectric
liquid, FC-77, using silicon test pieces with imbedded
microscale temperature sensors are described here; other test
facilities utilizing copper substrates and water and
refrigerants as the working fluid are described in [5, 6, 8].
The silicon test pieces are used to study flow patterns, local
heat transfer coefficients, and pressure drop during flow
boiling in microchannels over a wide range of flow and
geometric parameters. Only key features of the experiments
are explained here; more details of the test section assembly,
flow loop, and calibration procedures are available in
Harirchian and Garimella [5].
A. Experimental Setup
The test loop consists of a magnetically coupled gear
pump, a preheater installed upstream of the test section to
heat the coolant to the desired subcooling temperature, and a
water-to-air heat exchanger located downstream of the test
section to cool the fluid before it enters a reservoir. The
liquid is fully degassed before initiating each test using two
degassing ports and the expandable reservoir. Details of the
expandable reservoir design and the degassing procedure are
available in Chen and Garimella [10]. A flow meter with a
measurement range of 20-200 ml/min monitors the flow rate
through the loop and five T-type thermocouples are utilized
to measure the fluid temperature at different locations in the
loop. The pressure in the outlet manifold of the test section
is maintained at 1 atmosphere. The pressure in the inlet
manifold and the pressure drop across the microchannel
array are measured using a pressure transducer and a
differential pressure transducer, respectively.
Heater and
temperature
sensor leads
Silicon microchannel
heat sink with
integrated heaters
and temperature
sensors
Fig. 1. A representative microchannel test chip.
The microchannel test piece shown in Fig. 1 consists of a
12.7 mm × 12.7 mm silicon substrate mounted on a printed
circuit board. Parallel microchannels of rectangular crosssection
are cut into the top surface of the silicon chip using a
dicing saw. A polycarbonate top cover positioned above the
test piece and sealed with an O-ring provides enclosed
passages for the liquid through the microchannels.
Twelve test pieces, with microchannel widths ranging
from 100 μm to 5850 μm and depths ranging from 100 μm to
400 μm, are included in the experimental investigation. The
aspect ratio and hydraulic diameter of the microchannels in
the different test pieces take values from 0.27 to 15.55 and
96 μm to 707 μm, respectively. The width (w), depth (d),
and number (N), along with the hydraulic diameter (D h ),
aspect ratio (w/d), and single channel cross-sectional area
(A cs ) of the microchannels in each test piece are provided in
[11]. The average roughness of the bottom wall of the
microchannels ranges from 0.8 to 1.4 μm for the different
test pieces as measured by an optical profilometer; the
bottom wall of the 100 μm-wide microchannels has a lower
average roughness of 0.1 μm since a single dicing cut was
used in their fabrication. The surface roughness of
microchannel side walls is 0.1 μm as measured by a probetype
profilometer.
A 5 × 5 array of individually addressable resistance heat
sources is fabricated on the underside of the silicon chip. In
the present work, a uniform heat flux is provided to the base
of the microchannels. Also, a like array of temperaturesensing
diodes facilitates local measurements of the base
temperature. For a given current passing through a diode
temperature sensor, the voltage drop across the diode
determines the wall temperature. Details of the integrated
resistance heaters and diode temperature sensors, as well as
the procedures used to calibrate the heaters and sensors, are
provided in [9].
Experiments are conducted with the 12 test pieces to study
the effects of microchannel dimensions on the boiling heat
transfer and flow patterns for four mass fluxes ranging from
225 to 1420 kg/m 2 s. For each test, the liquid is driven into
the loop at a constant flow rate and preheated to
approximately 92°C, providing 5°C of subcooling at the inlet
of the channels. While the flow rate and the inlet fluid
temperature are kept constant throughout the test, the
uniform heat flux provided to the chip is incremented from
zero to the point at which the maximum wall temperature
reaches 150°C, which is the upper limit for the safe
operation of the test chips. Heat flux values approaching
critical heat flux are not used in the experiments since the
corresponding temperatures could cause the solder bumps in
the test chip to fail.
At each heat flux and after the system reaches a steady
state, high-speed visualizations are performed
simultaneously with the heat transfer and pressure drop
measurements. Movies of the flow patterns are captured at
various frame rates ranging from 2,000 frames per second
(fps) to 24,000 fps, with the higher frame rates used for the
smaller microchannels at the larger heat and mass fluxes.
The images obtained from the camera are then postprocessed
using a MATLAB [18] code developed in-house
to enhance the quality of the images, especially for those
©EDA Publishing/THERMINIC 2009 102
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7-9 October 2009, Leuven, Belgium
captured at higher frame rates.
B. Flow Instabilities
Chen and Garimella [10] investigated the effect of
dissolved air on flow boiling of FC-77 in microchannels
using a carefully designed degassing scheme. Their study
showed that dissolved air significantly affects both heat
transfer and pressure drop in microchannels. They also
observed larger flow instabilities in terms of pressure drop
fluctuations for the undegassed liquid.
In all the rest of the experiments conducted in the authors’
group, the liquid in the test loop is fully degassed before
initiating each test to help minimize flow instabilities. Also,
a throttling valve positioned upstream of the test section
serves to suppress instabilities in the microchannel heat sink.
Mild flow reversals were still observed at the inlet of the
microchannels at the highest heat fluxes studied, for
microchannels of cross-sectional area 0.144 mm 2 and
smaller. However, these instabilities did not affect the inlet
fluid temperature, which is held constant throughout each
test.
C. Data Reduction
The local heat transfer coefficient, h , is calculated from
h = q′′
w
/ ( Tw − Tref
)
(1)
where T is the local mean fluid temperature in the singlephase
region and the liquid saturation temperature in the
ref
two-phase region, and T w
is the local microchannel wall
temperature. The heat flux used in (1) is the wall heat flux
and is defined as
( )
q′′ = q / A /25
(2)
w net t
where q
net
is the net heat transfer rate to the fluid and A
t
is
the total heated area of the microchannels, with L being the
microchannel length:
t
( 2 )
A = N w+ d L
(3)
The calculated local heat transfer coefficients presented
here are based on measurements from the temperature sensor
located along the centerline of the test piece near the flow
exit. Flow visualizations are also reported from this
location.
Important nondimensional parameters often used in flow
boiling include Reynolds number, Re, Bond number, Bo, and
Boiling number, Bl. Reynolds number is calculated using
the liquid phase mass flux as:
Re = GD / μ
(4)
where G is the liquid mass flux and μ is the dynamic
viscosity of the liquid. Bond number represents the ratio of
buoyancy force to surface tension force and assumes
importance in microscale boiling:
( ) 2 f g
/
Bo = g ρ − ρ D σ
(5)
here, ρ
f
and ρ
g
are the density of the liquid and vapor
phases, respectively, and σ is the liquid surface tension.
As demonstrated in Harirchian and Garimella [11], the
channel cross-sectional area plays a critical role in
determining microchannel boiling mechanisms and heat
transfer; therefore, the length scale used in (4) and (5) is the
square root of the cross-sectional area of one channel rather
than its hydraulic diameter. Boiling number is the
nondimensional form of the heat flux and is calculated using
the liquid mass flux and latent heat, , as follows:
h
Bl q′′
/ Gh
w
fg
fg
= (6)
Following a standard uncertainty analysis [19], the
uncertainties associated with the wall heat flux and the heat
transfer coefficient are estimated to be 2 to 4% and 2.2 to
4.8%, respectively, for the cases considered. Details of the
measurement uncertainties are discussed in [11].
IV.
RESULTS AND DISCUSSION
A. Flow Visualizations
In Harirchian and Garimella [12], flow visualizations were
performed with simultaneous heat transfer measurements
during flow boiling in microchannels of different sizes for
different flow rates. Five major flow regimes of bubbly,
slug, churn, wispy-annular, and annular flow, and a postdryout
regime of inverted-annular flow were identified in
these microchannels, for which representative visualization
images are provided in Fig. 2. Detailed descriptions of these
regimes and the changes in flow regimes with microchannel
size and mass flux are discussed in detail in [12].
Fig. 3 shows a summary of the existing flow regimes at
different microchannel sizes and mass fluxes. It is seen that
in the smaller microchannels and at lower mass fluxes,
bubbly flow is not established; instead, slug flow is observed
for low heat fluxes. In slug flow, elongated vapor bubbles
are confined within the channel cross-section and are
separated from the walls by a thin liquid layer. As the heat
flux is increased, an alternating churn and confined annular
flow appears in these microchannels. In confined annular
flow, the vapor core occupies the whole cross-section of the
microchannels and is separated from the walls by a thin
liquid film.
As the channel cross-sectional area or the mass flux
increases, bubbly flow is observed at low heat fluxes. In the
bubbly flow regime, bubbles are smaller relative to the cross
section of the channels and confinement is not observed. At
higher heat fluxes, alternating churn and wispy-annular or
annular flow occurs. In wispy-annular or annular flow, the
vapor core does not necessarily occupy the entire crosssection
and can instead exist on only one side of the channel;
in other words, the flow is not confined by the channel walls.
For example, as can be seen in Fig. 4(b) for the 2200 μm
× 400 μm microchannels the wispy-annular flow (or annular
flow in Fig. 4(c)) and churn flow patterns are distributed side
by side across the width of the channel due to the large
channel aspect ratio, as also explained in [12].
©EDA Publishing/THERMINIC 2009 103
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7-9 October 2009, Leuven, Belgium
Flow direction
Bubbly flow
Vapor bubbles
(a)
Bulk liquid
Slug flow
Elongated vapor bubbles
(b)
Liquid slug
Vapor bubbles
Churn flow
Bulk liquid
(c)
Vapor chunks
Wispy-annular flow
Vapor core
Thin liquid film
(d)
Liquid droplets
Vapor bubble
Annular flow
Vapor core
Thin liquid film
(e)
Liquid droplets
Inverted annular flow
Liquid core
Thick vapor blanket
(f)
Fig. 2. Description of observed flow boiling regimes [12].
1420
G(kg/m 2 s)
225 630 1050
B
C/W
B
C/W
B
C/W
B
C
B
B/S
C/A
S
C/A
B
B
B/S
B
B
B/S
B
C/W
B/S
S
B
B/S
C/A
S
C/A
S
C/A
S
C/A
C/A
C/W
C/A
C/W
C/A
C/W
C/A
C/W
C/A
C/A
C/A
5850 x 400 (2.201)
2200 x 400 (0.815)
1000 x 400 (0.366)
1000 x 220 (0.231)
400 x 400 (0.144)
250 x 400 (0.089)
400 x 220 (0.079)
100 x 400 (0.037)
400 x 100 (0.026)
100 x 220 (0.021)
100 x 100 (0.009)
B
C/W
C/A
5850 x 400 (2.201)
B/S
C/W
C/A
2200 x 400 (0.815)
B/S
C/W
C/A
1000 x 400 (0.366)
B/S
C/A
400 x 400 (0.144)
S
C/A
250 x 400 (0.089)
S
C/A
100 x 400 (0.037)
0 100 200 300 400
q" (kW/m 2 )
Width x Depth (Area)
(µm) x (µm) (mm 2 )
5850 x 400 (2.201)
2200 x 400 (0.815)
1000 x 400 (0.366)
C/W
400 x 400 (0.144)
250 x 400 (0.089)
100 x 400 (0.037)
B
C/W
5850 x 400 (2.201)
B
B/S
C/W
2200 x 400 (0.815)
B
C/W
1000 x 400 (0.366)
B
C/W
400 x 400 (0.144)
B
B/S
C/A
250 x 400 (0.089)
S
C/A
100 x 400 (0.037)
B: Bubbly S: Slug C: Churn W: Wispy-annular A: Annular
B/S: Alternating bubbly/slug flow
C/W: Alternating churn/wispy-annular flow
C/A: Alternating churn/annular flow
: Single-phase flow
Fig. 3. Summary of boiling flow patterns in the microchannel test pieces; the microchannel dimensions are presented as width
(μm) × depth (μm) with a single-channel cross-sectional area (mm 2 ) in parentheses [14].
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Bubbly flow
Churn/wispy-annular flow
q” = 62.1 kW/m 2
Churn/annular flow
(a) q” = 193.4 kW/m 2 (b) q” = 264.1 kW/m 2
(c)
Fig. 4. Flow patterns in the 2200 μm × 400 μm microchannels
at the three different heat fluxes; G = 630 kg/m 2 s [11].
Another geometric parameter which affects flow boiling is
surface topography. Jones et al. [13] investigated the effects
of surface roughness on flow regimes and heat transfer
characteristics in pool boiling of water and FC-77. Their
experiments showed that at low heat fluxes, more activation
sites were observed for roughened surfaces (roughness
average of 5.89 μm) relative to the polished surfaces
(roughness average of 0.04 μm). Also, rougher surfaces led
to smaller bubble departure diameter and higher bubble
emission frequency.
B. Microscale Phenomena and Vapor Confinement
There has been a good deal of discussion in the literature
regarding the appropriate definition of a microchannel;
however, a clear, physics-based distinction of microchannels
from conventional-sized channels has not emerged. In
general, a microchannel refers to a channel for which the
heat transfer coefficient and pressure drop deviate from the
predictions from widely accepted models for conventionalsized
channels. For single-phase flow, Liu and Garimella
[20] and Lee et al. [21] showed that channels with hydraulic
diameters as small as 244 μm (the minimum considered in
the studies) still exhibit heat transfer and pressure drop
behavior that is well-predicted by conventional models.
With boiling present in the channels, however, the flow
phenomena differ from those in macroscale channels as the
channel approaches the bubble diameter in size. In these
small channels, correlations and models developed for larger
channels no longer apply [3]. Harirchian and Garimella [14]
developed a new criterion for delineating microchannels
from macroscale channels based on the presence of vapor
confinement as explained in the following.
The experimental flow visualizations reveal that the flow
confinement depends not only on the channel size, but also
on the mass flux since the bubble diameter varies with flow
rate. The different experiments carried out for various
channel sizes and mass fluxes can be categorized into two
groups of confined and unconfined flow regardless of the
heat input, and are represented in Fig. 5 on Reynolds number
and Bond number coordinates. This plot shows that for
channels of small cross-sectional area and at low mass
fluxes, vapor confinement is observed, while for larger
microchannels and at high mass fluxes, the flow is not
confined. The solid line on this plot shows the transition
between confined and unconfined flow and is a curve fit to
the transition points, represented by
( ) 0.5
0.5 1 ⎛ g ρf
− ρ ⎞
g
2
Bo × Re = GD = 160 (7)
μ ⎜ σ ⎟
⎝ ⎠
0.5
Bo × Re, a parameter termed the convective confinement
number here, is proportional to the mass flux, G, and the
cross-sectional area, D 2 , and is inversely proportional to the
fluid surface tension. This new flow boiling transition
0.5
criterion recommends that for Bo × Re < 160 , vapor
bubbles are confined and the channel should be considered
as a microchannel. For larger convective confinement
numbers, the flow does not experience physical confinement
by the channel walls and the channel can be considered as a
conventional (macroscale) channel. It is important to note
that this transition criterion is independent of the heat flux
and is very useful in determining whether a channel behaves
as a microchannel or a conventional, macroscale channel,
regardless of the heat input, for practical applications. A
comprehensive flow regime map accounting for the heat
input which determines the specific flow patterns is
presented in section G.
In Harirchian and Garimella [14], the proposed criterion
for transition between confined and unconfined flow is
compared with available experimental observations from
other studies in the literature for water and fluorocarbon
liquids. The comparison shows that the proposed criterion is
successful in predicting the confined or unconfined nature of
the flow from a variety of studies in the literature.
The effects of the physical confinement by the channel
walls on the heat transfer coefficient and boiling curves are
discussed next.
Re
10 4 Confined Flow
Unconfined Flow
10 3
10 2
Unconfined Flow
Confined Flow
0.5
Bo × Re = 160
Bo × Re =
160
10 1
10 -2 10 -1 10 0 10 1
Bo
Fig. 5. Transition from confined flow to unconfined flow [14].
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C. Heat Transfer Coefficients and Boiling Curves
Heat transfer coefficients and boiling curves have been
studied extensively in the authors’ group and the effects of
several geometric and flow parameters on flow boiling heat
transfer have been systematically investigated [4-17, 25, 26]
as summarized in this section and the next.
Fig. 6 illustrates the effect of microchannel dimensions on
the heat transfer coefficient for a fixed mass flux of 630
kg/m 2 s [11]. In this figure, the heat transfer coefficient is
plotted versus the wall heat flux for both single-phase and
two-phase flows in all the microchannels considered. As can
be seen from this figure, the onset of boiling is associated
with an increase in the wall heat transfer coefficient.
A careful examination of this figure reveals that at this
mass flux, for microchannels with a cross-sectional area of
0.089 mm 2 and larger, the heat transfer coefficient is
independent of microchannel size. For smaller crosssectional
areas where bubble confinement was visually
observed, the heat transfer coefficient behavior is markedly
different, with the heat transfer coefficient being relatively
higher at the lower heat fluxes. As the heat flux increases,
the curves cross over, resulting in lower values of heat
transfer coefficient. The largest heat transfer coefficient is
seen in the 100 μm × 220 μm microchannels, with a crosssectional
area of 0.021 mm 2 , before partial dryout occurs.
For the 100 μm × 100 μm microchannels, the heat transfer
coefficient is relatively lower at low heat fluxes since partial
dryout occurs even at very low heat fluxes.
The larger heat transfer coefficients in the smaller
microchannels are attributed to the confinement effects
caused by bubbles occupying the whole cross-section of the
microchannels due to the small cross-sectional area relative
to the bubble diameter at departure. As discussed in sections
A and B above, flow visualizations reveal that in all of the
microchannels with cross-sectional area and mass flux
values leading to a convective confinement number less than
160, slug flow commences soon after incipience of boiling
and flow enters the churn/annular regime at relatively low
heat fluxes. Early establishment of annular flow in
microchannels of very small diameter was also reported in
other studies [22, 23]. As a result, bubble nucleation at the
walls is not the only heat transfer mechanism, and the
evaporation of the thin liquid film at the walls in the slug and
annular flows also contributes to the heat transfer.
Therefore, the value of heat transfer coefficient is larger for
these smaller microchannels at lower heat fluxes. At high
heat fluxes, a decrease in heat transfer coefficient is detected,
which is due to an early partial wall dryout in these small
channels. In microchannels with larger cross-sectional areas,
nucleate boiling is the dominant flow regime, and hence, the
heat transfer coefficient is independent of channel size.
Similar trends have been reported in the literature for the
dependence of confined pool boiling on plate spacing in
parallel-plate configurations; as the plate spacing was
reduced below the bubble departure diameter, heat transfer
was enhanced in the low heat flux region due to confinement
effects. As the spacing was decreased further, the heat
transfer coefficient increased until it reached a maximum,
after which it deteriorated with decreasing channel spacing
[24].
h(kW/m 2 K)
9
8
7
6
5
4
3
2
1
G = 630 kg/m 2 s
5850 x 400
2200 x 400
1000 x 400
700 x 400
1000 x 220
400 x 400
250 x 400
400 x 220
100 x 400
400 x 100
100 x 220
100 x 100
0
0 50 100 150 200 250 300 350
q" w
(kW/m 2 )
Fig. 6. Effect of microchannel dimensions (width µm × depth
µm) on heat transfer coefficients [11].
It is emphasized that it is neither the channel aspect ratio
nor the smallest dimension of the microchannel that is the
determining geometric dimension affecting boiling heat
transfer, but instead, the channel cross-sectional area [11].
Similar plots for three other mass fluxes are shown in [14].
These plots showed that for the channels in which
confinement is not present and nucleate boiling is dominant
up to very high heat fluxes, and for which the convective
0.5
confinement number Bo × Re is larger than 160, the heat
transfer coefficient is independent of microchannel size; all
the curves collapse on to a single curve in these cases. For
microchannel dimensions and mass fluxes which result in
0.5
Bo × Re < 160 , the heat transfer coefficients are larger
due to the contribution of thin-film evaporation to the heat
transfer mechanisms.
The effect of mass flux on heat transfer coefficient was
investigated in Harirchian and Garimella [9]. In Fig. 7, heat
transfer coefficients are plotted as a function of the wall heat
flux for different mass fluxes. The heat transfer coefficient
increases with mass flux in the single-phase region for a
fixed wall heat flux. After the onset of nucleate boiling,
however, the heat transfer coefficient becomes independent
of mass flux, and increases with heat flux. At high levels of
wall heat flux, as the contribution from convective heat
transfer begins to dominate that of nucleate boiling, the heat
transfer coefficient becomes a function of mass flux and
increases with increasing mass flux. Flow visualizations
performed for these cases show that the plots of heat transfer
coefficient diverge from each other at the heat flux where the
bubble nucleation is suppressed at the walls. Other
microchannel sizes tested yielded similar trends for the
dependence of heat transfer coefficient on mass flux. These
results regarding the dependence of heat transfer coefficient
on flow rate are also consistent with the findings of Chen
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and Garimella [15, 16].
h(kW/m 2 K)
10
9
8
7
6
5
4
3
2
1
w=400μm
d = 400 µm
250 kg/m 2 s
700 kg/m 2 s
1150 kg/m 2 s
1600 kg/m 2 s
0
0 50 100 150 200 250 300 350
q" w
(kW/m 2 )
Fig. 7. Effect of mass flux on heat transfer coefficients [9].
At high heat fluxes, a decrease in heat transfer coefficient
is detected. Flow visualizations reveal that this is attributed
to a partial wall dryout as also reported in [15].
In Harirchian and Garimella [11], boiling curves are
discussed for different channel sizes and a mass flux of 630
kg/m 2 s. It is shown that for microchannels of cross-sectional
area 0.089 mm 2 and larger, the boiling curves cluster
together beyond the onset of nucleate boiling, indicating the
dominance of nucleate boiling. As boiling starts in these
microchannels, the wall temperature shows a weak
dependence on the heat flux. This is consistent with the
dominant nucleate boiling flow regime that was observed
through the flow visualizations. As the heat flux increases,
the wall temperature becomes more dependent on the heat
flux and the boiling curves deviate for different channel sizes
as convective boiling dominates. For the microchannels with
smaller cross-sectional areas, the wall temperature increases
with increasing wall heat flux and the boiling curves do not
collapse on to those of the larger microchannels. The strong
dependence of the wall temperature on the heat flux for these
microchannels can be explained based on the flow
visualizations which reveal that thin-film evaporation and
forced convection in the thin liquid film surrounding the
vapor slug or annulus, rather than nucleate boiling, are the
main heat transfer mechanisms in the smaller channels.
Harirchian and Garimella [9] also investigated the effect
of mass flux on the boiling curves. It was shown that for
cases later determined as having a convective confinement
number of larger than 160, the boiling curves for all mass
fluxes collapse to a single curve beyond the onset of nucleate
boiling, indicating the dominance of nucleate boiling. For
the mass fluxes at which confinement occurs, the boiling
curves deviated from other curves due to an early transition
to slug flow and annular flow regimes at lower and higher
heat fluxes, respectively.
Holcomb et al. [25] investigated the influence of
microchannel size and mass flux on flow boiling of
deionized water in silicon microchannels. Their experiments
were conducted over a similar range of parameters as in the
FC-77 studies discussed thus far and similar trends for
dependence of heat transfer performance on channel
dimensions and flow rate were observed; the boiling curves
and heat transfer coefficients were found to be largely
independent of channel size and mass flux, except in the
vicinity of transition from single-phase to two-phase,
indicating the dominance of nucleate boiling for the
parameters considered.
The influence of surface roughness on flow boiling heat
transfer has also been investigated with deionized water [17].
These experiments indicated only a small influence of
surface roughness on boiling incipience and on saturated
boiling heat transfer coefficients at low heat fluxes. At
higher heat fluxes, however, a heat transfer enhancement of
20 to 35% was obtained with the rougher surfaces
(roughness average of 3.9 and 6.7 μm) relative to the smooth
surfaces (1.4 μm). The effect of surface roughness on pool
boiling heat transfer was also studied by Jones et al. [13].
They observed a continuous increase in heat transfer
coefficient with increasing surface roughness in pool boiling
of FC-77; however, experiments with water showed little
improvement in heat transfer with increasing surface
roughness except for very rough surfaces with an average
roughness of 10 μm, at which a significant increase in heat
transfer coefficient was observed. It should be noted that the
test chips considered for flow boiling studies with FC-77
have smooth surfaces.
D. Effect of Vapor Quality
It is also important to understand the variation of flow
boiling heat transfer coefficient as a function of vapor
quality. Bertsch et al. [5, 6] investigated flow boiling of
refrigerant HFC-134a in parallel copper microchannels of
dimensions 762 μm × 1905 μm as a function of local vapor
quality. A custom-designed experimental setup allowed for
the measurement of heat transfer coefficients at specific
vapor qualities spanning the entire range from subcooled
liquid to superheated vapor. The heat transfer coefficient
was found to vary significantly with vapor quality; it
increased as the vapor quality was increased from subcooled
liquid and reached a peak at a local vapor quality of 20%,
after which it dropped again sharply for further increases in
vapor quality.
In flow boiling of FC-77, the heat transfer coefficient
increases with increasing exit vapor quality [26], until the
point of partial dryout, whereupon a decrease in heat transfer
coefficient is observed. It is also noted that larger exit
qualities could be achieved in smaller microchannels,
resulting in early transition to annular flow and larger values
of heat transfer coefficient in these smaller channels.
E. Pressure Drop
The pressure drop and pumping power is now considered,
along with the influence of channel dimensions and mass
flux on these quantities.
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Δp(kPa)
80
70
60
50
40
30
20
10
G=630kg/m 2 s
5850 x 400
2200 x 400
1000 x 400
700 x 400
1000 x 220
400 x 400
250 x 400
400 x 220
100 x 400
400 x 100
100 x 220
100 x 100
0
0 50 100 150 200 250 300 350
q" w
(kW/m 2 )
Fig. 8. Effect of microchannel dimensions (width µm × depth
µm) on pressure drop [11].
The pressure drop as a function of the average wall heat
flux is shown in Fig. 8 for a wide range of microchannel
sizes. The two-phase region can be clearly distinguished
from the single-phase region by the sharp change in the
slope of the curves. In the single-phase region, the pressure
drop slightly decreases with increasing heat flux due to the
reduction in liquid viscosity as the liquid temperature
increases. In the two-phase region, the pressure drop is
strongly dependent on heat flux and increases rapidly and
almost linearly with increasing heat flux due to the
acceleration of vapor, as also reported in other studies [15,
27, 28].
In both the single-phase and two-phase regions, the
pressure drop increases with decreasing microchannel crosssectional
area at a given heat flux. In the two-phase region,
the slope of the line also increases as the channel area
decreases, with much larger pressure drops for smaller
channels at higher heat fluxes.
It is also seen that for the microchannels with similar
cross-sectional areas and different aspect ratios (e.g., 250 μm
× 400 μm and 400 μm × 220 μm microchannels), the
pressure drops are similar in value.
For a fixed channel size, in both single-phase and twophase
regions, the pressure drop increases with increasing
mass flux [9], which agrees with the results of Pate et al.
[28]. Chen and Garimella [15], however, found that the
pressure drop was independent of mass flux in the two-phase
region. They attributed this observation to the balance
between the frictional pressure drop and accelerational
pressure drop under the moderate inlet subcooling
considered in their tests, which is in contrast to the very
modest subcooling used in the current work.
The pumping power required to manage a given base heat
flux with different microchannel sizes is also of practical
interest. In the single-phase region the pumping power
required is almost constant, independent of the heat flux,
while in the two-phase region, the pumping power increases
rapidly with heat flux [9]. The experiments reveal that for
microchannels without vapor confinement, the pumping
power is not a strong function of microchannel width. As
the microchannel size decreases below the confinement
threshold, however, the pumping power increases with
decreasing channel size. Therefore, for a given pumping
power, more heat can be removed from the heat source with
larger microchannels.
F. Heat Transfer Predictions
A large number of correlations have been proposed in the
literature for predicting heat transfer coefficients for pool
boiling and flow boiling in tubes and channels. Of the many
predictive correlations for boiling heat transfer, those of
Cooper [29] and Gorenflo [30] are widely used for
predicting nucleate pool boiling heat transfer coefficients.
Flow boiling features simultaneous contributions from
nucleate boiling and forced convection. There have been
two main approaches to model flow boiling: a superposition
approach and an extrapolation approach [7]. Chen [31]
suggested the superposition approach, in which the nucleate
boiling and forced convection components are linearly
summed with the introduction of a suppression factor for the
nucleate boiling term and an enhancement factor for the
forced convection term. Shah [32] proposed an
extrapolation-type correlation which used a boiling number
and a convective number. Following these two early studies,
many modifications have been proposed to both approaches
to obtain better agreement with different sets of experimental
data for conventional channels [33, 34]. In the last decade,
experiments have focused on mini- and microchannels and
the forced convection component in flow boiling correlations
has been adapted for laminar or developing flows [30, 35,
36, 37] to better represent the flow conditions in mini- and
microchannels.
The experimental results obtained by the authors were
compared to predictions for the same conditions from ten
correlations from the literature in Harirchian and Garimella
[9]. Both pool-boiling and flow-boiling correlations for both
macro and microchannels were considered. For most of the
0.5
experimental cases (with Bo × Re > 160 ), the nucleate
pool boiling correlation of Cooper [29] predicted the
experimental results very well, with a mean absolute error of
7.2%. For smaller microchannels at lower mass fluxes
(which would exhibit vapor confinement according to the
criterion proposed here), the error associated with the
prediction of heat transfer coefficient using this correlation
was larger at 15%; however, this pool-boiling correlation
still predicted the experimental results better than other
empirical correlations developed specifically for
microchannel flow boiling.
In a recent review [3], 25 published heat transfer
correlations were examined to identify the applicability of
correlations developed both for conventional-sized and
microscale channels in predicting the heat transfer
coefficient in small channels; 1847 experimental data points
were compiled from ten different published studies which
reported flow boiling heat transfer measurements in channels
of hydraulic diameter less than 2 mm. Again, the pool
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boiling correlation of Cooper [29] showed the lowest
deviation between experimental measurements and
predictions, indicating the dominance of the nucleate boiling
heat transfer regime. This study [3] showed that none of the
correlations developed for flow boiling offered an improved
prediction over pool boiling correlations. In particular,
correlations developed especially for minichannels and
microchannels show essentially no improvement over those
developed earlier for conventional-sized channels.
Summaries of all the correlations assessed, along with their
conditions and ranges of applicability, are tabulated in [3]
and [9].
Based on the clear need that was identified for flow
boiling correlations that are applicable over a wide range of
parameters, Betsch et al. [4] developed a composite
correlation that included both nucleate boiling and
convective heat transfer terms while taking into account for
the confinement in small channels. They compared their
proposed correlation to 3899 data points from 14 studies in
the literature for 12 fluids with a wide range of hydraulic
diameters, confinement effects, mass fluxes, heat fluxes, and
vapor qualities, and achieved a mean absolute error of less
that 30%.
Subsequent experimental heat transfer measurements with
water [25] obtained under the same conditions and
parameters as those discussed here for FC-77 also compared
well with predictions from the correlations of Cooper [29]
and Bertsch et al. [4], with mean absolute errors of 23.2%
and 24.6%, respectively.
This discussion of the literature and the comparison of
experimental results from a wide range of experimental
studies with existing empirical correlations point to a clear
need for physics-based models for flow boiling heat transfer
in microchannels. Such models should account for
microscale effects and must be validated against a large
experimental database featuring a wide range of parameters
and operating conditions. Flow regime maps must first be
developed to determine the flow patterns present for any
given set of parameters. Physics-based models for each of
the flow regimes can then be developed and validated using
such a database.
G. Flow Regime Maps
Flow regime maps are commonly used to determine the
flow patterns that exist under different operating conditions,
as well as the conditions for flow pattern transitions. Such
maps are essential to the development of flow regime-based
models for the prediction of the heat transfer rate and
pressure drop in flow boiling. The coordinates used to plot
these flow regime maps can be superficial phase velocities or
derived parameters containing these velocities; however, the
effects of important parameters such as channel size are not
represented in a number of these maps. Early flow regime
maps for horizontal and vertical two-phase flow in channels
with diameters of a few centimeters were developed by
Baker [38], Hewitt and Roberts [39], and Taitel and Dukler
[40]. In recent years, a few studies [41, 42, 43] have
developed flow regime maps for boiling in microchannels
and have shown that flow regime maps developed for larger
tubes are inapplicable for predicting flow regime transitions
in microchannels. Flow regime maps for adiabatic twophase
flow in microchannels were also proposed through
high-speed visualizations [44, 45, 46]; however, it has been
shown [43] that adiabatic flow regime maps are not suitable
for the prediction of microscale boiling. Despite the
inability of macroscale boiling maps or adiabatic two-phase
flow regime maps to predict the boiling flow patterns in
microchannels, a review of the literature shows a dearth of
investigations into flow regime maps specifically targeted at
microchannels undergoing flow boiling that are applicable to
a wide range of microchannel dimensions and experimental
conditions.
In recent work by the authors [12], two different types of
flow regime maps for microchannel flow boiling of FC-77
have been developed based on the experimentally visualized
flow patterns. Twelve different flow regime maps were
plotted for the six channel dimensions considered using
coordinates of mass flux and vapor quality, and alternatively,
of liquid superficial velocity and vapor superficial velocity.
Both types of flow regime maps depend on channel
dimensions; hence, for each channel dimension, a separate
flow regime map is required to capture the flow regime
transitions accurately. The effects of channel width on the
flow regime transition were discussed as well. The flow
regime maps developed in [12] were also compared to flow
transitions from other studies in the literature for adiabatic
two-phase flow and for boiling in macro- and microchannels.
It was concluded that only the flow regime maps
developed for microscale flow boiling in comparable
channel sizes could reasonably match the observed flow
transitions.
Due to dependence of flow regimes (and regime maps) on
channel dimensions, it is important to include the effects of
channel size in the flow regime maps. To address this need,
a comprehensive flow regime map has recently been
developed [14] and is discussed here.
Bl.Re
10 -2 Churn/Confined Annular
Confined Slug
Bubbly
Churn/Wispy-Annular
Churn/Annular
10 0
-3
Bl = 0.017 Bo ×
Re
10 -4
0.5
Bo × Re = 160
10 1 10 2 10 3 10 4
(Bo) 0.5 .Re
0.4 -0.3
( )
Fig. 9. Comprehensive flow regime map, including regime
transitions, for FC-77 [14].
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7-9 October 2009, Leuven, Belgium
Fig. 9 shows the comprehensive flow regime map
developed based on the experimental results and flow
visualizations performed with FC-77. The abscissa in this
plot is the newly defined convective confinement number,
0.5
Bo × Re, which is proportional to the dimensional
quantity, G × D 2 . The ordinate, Bl× Re, is a
q w
× D . Plotting all
nondimensional form of the heat flux, ′′
the ~390 experimental data points obtained in [11] and [12]
for flow boiling of FC-77 in 12 different microchannel test
pieces with channel cross-sectional area in the range of
0.009-2.201 mm 2 , four mass fluxes in the range of 225-1420
kg/m 2 s, and heat fluxes in the range of 25 to 380 kW/m 2 on
Bl× Re versus
Bo
0.5
× Re logarithmic axes leads to a
comprehensive flow regime map with four distinct regions
of confined slug flow, churn/confined annular flow, bubbly
flow, and churn/annular/wispy-annular flow.
0.5
The vertical transition line is given by Bo × Re = 160 ,
which represents the transition to confined flow. The other
transition line is a curve fit to the points of transition from
bubbly or slug flow to alternating churn/annular or
churn/wispy-annular flow, and is given by
0.5
( ) 0.7
Bl× Re= 0.017 Bo × Re
(8)
which can be rearranged to give
0.4 0.3
Bl = 0.017( Bo × Re −
)
(9)
0.5
This flow regime map shows that for Bo × Re < 160
vapor confinement is observed in both slug and
0.5
churn/annular flow regimes while for Bo × Re > 160 , the
flow is not confined. For low heat fluxes with
Bl < 0.017
0.4 0.3
Bo × Re − , flow patterns of slug (if
( )
0.5
0.5
Bo × Re < 160 ) or bubbly (if Bo × Re > 160 ) flow
exist in the microchannels. At higher heat fluxes with
0.4 0.3
Bl > 0.017( Bo × Re −
), vapor bubbles coalesce,
resulting in a continuous vapor core in the alternating
churn/annular or churn/wispy annular flow regimes.
In [14], experimental data from a range of other studies in
the literature were plotted on this comprehensive flow
regime map. The map developed was clearly able to
represent the flow regimes found in the literature for water
and fluorocarbon liquids.
IV. SUMMARY
Extensive experimental work has been conducted with
microchannel test pieces encompassing a wide range of
channel dimensions over a broad range of operating
conditions to systematically determine the effects of
important geometric and flow parameters on pressure drop,
heat transfer, and flow regimes associated with microscale
flow boiling. Local heat transfer measurements obtained
with simultaneous, detailed flow visualizations have led to a
better understanding of boiling phenomena in microchannels
and the governing heat transfer mechanisms. The extensive
microscale boiling experiments and analyses have resulted in
a comprehensive understanding of boiling, with some of the
significant findings listed below:
• A large database of boiling flow pattern visualizations is
obtained for a wide range of channel dimensions and
flow parameters, leading to a good understanding of
microscale flow regimes.
• A clear knowledge of the effects of microchannel
geometry on flow boiling is obtained; the cross-sectional
area of the microchannels is found to play a determining
role in boiling mechanisms and heat transfer.
• Vapor confinement and emergence of microscale effects
are shown to depend not only on channel size and fluid
properties, but also on the flow rate. Based on the
experimental results, a new transition criterion is
developed which predicts the conditions under which
microscale confinement effects are exhibited in flow
boiling.
• For conditions under which flow confinement does not
occur, the heat transfer and boiling curves are
independent of, and pressure drop and pumping power
have only minor sensitivity to, channel size and flow
rate.
• Effects of surface roughness on pool boiling and flow
boiling have been studied for water and dielectric
liquids; surface roughness is found to have a minor
effect on heat transfer coefficient at low heat fluxes
while it leads to a 20-35% enhancement at higher heat
flux region in flow boiling of water.
• Empirical correlations are developed for prediction of
heat transfer coefficient based on a large dataset of
approximately 3900 data points from several studies in
the literature.
• A comprehensive flow regime map for flow boiling of
FC-77 is developed, along with quantitative regimetransition
criteria, based on approximately 390 data
points encompassing a wide range of microchannel
dimensions, mass fluxes, and heat fluxes. This
comprehensive flow map is expected to facilitate the
development of flow regime-based models for the
prediction of boiling heat transfer coefficients.
ACKNOWLEDGEMENTS
Financial support from the State of Indiana 21st Century
Research and Technology Fund and from the Cooling
Technologies Research Center, an NSF Industry/University
Cooperative Research Center at Purdue University, is
gratefully acknowledged.
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©EDA Publishing/THERMINIC 2009 110
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Exposition, IMECE2007 11 (A), 437-446.
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[29] Cooper, M. G., 1984. Heat Flow Rates in Saturated
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[32] Shah, M. M., 1977. General Correlation for Heat
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[34] Tran, T. N., Wambsganss, M. W., and France, D. M.,
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[36] Zhang, W., Hibiki, T., and Mishima, K., 2004.
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[37] Peters, J. V. S. and Kandlikar, S. G., 2007. Further
Evaluation of a Flow Boiling Correlation for Microchannels
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[38] Baker, O., 1954. Design of Pipe Lines for Simultaneous
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[39] Hewitt, G. F. and Robert, D. N., 1969. Studies of Two-
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[40] Taitel, Y. and Dukler, A. E. 1976. A Model for
Predicting Flow Regime Transitions in Horizontal and Near
Horizontal Gas-liquid Flow. AIChE Journal 22, 47-55.
[41] Hetsroni, G., Mosyak, A., Segal, Z., and Pogrebnyak,
E., 2003. Two-Phase Flow Patterns in Parallel
Microchannels. International Journal of Multiphase Flow 29,
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[42] Huo, X., Chen, L., Tian, Y.S., and Karayiannis, T. G.,
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[44] Chung, P. M.-Y. and Kawaji, M., 2004. The Effect of
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Thermophysical Engineering 9, 165-182.
[46] Field, B. and Hrnjak, P., 2007. Visualization of Two-
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Congress and Exposition, IMECE2007-43471, Seattle, WA.
©EDA Publishing/THERMINIC 2009 112
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7-9 October 2009, Leuven, Belgium
Impact of Moisture Absorption on Warpage of Large
BGA packages during a lead-free reflow process
B. Vandevelde 1 , R. Deweerdt 2 , F. Duflos 2 , M. Gonzalez 1 ,
D. Vanderstraeten 3 , Eddy Blansaer 3 , Guy Brizar 3 , Renaud Gillon 3
1 IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
2 Groep T, Leuven, Belgium
3 On Semi, Oudenaarde, Belgium
Abstract- During a solder reflow process, IC components
deform under a rather excessive temperature loading. A too
high warpage at temperatures above solder melting, can cause
either that the joints in the corner are not soldered to the PCB
pads, or that the solder joints are shorted due to compressing of
the corner joints.
In this work, the warpage of a 35by35 mm 2 large PBGA
package has been measured during a temperature profile which
is similar to a lead-free soldering process. It was found that the
warpage becomes very high when the applied temperature is
above the glass transition temperature of the overmould
material. At that moment, there exists a very large CTE
mismatch between the overmould and the BT laminate.
The warpage measurements have been successfully verified
by Finite Element Modelling adapting the right material
properties. This proves that modeling can be used as an
estimator of warpage for packages.
Also the impact of initial moisture uptake has been
experimentally investigated and it was shown that it has a
dominant effect on its warpage behaviour.
Keywords – Warpage, PBGA, topography measurements
thermo-mechanical stress, solder reflow, FEM simulation
I. INTRODUCTION
Packages consist of different materials, having a different
coefficient of thermal expansion (CTE). Under a temperature
change, the different mechanical expansions cause internally
acting forces and this finally results in internal mechanical
stresses and an out-of-plane deformation of the package.
In this paper, the solder reflow process is considered as
temperature profile, where components are subjected to
rather excessive temperature loading. As a consequence,
excessive warpage can cause shorts due to compression of
neighbouring balls in the corner area under global warpage,
as indicated in the schematic drawing in Fig. 1. For other
package concepts, e.g. QFN’s, the opposite can happen that
packages are warped upwards in the corner, resulting in open
connections, or even worse, so-called frozen connections
only made by mechanical contact, giving no failure at room
temperature but starts to disconnect again at higher
temperatures.
20°C
250°C
(SAC reflow
temperature)
Fig. 1: Schematic drawing of shorts at the corner due to excessive
warpage (happens during liquid soldering)
This phenomenon of interconnection problems due to
excessive warpage during solder reflow, is strengthen by the
change to lead-free, which requires typically 30°C higher
melting temperature, and also by moisture absorption, as will
be shown in this paper. As warpage is typically proportional
to the square of the package size, large packages are also
more vulnerable. Also the overmould properties play a very
important role: both its Tg (glass transition point) and the
amount of moisture it will absorb, will determine the
warpage profile..
II. EXPERIMENTAL WORK
A. Sample description
For this study, a PBGA package encapsulated by an
overmould material has been selected. The size of the
package is 35 by 35 mm 2 , the die size is 13 by 13 mm 2 .
Fig. 2: Picture and schematic drawing of the PBGA 35x35 mm 2
package
©EDA Publishing/THERMINIC 2009 113
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7-9 October 2009, Leuven, Belgium
Regarding the study of the impact of moisture absorption
taken up by the package, the same package type has been Temperature (°C)
measured with four different pre-conditions, as shown and
250
described in Table 1. For each condition, 5 samples have
been measured.
200
TABLE I
Overview of Sample Conditions for warpage measurements
Condition
Code
Reference structure with uncontrolled
“REF”
history, as they were lying for more than 1
year lying on the shelf (probably, they took
up some moisture)
Reference structure dried for 3 days at
“DRY”
120°C
Reference structure humidified in a
“WET1”
humidity chamber, for 168h at 85°C and
85% humidity.
Reference structure humidified in a pressure “WET2”
cooker chamber, for 18h at 120°C and 100%
humidity.
B. Measurement setup
The measurements were done with the Topography and
Deformation Measurement (TDM) System from Insidix
[4,5]. The out-of-plane measurements use the principle of
the projection moiré technique to measure the topography as
the difference between a reference horizontal surface and the
measured surface. This reference surface is a calibration tool
that is perfectly flat and homogeneous white and is measured
beforehand. The outcome of one measurement is the out-ofplane
profile, as shown in Fig. 3.
The warpage is then defined as the difference in out-ofplane
displacement between the center and the corner
(not the difference in z-height!).
150
100
50
0
0 5 10 15 20 25
Time (min)
Fig. 4: Temperature profile applied to PBGA sample for the
topography measurement
C. Measurement result for a “DRY” sample
The first experiment presented in this paper is the warpage
profile measurement for a dry sample. Fig. 6 shows the outof-plane
profile for this package at 22°C and at 227°C (=
maximum reflow temperature). At 22°C, the warpage is
almost zero, while at 227°C, the warpage is visibly high.
Z-height (µm)
1800
1600
1400
1200
1000
800
600
400
200
0
227°C
22°C
0 10 20 30 40 50
Distance from one corner (mm)
Fig. 5: Out-of-plane profile (topography) measured by INSIDIX
equipment (along the diagonal).
Fig. 3: Topography measurement of the PBGA package
B. Temperature loading profile
A typical reflow temperature profile has been applied for
this package, with a maximum of 227°C. The heating is
performed by IR camera’s, while the temperature is
measured using a thermo-couple touching the BGA sample.
The warpage has been measured at different temperatures,
both in heating and cooling. The result for this sample is
shown in Fig. 6. At room temperature, there is a small
warpage of about 50 µm (corners bending downwards). This
warpage is almost constant up to 170°C. Above this
temperature, the warpage substantially change and the corner
start to bend downwards. This reason is that the glass
transition for the overmould is reached, resulting in a high
CTE mismatch between the overmould and the BT (while
they are quite well matched below 170°C). As a
consequence, the corners start to warp downwardsn and this
becomes very high at maximum temperature (450µm).
©EDA Publishing/THERMINIC 2009 114
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7-9 October 2009, Leuven, Belgium
Warpage (µm)
500
400
300
200
Heating curve
Cooling curve
(+) Warpage
Z-height (µm)
1600
1400
1200
1000
800
Sample @22°C after 168h
in 85%-85°C chambre
Dried sample @22°C
100
600
0
0 50 100 150 200 250
-100
(-) Warpage
Temperature (°C)
Fig. 6: Warpage measured by INSIDIX equipment during a reflow
process (red curve is when temperature goes up, the blue curve refers
to the cooling down of the package).
The warpage during cooling is very similar to the warpage
measured during heating. This indicates that the deformation
is fully reversible and elastic (no plasticity neither creep
effects).
D. Measurement result for a “REF” sample
Warpage (µm)
Although the “REF” samples haven’t been stored in dry
package and could take up moisture for more than one year,
it has a very similar warpage vs. temperature behaviour as
the dried one. With the “REF one, there is a delta warpage of
about 50µm after the solder reflow, which could indicate that
the absorbed moisture cause additional pressure during the
heating up, resulting in a small permanent deformation after
the reflow process.
500
400
300
200
100
0
0 50 100 150 200 250
-100
-200
(-) Warpage
"DRY"
(+) Warpage
"REF"
Temperature (°C)
Fig. 7: Warpage measured by INSIDIX equipment during a reflow
process for “DRY” and “REF” sample (see description in Table 1).
E. IMPACT of moisture on warpage profile
Even after being in the moisture oven (168h in 85%
humidity, 85°C), the initial warpage is already much
different from the dried and reference sample, as shown in
Fig. 8. The additional bowing is caused the expansion of the
overmould due to the moisture uptake.
400
200
0
0 10 20 30 40 50
Distance from one corner (mm)
Fig. 8: Z-profile of a dried sample and a sample which has been in the
moisture oven for 168h (both at room temperature)
It was also found that there is no difference between
“WET1” and “WET2” conditioned samples. Probably, in
both conditions, the mould materials are fully saturated by
moisture.
The warpage measurement trend in a reflow profile for the
“WET” samples are shown in Fig. 9 and compared with the
“DRY” and “REF” samples (the graphs show the average of
5 measured samples).
The “wet” sample is a clrealy different story. Due to the
moisture uptake, the component has already an initial
warpage of 200µm, which is caused by expansion of the
overmould due to moisture uptake. After the reflow process,
the warpage does not come back on the same curve, but will
return to warpage , even with different sign. This is caused
by a strong plastic deformation, strengthen by the vapour
pressure.
Warpage (µm)
REF DRY WET
700
600
500
400
300
200
100
0
-100 0 50 100 150 200 250
-200
(-) Warpage
-300
Temperature (°C)
(+) Warpage
Fig. 9: Measured warpage during a reflow temperature profile (from
room temperature to 230°C and back)
©EDA Publishing/THERMINIC 2009 115
ISBN: 978-2-35500-010-2

III. FINITE ELEMENT MODELLING OF BGA WARPAGE
A finite element model is built for this package (Fig. 11).
Non-linear material properties are applied both for the
overmould and BT laminate, in order to be able to include
the T g for both materials.
7-9 October 2009, Leuven, Belgium
Out-of-plane deformation (µm)
350
300
250
200
150
100
Experiment
FEM - no expanding
strain
FEM - 0.05% strain
FEM - 0.1% strain
FEM - 0.15% strain
50
0
0 5 10 15 20 25
Distance to center over the diagonal (mm)
Fig. 12: Simulations of warpage due to moisture uptake (vs.
experiment)
IV. CONCLUSIONS
Warpage has been successfully measured using the
INSIDIX equipment. For the particular PBGA package, a
significant impact of moisture uptake and the Tg of the
overmould has been found. It was shown that FEM can be
used to estimate warpage of large package under reflow
conditions.
Fig. 10: 3D Finite Element Model simulating the thermally induced
mechanical deformation during a reflow process
Warpage (µm)
500
400
300
200
100
0
0 50 100 150 200 250
-100
-200
DRY
Temperature (°C)
FEM
Fig. 11: Comparison between FEM analysis and measurement of the
warpage of the 35by35 mm 2 PBGA
The authors would like to thank Veerle Simons at IMEC
for her support in the measurements. This work has been
also supported by the ELIAS project, funded by the IWT and
MEDEA+.
REFERENCES
[1] IPC/JEDEC Joint Industry Standard, J-STD-020C,
“Moisture/Reflow Sensitivity Classification for Plastic Integrated Circuit
Surface Mount Devices”, July 2004.
[2] B.T. Vaccaro, I.I. Shook, E. Thomas,J.J. Gilbert, C. Horvath, A.
Dairo and G.J. Libricz, PBGA package warpage and impact on traditional
MSL classification for Pb-free assembly, SMTA International conference,
2005.
[3] R.L. Shook, J.J Gilbert, E. Thomas, B.T. Vaccaro, A. Dairo, C.
Horvath, G.J. Libricz, D. L. Crouthamel, and D.L. Gerlach, “Impact of
Ingressed Moisture and High Temperature Warpage Behavior on the Robust
Assembly Capability for Large Body PBGAs”, Proceedings of Electronic
Components and Technology Conference, 2003, pp. 1823-1828.
[4] Richard, I.; Fayolle, R.; Smyth, A.; Lecomte, J.-C, New
experimental approach for failure prediction in electronics: topography and
deformation measurement complemented with acoustic microscopy,
EuroSimE 2005, pp 305 – 310.
[5] M. Hertl, D. Weidmann, and J-C. Lecomte, Process Optimization:
Influence of Heating and Cooling Rate on the Thermo-Mechanical Stress
Generated in Components, EMPC2009, June 15th – 18th 2009, Rimini,
Italy
.
With the same simulation model, the out-of-plane
deformation over the diagonal of the package was calculated
for different expansion strains. Comparing the results with
the experiment, it was found that the moisture uptake by the
overmould causes an expansion of about 0.12%.
©EDA Publishing/THERMINIC 2009 116
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Evaluation of Materials for High Temperature IC
Packaging
Robert Klieber, Renee Lerch
Fraunhofer Institute for Microelectronic Circuits and Systems
Finkenstr. 61
D47057 Duisburg, Germany
Abstract- Fast decrease of device dimensions, rapid growth of
the number of elements per integrated circuit device (IC) and
the increasing amount of interconnections between the chip and
the substrate lead to a more complex design and production of
the ICs and to higher demands towards packaging technology
as well. This is especially true in the field of high temperature
electronics with operating temperatures of up to 250°C. We
present an evaluation of materials for both the adhesive and the
encapsulant for packaging of high temperature ICs for this
temperature range. Among the available materials only glassbased
formulations could withstand extended periods of heat
and substantial numbers of temperature cycles. In addition,
samples of high temperature CMOS ICs (capacitive pressure
sensors and EEPROMs) have been successfully assembled
using these materials.
I. INTRODUCTION
Fast decrease of device dimensions, rapid growth of the
number of elements per integrated circuit device (IC) and the
increasing amount of interconnections between the chip and
the substrate lead to a more complex design and production
of the ICs and to higher demands towards packaging
technology as well. The rise in power density due to the
increasing miniaturization of the device size and the interest
of industry for ICs working in high temperature
environments lead to high operation temperatures of the
integrated circuit devices and the encapsulation. Within
automotive, aerospace, space, geothermal wells and nuclear
power applications high temperature devices operate
between 150°C to 600°C. These integrated circuits have to
be protected from mechanical damage, moisture and
radiation, which could negatively affect the device
performance, reliability or lifetime. The proper choice of the
encapsulant therefore enhances the reliability of the IC
devices and improves their mechanical and physical
properties for these high temperatures. While adhesives and
encapsulants are a common technique for die-bonding and
encapsulation of ICs for applications up to 150°C, these
materials fail in high temperature applications for
temperatures higher than 150°C.
II. EXPERIMENTAL SETUP
To monitor the performance of the die attach and the
encapsulant materials, samples have been prepared and
tested in a 250°C ambient and in thermal cycling
experiments, cycling the samples between room temperature
(25°C) and 250°C. At designated time stamps and cycle
amounts tests have been performed at room temperature.
To evaluate the performance of the die adhesives chips of
the size 3 mm 2 were bonded into standard DIL24 ceramic
housings with a gold surface and onto ceramic plates. The
thickness of the adhesives layers was between 20 and 40 μm
after curing. The required die shear force to take off the
chips was measured in accordance with MIL-STD-883
Method 2019 by applying a force parallel to the surface of
the substrate as shown in Fig. 1.
In order to evaluate the performance of the various
encapsulants a die of the size 2x1.5x1 mm 3 was bonded with
the best die adhesive material into a DIL24 ceramic housing.
25 μm thick aluminum bond wires have been used to create
electrical connections between each DIL24 housing pad and
the surface of the die having a gold layer on the top surface.
The electrical connection between the pads of the housing
and the die were tested by a measurement of the resistance
between two contacts of the DIL24 housing as shown in
Fig. 2 after the encapsulation. Also visual inspections of the
encapsulants have been made to reveal defects like flaws and
fractures.
Fig. 1. Schematic drawing of the shear force measurement for the die
attachment test
Fig. 2. Schematic drawing of the conduction measurement for the
encapsulation test
This work was partially funded by the government of the state of North
Rhine-Westphalia as part of the "Hochtemperaturelektronik" program.
©EDA Publishing/THERMINIC 2009 117
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7-9 October 2009, Leuven, Belgium
III. DIE ATTACHMENT
To attach integrated circuits to a substrate die adhesives
are used in packaging technology. Several products were
chosen from a worldwide survey of potential candidates for
die attach, which mainly differ in their coefficient of thermal
expansion (CTE) and their hardness. Table 1 summarizes
the CTEs of important materials. A CTE mismatch between
the die attach material and the die can cause shear loading
and lead to high mechanical stress in the silicon chip, which
can result in a breakage of large dies at high temperatures.
This can be partly compensated by a high flexibility, - a low
hardness of the die attach material. Besides common used
products like epoxies, polyimides (medial hardness, medial
CTE mismatch) also glasses (high hardness, low CTE
mismatch) have been tested.
Fig. 3a and 3b show the results of the storage test at 250°C
for different time stamps. The shear force measurement
system was limited to maximum measurable shear force of
49 Newton. Each point in the plots represents an average of
three shear force measurements. The shear force required to
take off the chip decreases for increasing storage time for the
polyimides and the epoxy and after three hundred hours the
required shear force was below 19 N for all die attach
materials except the glasses. According to the MIL standard
a shear force of 19 N is the minimum allowed shear force the
chip has to resist for this chip size. After 1000 hours the
adhesion strength of the polyimide and the epoxy nearly
vanishes. The glasses showed no detectable loss of their
adhesion strength up to 6000 hours.
The cycling tests show similar results (Fig. 4a and 4b).
The shear force required to take off the chip decreases fast
for the epoxy and nearly vanishes after 500 cycles. The
polyimides are below MIL standard after 1500 cycles. In
contrast the glasses show no detectable decrease of their
adhesion strength up to 2500 cycles, indicating that die
attach material with a CTE in the range of the substrate and a
high shore hardness can be used for die attachment.
Therefore these glasses were also used for high temperature
die attachment for the subsequent encapsulant tests.
Fig. 3b. Maximum required shear force to lift off the chip as a function of
storage time at 250°C for glasses.
Fig. 4a. Maximum required shear force to lift off the chip as a function of
the number of cycles between 25°C and 250°C for polyimides and an
epoxy. The dashed line indicates the minimum allowed shear force for a 3
mm 2 die.
Fig. 3a. Maximum required shear force to lift off the chip as a function of
the storage time at 250°C for polyimides and an epoxy. The dashed line
indicates the minimum allowed shear force for a 3 mm 2 die.
Fig. 4b. Maximum required shear force to lift off the chip as a function of
the number of cycles between 25°C and 250°C for glasses.
©EDA Publishing/THERMINIC 2009 118
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TABLE I
COEFFICIENTS OF THERMAL EXPANSION AND SHORE HARDNESS
Material CTE [ppm/K] Shore Hardness
Silicon 2 - 4
Al203 (Substrate) 6,50
Glass 4 - 7 >90
Epoxy 19 - 65 60-80
Polyimide 20 - 120 60-80
Silicone 200 - 300 25-30
7-9 October 2009, Leuven, Belgium
electrical connections after more than 14.000 temperature
cycles and 14.000 hours of storage.
IV. ENCAPSULATION / GLOB-TOP
After die attach and wire bonding the integrated circuits
have to be protected from mechanical damage, moisture and
radiation by an encapsulant. Thirteen different encapsulants
have been tested. Besides epoxies and polyimides, silicones
and glasses have been tested. The materials were selected
according to the following considerations:
• The low hardness of the silicones can compensate
different thermal expansion coefficients between the
substrate, the die and the bond wires (low hardness,
high CTE mismatch to the die).
• As the thermal expansion coefficient of the polyimides
and the epoxies is in the range of the bond wires, the
expansion of the encapsulant should not tear up the
bond wires (medial hardness, medial CTE mismatch to
the die).
• As glasses are very hard and their thermal expansion
coefficient is lower than the CTE of the bond wire,
glasses will force the bond wire to their expansion
(high hardness, low CTE mismatch to the die).
Fig. 5a and 5b show the results of the storage test at 250°C
for different time stamps. Most of the encapsulated chips
show a steadily increasing amount of defect wire bonds with
the passing of storage time. All encapsulants made of
silicone, epoxy or polyimide show first wire bond breakage
after 25 to 50 storage hours. In contrast to the epoxy
encapsulants, which destroyed all bond wires after 1000 h,
not all bond wires had been destroyed in systems
encapsulated with polyimide or silicone. Due to their elastic
behavior silicones sometimes reconnect broken bond wires.
The surface of the silicones do not show any change,
whereas flaws and fractures can be found on the surface of
the polyimide and epoxy encapsulants. Only the glasses
show no wire bond breakage for up to 14.000 h.
Fig. 6a and 6b demonstrates the results of the cycle test
between room-temperature and 250°C. Most of the
encapsulants destroy all bond wire connections after 50
cycles. After 500 temperature cycles all bond wires
encapsulated with silicone or epoxy and also one of the
polyimides have been destroyed completely. The second
polyimide encapsulant shows a low amount of destroyed
bond wires (

7-9 October 2009, Leuven, Belgium
VI. APPLICATIONS
Several EEPROM ICs and capacitive pressure sensor
chips have been bonded into a standard DIL housing with
the glass die bond material. Afterwards the chips have been
contacted by standard aluminum bond wires (25 µm) and
encapsulated with glass. Fig. 8 shows an EEPROM chip for
high-temperature operation, encapsulated by glass in order to
protect the chip and the bond wire connections from
mechanical damage, moisture and radiation. In current tests
the chips have shown no failure during storage tests at 250°C
for 800 h.
Fig. 6b. Percentage of wire bond breakage as a function of the number of
cycles between 25°C and 250°C for epoxies and glasses.
V. SENSITIVITY OF TRANSISTOR PARAMETERS TO
PACKAGING
While silicone-, polyimide- and epoxy-based
encapsulation processes employ rather moderate curing
temperatures of about 200°C or less, process temperatures
for glass encapsulants exceed 450°C for up to 1 hours. As
temperatures in this range are also present in the last stages
of CMOS wafer fabrication, there was concern that they
could adversely affect CMOS device parameters.
Therefore test structures were prepared and fabricated in
the IMS H10 High-Temperature SOI process to measure the
effects of the glass encapsulation process on diode and
transistor parameters. The parameters were measured as
soon as possible after each assembly step, and during
subsequent storage at 250°C. Fig. 7 shows the typical
variation of the measured parameters: although there is a
peak deviation associated with the high-temperature filling
step, it is nearly gone after an 816 hour bake. At all times
the parameters were well within the range allowed for
process variations. Except for the time immediately after the
filling step, the deviations are on the same order as those for
standard encapsulation methods.
Fig. 8: Picture of the high-temperature EEPROM IC, before and after
encapsulation.
VII. CONCLUSION
The reliability and performance of different die attach
materials and encapsulants have been examined in storage
and cycling experiments. Although specified to work at
temperatures at least up to 250°C, many encapsulants and
die-bonding materials fail in these tests after short periods or
a small number of temperature cycles.
Glass-based die attach and encapsulation materials
showed the best performance of the tested materials. With
this approach standard aluminum wire bonding techniques
can be used with glass as die attach and packaging material
for high temperature electronic assembly of integrated
circuits. These die attach materials showed the best
performance and no detectable loss in shear strength up to
5000 cycles and for more than 5000 storage hours. It was
also the best packaging material, which showed no bond
wire failure up to 14.000 temperature cycles and storage
hours.
With this glass-based approach SOI chips have been
assembled with glass as die attach and packaging material,
with promising results so far.
Fig. 7. Typical variation of a device parameter (NMOS threshold voltage)
over the stages of glass-based assembly and subsequent high-temperature
bake (square). For comparison, the variation during standard epoxy based
assembly is shown (circle)
©EDA Publishing/THERMINIC 2009 120
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7-9 October 2009, Leuven, Belgium
Electro-thermal modeling of different LEP-thickness
white OLEDs
Ernő Kollár, Gusztáv Hantos @eet.bme.hu
Department of Electron Devices, Budapest University of Technology and Economics
H-1111 Budapest, Goldmann tér 3., Hungary
Abstract-In our project the final purpose is to develop a costeffective
roll-to-roll technology of fabricating large-surface,
high-output OLED (Organic Light Emitting Diode) devices for
intelligent lighting applications.
The electrical and optical characteristics of multi-layered
OLEDs depend on the thickness of the layers. To reach the
highest efficiency in an application is needed to optimize the
each layers. In this paper we have measured the I-V
characteristics of the different LEP (Light Emitting Polimer)
thickness white OLEDs. We have examined in 50C wide
temperature range. We have created an electro-thermal model,
which describe the temperature and LEP thickness dependence
of the forward bias.
The results work as the feedback for the fabrication process
and the OLED planning to our project partner.
I. INTRODUCTION
In our research project called Fast2Light [1] the overall
objective is to develop a novel, cost-effective, high-output,
roll-to-roll, large-surface deposition process for fabricating
light-emitting polymer-OLED [2] foils for intelligent
lighting applications. The tested OLED device was realized
on thin glass substrate, which was provided by a project
partner.
On the DUTs there are more different size OLEDs and
OLED groups. This design allows of the examination of the
pixel size devices and more cm 2 size ones in same
technology. The groups allows of gaining certain
information about fabrication process. In this paper we deal
with the about 10 mm 2 lighting surface OLEDs as is shown
by arrows on Fig.1.
Fig. 2. The layer structure of the OLED device under test
The project partner has provided 60, 80 and 100 nm LEP
thickness white OLED samples. Our purpose is to create a
model which helps to choose the optimal LEP thickness
adapted to the needs. Such a need can be, for example, the
principle of operation at a standard power supply.
The layer structure of an OLED device is shown in Fig. 2.
[3]
II.
MEASUREMENT ARRANGEMENT
We have studied the forward bias above 4 V. The end
points of I-V characteristics depend strongly on the
temperature and the LEP thickness, that’s why this point is
between 5 V and 9 V. For comparison we have used the
22 mA/cm 2 value as suggested limit by provider.
The measurement was carried out on GPIB and RS232
controlled conventional laboratory equipment. The OLEDs
were attached to a cold-plate of variable constant
temperature. We have applied an analogue measuring point
changer for the full automatic measuring. The I-V
characteristics were measured between 5 °C and 50 °C. The
power supply step was 0.01 V in every second. We
measured all of three OLEDs on every sample.
Fig. 1. The 10 mm 2 lighting surface OLEDs on the device under test
III.
FORWARD BIAS
Drawing the forward I-V values in log-log scale results
straight lines in two ranges. We have considered the forward
current of the device as the sum of two power functions [4].
The parameters of the power functions are: m for the
exponent and b for the factor. The LOW and HIGH
subscripts show in which forward bias range the power
function is effective (1).
©EDA Publishing/THERMINIC 2009 121
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I
OLED
7-9 October 2009, Leuven, Belgium
b U
b U
(1)
LOW
mLOW m HIGH
HIGH
Current [A]
1,E-02
1,E-03
1,E-04
1,E-05
LEP = 60 nm
y = 2,144E-08x 6,729E+00
R 2 = 1,000E+00
LEP = 80 nm
y = 2,350E-08x 6,194E+00
R 2 = 1,000E+00
LEP = 100 nm
y = 2,464E-08x 5,287E+00
R 2 = 9,999E-01
1 10
Voltage [V]
Fig. 3. The effect of the LEP thickness; forward I-V characteristics at 25 o C
and the fitted power functions
In our case above 4 V the HIGH range power function is
effective. For simplicity we deal with the only HIGH range
and we leave HIGH subscript. We use it as follow (2):
I
OLED
mT
, d
T
, d bT
, d U
LEP
LEP
where T is the temperature and d LEP is the thickness of the
LEP.
We have fixed the glass substrate to a cold-plate. In the
case of power dissipation the temperature of the LEP could
be a bit higher than that of the cold-plate. In other words, the
tail of the I-V curve may show a certain degree of selfheating.
We measured this temperature error by an infrared
camera. This error is less than 1 C at the tail of curve.
IV.
LEP
PARAMETER FITTING
We carried out the fitting of power function, and we have
tried to determinate m and b parameters on each curve. Fig. 4
shows the changing of m parameter. If the LEP thickness or
the temperature increases, then the exponent decreases.
Similarly we plotted the b parameter (Fig. 5). If the LEP
thickness or the temperature increases, then the factor
increases.
m as exponent
8
7
6
5
4
3
2
1
0
0 20 40 60 80 100
Thickness of LEP [nm]
Temperature
Fig. 4. The effect of the LEP thickness and temperature for the m exponent
(Temperature range is between 5 and 50 C)
(2)
b as factor
10
8
6
4
2
*1E-8
Temperature
0
0 20 40 60 80 100
Thickness of LEP [nm]
5. The effect of the LEP thickness and temperature for the b factor
(Temperature range is between 5 and 50 C)
These parameters vs. LEP thickness able to change
polynomial way. The temperature dependence of m and b
act as polynomial. That’s why we suggest matrixes for m and
b.
V. MODEL
The problem is similar in the case of two parameters. We
use x instead of m and b (3):
x
T
d
LEP
T X d
LEP
, (3)
where T is a temperature row matrix, d LEP is the thickness
column matrix, X is the parameter matrix. If the temperature
and the LEP thickness is known, then the x(T , d LEP ) matrix
product will give only a number.
As follows we show matrixes when the polynomials are
quadratic (4):
0
x
11
x12
x13
d
LEP
0 1 2
1
x T,
d
LEP
T T T
x21
x22
x23
d
LEP (4)
2
x
31
x32
x33
d
LEP
Where the upper index means power exponent.
We determined the M and B matrixes (5), these are:
5.76E
5
M
3.30E
6
3.21E
8
2.21E
3
B
2.49E
5
6.98E
8
VI.
2.26E
2 6.68E
0
2.05E
4 4.03E
2
,
2.64E
8
5.05E
4
3.42E
2 3.14E
1
3.59E
4 4.26E
3
4.73E
6 3.28E
5
CONCLUSION
We have constructed the electro-thermal model for
different LEP-thickness white OLEDs. The model uses
power function to approximate the forward bias above 4 V.
(5)
©EDA Publishing/THERMINIC 2009 122
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7-9 October 2009, Leuven, Belgium
The parameters of the power function are matrixes. Knowing
the value of the LEP thickness, the temperature and the
parameter matrixes than I-V characteristic of WOLED can
be determined easy way.
The knowing M and B matrixes helps the design of
electrical property of the WOLED.
ACKNOWLEDGMENT
This work has been supported by the ICT-
2007.3.2/216641 Fast2Light Project of the Framework 7
program of the EU.
[1] http://www.fast2light.org/
REFERENCES
[2] Klaus Müllen, Ullrich Scherf “Organic Light Emitting Devices,”
Synthesis, Properties and Applications, 2006, Wiley
[3] Milan Stolka, Organic Light Emitting Diodes (OLEDs) for General
Illumination Update 2002, AN OIDA TECHNOLOGY
ROADMAP, August, 2002, http://www.OIDA.org
[4] Ernő Kollár, Imre Zólomy, Andrés Poppe, “Electro-thermal
modeling of large-surface OLED” Symposium on Design, Test,
Integration and Packaging of MEMS/MOEMS (DTIP'2009). Rome,
Italy, pp 239-242, 1-3, April 2009
KEY WORDS
OLED, electro-thermal, LEP, modeling
BRIEF BIOGRAPHY
Ernő Kollár received his M.Sc. degree in electrical
engineering at the Budapest University of Technology and
Economics, Hungary, in 2001. His field of research includes
thermal testing, compact modeling, heat-flux measuring, as
well as thermal conductivity measuring by evaluation of
structure function. His latest research interests are electrothermal
model generation, power LEDs, OLEDs.
©EDA Publishing/THERMINIC 2009 123
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7-9 October 2009, Leuven, Belgium
Electro-Thermal Simulation of Multi-channel Power Devices on PCB with SPICE
Torsten Hauck*, Wim Teulings*, Evgenii Rudnyi **
* Freescale Semiconductor Inc.
** CADFEM GmbH
Abstract
In this paper we will present an efficient method allowing thermal
modeling, simulation and design of a multichannel power semiconductor
device on Printed Circuit Board (PCB). The method starts
with a finite element discretization of the heat equation at the
continuous field level. In a second step, the resulting large set of
differential equations is approximated by a reduced-order model by
means of the well-known Arnoldi algorithm. Next, the reduced-order
thermal model is represented by an electrical equivalent network
allowing SPICE simulation. The new approach allows to
simultaneously evaluate the temperature of the semiconductor
junctions and of the PCB track underneath the semiconductor device.
The entire model generation procedure was automated and is now
available for use with the software tool ANSYS/Workbench. This
allows the development of a set of thermal SPICE models of different
devices and different PCB design layouts. We will demonstrate the
method by performing an electro-thermal analysis of Freescale's new
eXtreme Switch devices. These devices typically consist of 4 highside
MOSFET switches with associated drive-, diagnostic- and
protection circuitry integrated in a Power Quad Flat No-Lead (PQFN)
package. A typical application demonstrates the validity of the
followed approach.
1. Introduction
It is important to keep the maximum junction temperature of a
MOSFET power die within the authorized range. Otherwise
overheating will impact the reliability and cause device failure. On the
other hand, the PCB surface, used as a heat-sink, must be minimized
to save costs. Hence, the ability to predict the thermal performances of
a particular design layout is a crucial element when a cost-optimized
and reliable system must be designed. In this paper we will present an
efficient modeling method for design and simulation of multichannel
power semiconductor devices in a realistic applicative environment.
We start with a full scale finite element model (see Section 2), and
then introduce the model order reduction (see Section 3). That allows
us to reduce the complexity of the original final element model and
makes it possible to go to system level simulation. In section 4 we will
briefly describe the transformation of the state space representation of
the dynamic heat equation into an electrical equivalent circuit,
represented by a SPICE netlist. The entire system and the simulation
of selected application cases, including electro-thermal coupling, will
be shown Section 5.
2. Finite Element Modeling
The most accurate thermal model is generally achieved by means
of finite element modeling, but this approach is much too time
consuming to allow an interactive design optimization. Here the
original geometry is replicated in the model where additionally the
thermal properties of each part are specified. Figure 1 shows pictures
of the eXtreme Switch device. The PQFN package is a Multi Chip
Module (MCM), which carries one control- and one power die
interconnected through copper leadframe, heavy gauge aluminum and
gold bonding wires. During module assembly, the PQFN pads are
soldered onto a printed circuit board. Figure 2 shows the associated
solid model as introduced in a CAD-tool.
Drain pad
Fig.1: Semiconductor package, left: bottom view with exposed
pads, right: top view of a de-capsulated package
Fig. 2: Solid model of the assembly of package and PCB
During finite element meshing the solid model is divided into a
finite number of elements (see Fig 3). The partial differential equation
for transient heat conduction reads
∂T
∇k∇T
+ Q − ρ C = 0 . (1)
∂t
With the finite element discretization Eq (1) is replaced by the
following set of ordinary differential equations:
H
⋅ T & + K ⋅ T = F ⋅ p J , (2)
where the matrices H, K and F represent heat capacity, thermal
conductivity and load distribution. Vectors T an p J represent all nodal
temperatures and the heat dissipation power in the particular transistor
junctions.
heavy gauge
wires
Leadframe
control
chip
power
chip
PCB
Fig. 3: Finite element mesh (mold compound removed).
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Eq (2) could be directly converted to a Kirchhoff-network then defines the inputs and outputs and generates the files necessary to
consisting of thermal resistors and capacitors [1]. But, by the nature of run MOR for ANSYS. This way the process to generate the reduced
the finite element method, the dimension of such a model would model is fully automated. The time to generate the reduced model is
become rather high. For example, the number of degrees of freedom comparable with that of the static solution and for the model in Fig. 3
of the model in Fig 2 would approach 300 000 and is out of reach for it is about 100 s.
effective representation by an electrical equivalent circuit.
A comparison of one transient junction temperature response in
There are many ways to develop a compact dynamic thermal ANSYS (dimension of the model about 300000) with the reduced
model [2][3] but in our view model order reduction [4][5][6] model of the dimension 30 is shown in Fig. 7.
possesses the most attractive properties.
3. Model Order Reduction
The model order reduction is based on the assumption that the
movement of a high-dimensional state-vector can be well approximated
by a small dimensional subspace (Fig 5 left). Provided this
subspace is known the original system can be projected on it (see Fig
5). The main question is how to find the low dimensional subspace
that possesses good approximating properties. It happens that a very
good choice is a Krylov subspace [4]-[6].
The model reduction theory is based on the approximation of the
transfer function of the original dynamic system. It has been proved
that in the case of Krylov subspaces, the reduced system matches
moments of the original system for the given expansion point. In other
words, if we expand the transfer function around the expansion point,
first coefficients will be exactly the same, as for the original system.
Mathematically speaking this approach belongs to the Padé
approximation and this also explains good approximating properties of
the reduced models obtained through modern model reduction
methods. The description of the algorithm can be found in [4]-[6].
Fig. 6: The structure of MOR for ANSYS.
Fig. 5: Model reduction as a projection of the high dimensional
system onto the low-dimensional subspace.
The reduced low order system is given as a state space
representation of the transient heat equation with the state vector of
generalized variables z, the evolution matrices E and A, the input
matrix B and the output matrix C. The vector T J comprises all
transistor junction temperatures. The required number of state
variables is determined by an error estimation procedure [7].
E⋅ z&
= A ⋅ z + B ⋅ p
T = C ⋅ z
J
J
The software tool “MOR for ANSYS” [5] has been used to
perform model reduction on the finite element models developed in
ANSYS Workbench. The block scheme of the software is shown in
Fig 6.
The software reads system matrices from ANSYS FULL files,
runs the order reduction algorithm and then writes the reduced
matrices out. The process of generating FULL files in ANSYS
Workbench is automated through scripting. The developer defines
named selections to describe the power dissipations in the model. The
script (so called a command snippet) takes them as arguments and
(3)
Fig. 7: The relative difference between the thermal response in
ANSYS and that produced by the reduced mode.
4. Model Representation by an electrical equivalent circuit
The state space format is very common for data flow analysis
tools. In system analysis it is handled as a dynamic block representing
the heat transfer of a semiconductor package. Alternatively, the
reduced system can be rewritten as an equivalent RC network model
[6]. To achieve this, we diagonalize the state space matrices. The
transformation matrix U is normalized such that the evaluation matrix
E becomes an identity matrix. Each evolution equation can be
replaced by one RC-cell with a unit capacitance and a resistance being
the reciprocal of the associated diagonal element of evolution matrix:
T
U ⋅ E⋅
U = I
U
1
( )
1 , , L ,
T 1
A ⋅ U = −Diag
R1
R2
R n
⋅ (4)
Input and output matrices B and C of the state space are now
represented by controlled voltage_ and current sources. Fig. 8 shows a
simplified thermal network model. The number of junction nodes was
reduced to two for simplicity of the schematics.
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The transformation of the reduced matrices in the form of Eq (4)
to a SPICE netlist was automated through a Python script. The script
reads the reduced matrices in the Matrix Market format produced by
the MOR for ANSYS and then exports thus obtained subcircuit netlist.
As opposed to common CAUER- or FOSTER- type RC- circuits,
the physical interpretation of the state space representation of the heat
transfer presented here is not as obvious. The thermal state of the
structure is completely described by the state vector. The evolution of
each state variable in time is determined by the RC-cells. Heat sources
(power dissipation) and resulting temperature readings are mapped by
the controlled current and voltage sources. The state space model and
its representation as SPICE netlist automatically includes all thermal
cross couplings and multidimensional heat flow directions. This is a
clear advantage for multichannel devices, such as Freescale’s dual or
quad analog power switches, where several power MOSFETs can be
controlled independently by the user.
drain pad
Fig. 9: an analog power IC (eXtreme Switch)
Two separate SPICE netlists were generated for the heat transfer
in device and PCB. They are defined as simple sub circuits. The
system model is easily done by importing the thermal subcircuits and
the final assembly of thermal and electrical circuits. This can also be
done with a schematics editor. The output node of the thermal device
model is connected to the input node of the thermal PCB model (ref.
Fig. 11). This approach allows to connect the PCB model of any other
PCB layout to the same switching device just by replacing the
associated SPICE sub circuit.
The system simulation is demonstrated for a power module that
drives four bulb lamps with high inrush currents. All channels of the
eXtreme Switch are connected to a 12V battery. Each output is
connected to a bulb lamp.
The steady state load current level of one bulb is about 4A,
whereas the maximum inrush current goes up to about 70A. The
associated power dissipation is computed within each of the four high
side power switch models, and fed into the corresponding terminals of
the thermal device model.
Fig.8: Electrical equivalent circuit representation of thermal state
space model for multichannel devices (with exposed pad).
The voltage at the four terminals of the thermal device model
directly reflects the temperature within the particular transistor
junctions. The drain pad node between device and PCB model reflects
the average temperature of the drain terminal, which is equal to that of
the PCB land to which the drain terminal is mechanically and
electrically connected (ref. Fig. 11). Thermal cross-coupling between
the channels is implicitly considered within the thermal device model.
The ambient temperature is set to 85°C by means of a voltage source,
which is connected to the thermal PCB model (ref. Fig. 11).
5. Thermo-Electric System Simulation
The proposed model generation path and electro-thermal system
simulation are demonstrated for one of Freescale’s new High-Side
Switch devices with four independent channels. The device is
packaged in the thermally well performing PQFN (Power Quad Flat
No Lead) package. The corresponding thermal model contains two
distinct submodels: one for the 4-Channel High Side switch and one
for the associated printed circuit board (PCB). The device model
provides the independent thermal ports, each of them representing the
junction of one channel switch. Device model and PCB model share
one common node, the voltage of which represents the temperature of
the connection point between the device’s drain terminal and the
subjacent PCB land (see the drain pad in Fig. 9 and 10). The PCB
model also represents the heat convection of the system into the
ambient air.
drain pad
Fig. 10: Printed circuit board (here thermal test board 2s2p)
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thermal
PCB model
ambient
temperature
electrical
device and
bulb
models
thermal
device model
Fig. 11: SPICE circuit, with electrical equivalent circuit of the PCB and the 4 channel eXtreme switch device
Fig. 12: Temperature response for use case 1, high side switch HS2 ON
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Fig. 13: Temperature response for use case 2, high side switches HS2 and HS1 sequentially switched ON
Fig. 14: Temperature response for use case 2 with the thermally enhanced printed circuit board
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For the first use case, only the upper high side switch HS2 was
switched on for 100ms. The inrush current peak only lasts a few
milliseconds but reaches almost 70 Amps. Newt, the current
exponentially decays to the nominal current load of 4 Amps. Figure 12
shows the resulting temperature response in transistor junctions and
drain pad. It can be observed that channel HS2 (the only channel that
carries current in this example) heats up to about 127°C. The other
channels heat up to about 105°C due to cross-coupling (they do not
dissipate any power themselves). Channel HS0, in closest proximity to
HS2, heats up somewhat more than HS3 and HS1, as can be expected.
In a second use case the simulation has been repeated with an
additional inner switch HS1 being put ON 10 milliseconds later than
exterior switch HS2. It can be seen that first, the junction temperature
of HS2 starts increasing as before. Next, after having started to
decrease, it suddenly increases to a second maximum, due to crosscoupling
induced by the power dissipation occurring in the adjacent
switch HS1. The thermal cross coupling causes high side switch HS2
to heat up to 132°C. The temperature of high side switch HS1 reaches
an even higher value of up to 141°C (ref. Fig. 13).
A third simulation run is repeating use case two but on a thermally
enhanced printed circuit board lower thermal resistance). This time the
maximum temperature of switch HS2 is significantly reduced
compared to the previous simulation (ref. Fig. 14).
Freescale is able to supply SPICE models of several of its eXtreme
switch devices for different PCB layouts. The combination of the
component model with the PCB models is shown to be possible with
the SPICE schematics editor. Thanks to this approach, system design
with Freescale’s eXtreme Switch devices will become very flexible
and quick. It will enable our customers to cost-optimize their PCB
layout and module design work without having to perform long, costly
and tedious FEM simulations.
6. Summary
We presented a new procedure for thermal modeling& simulation
of SMART power ICs (High Side Switches based on MOSFET) on
Printed Circuit Boards with different layouts. Key elements were the
order reduction of finite element models, the extraction of equivalent
thermal circuit models, the assembly and simulation of electro-thermal
systems with the circuit simulator SPICE. The proposed approach has
many advantages:
• SPEED: A complete electro-thermal simulation with
SPICE circuit simulator will take some tenth’s of
seconds, whereas any finite element simulation of a
comparable system would take several hours,
• MODULARITY: Thanks to the separation of the
thermal models of the device-package and that of the
underlying PCB, the performance of several different
PCBs may be evaluated within very short time. This
allows a designer to fine-tune his design very quickly,
• FUNCTIONALITY: Coupling of electrical and thermal
field becomes straight forward. Phenomena, such as the
influence of an increased supply voltage on the power
dissipation, may be evaluated by a simple SPICE
simulation.
7-9 October 2009, Leuven, Belgium
REFERENCES
[1] J. T. Hsu, L. Vu-Quoc: “A Rational Formulation of Thermal
Circuit Models for Electro-thermal Simulation - Part I: Finite
element Method”, IEEE Transactions on Circuits and Systems,
43(9), pp. 721-732, (1996)
[2] M.N. Sabry: “Dynamic compact thermal models used for
electronic design: a review of recent progress”, Proc. IPACK03,
pp. 1–17
[3] T. Bechtold, E. B. Rudnyi and J. G. Korvink: “Dynamic Electro-
Thermal Simulations of Microsystems - A Review”, Journal of
Micromechanics and Microengineering, Institute of Physics
publications, 15 (2005), R17-R31
[4] A. Augustin, T. Hauck: “A New Approach to Boundary
Condition Independent Compact Dynamic Thermal Models”,
Twenty Third Annual IEEE Semiconductor Thermal
Measurement and Management Symposium, SEMI-THERM
2007
[5] E. B. Rudnyi and J. G. Korvink: “Model Order Reduction for
Large Scale Engineering Models Developed in ANSYS”,
Lecture Notes in Computer Science, v. 3732, pp. 349-356, 2006
[6] L. Codecasa, D. D’Amore, P. Maffezzoni: “An Arnoldi Based
Thermal Network Reduction Method for Electro-Thermal
Analysis”, IEEE Transactions on Components and Packaging
Technologies, Vol. 26, 2003, N 1, pp. 186-192
[7] T. Bechtold, E. B. Rudnyi and J. G. Korvink: “Error Indicators
for Fully Automatic Extraction of Heat-transfer Macromodels
for MEMS”, Journal of Micromechanics and Microengineering
2005, v. 15, N 3, pp. 430-440
©EDA Publishing/THERMINIC 2009 129
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Pixel-by-Pixel Calibration of a CCD Camera Based
Thermoreflectance Thermography System with
Nanometer Resolution
Mihai G. BURZO, Pavel L. KOMAROV and Peter E. RAAD*,
IEEE Conference Publishing
Southern Methodist University and TMX Scientific,
5232 Tennyson Pkwy, Bldg. 2, Plano, TX 75024, U.S.A.
Abstract- This work presents for the first time a method for
calibrating pixel-by-pixel and in-situ a CCD camera-based
thermoreflectance thermography system with nanometer
spatial resolution. Using the thermoreflectance method to
determine the temperature map of an activated device requires
two steps: first, the thermal image is acquired using a CCD
camera or laser-diode set-up and, second, the obtained thermal
image is converted to the actual temperature map by
multiplying each pixel of the thermal image with the
corresponding thermoreflectance coefficient. The critical aspect
is that even if the thermoreflectance coefficient is known, or
measured independently for each surface material, converting
the thermal image to the temperature map requires building
manually the exact corresponding map of the
thermoreflectance coefficient, which sometimes can be difficult.
In addition, the thermoreflectance coefficient is highly
dependent on the wavelength of the probing light, numerical
aperture, focus level, light uniformity, and other measurement
effects. To mitigate these issues, one must obtain the
thermoreflectance coefficient map of the same measurement
area of interest, while ensuring that the same objective lens is
used, the same focus level is maintained, and the same exact
position is kept for frame acquisition at both the low and high
temperature settings. To satisfy all of these requirements, the
position of the sample must be adjusted in 3D space with
nanometer spatial resolution.
I. INTRODUCTION
Thermal management of microelectronic microstructures
is becoming more and more crucial with the progress to
nanotechnology, increase in element power density and,
circuits being packaged closer and closer together. For large
devices and board level scales (few micrometers and above)
the technology today is at the point where anyone in need of
measuring the thermal behavior of electronic devices can
choose from an array of both scientific and commercial
measuring systems with each apparatus being best for certain
applications with most working well for most application.
Nonetheless when dealing with submicron and nanometer
scale devices the choice of thermal measurement systems is
limited with most, if not all systems, being still in R&D or
scientific/lab prototype phase at best. Among the available
technologies the thermoreflectance thermography method is
so far one of the methods that have been successfully
employed to make submicron temperature mappings [1-3]
but still has its limitations. The thermoreflectance method
has important advantages over contact and other optical
methods since it is non-contact and non-destructive, costeffective,
can produce both steady-state and transient surface
temperature, provides accurate results with excellent
submicron spatial and thermal resolutions.
Thermoreflectance microscopy is based on the physical
principle that a change in the temperature of a given surface
causes a small change in that surface reflectivity. To
measure the temperature change, ΔT, one needs to measure
the relative change in the reflectivity of the sample, ΔR/R,
and the small thermoreflectance calibration coefficient, C TR .
The thermoreflectance coefficient defines the rate of change
in the surface reflectivity as a function of the change in
surface temperature. The C TR coefficient is strongly
dependent on the material under test, the wavelength of the
probing laser [4, 5], and the composition of the sample [5].
For example, in the case of gold [6] the value of the C TR
coefficient changes from positive to zero to negative values
only by changing the wavelength from 400 to 600nm.
When using a CCD camera bases thermoreflectance
thermography system for thermal mapping of an active
electronic device, the investigator ends up with one 2D
surface map for the relative change in the reflectivity of the
sample, ΔR/R, and another 2D map of the C TR coefficient.
Combining the two maps yield the temperature map of the
device and at a quick glance it looks as a simple algebraic
task, i.e., dividing each pixel value of the ΔR/R map with the
corresponding pixel on the C TR map. Nevertheless, because
during the calibration procedure the sample itself and the
sample holder assembly is subject to thermal expansion that
causes movement in the microns to tenths of microns range,
and because the position of the sample during the
calibrations and the ΔR/R data acquisition needs to be
precisely the same, the procedure of combing the ΔR/R and
C TR maps becomes a not so trivial task.
©EDA Publishing/THERMINIC 2009 130
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7-9 October 2009, Leuven, Belgium
Fig. 1 Thermoreflectance thermography system
The goal of this work is to present a thorough procedure
for pixel-by-pixel calibration of a CCD based
thermoreflectance thermography system, i.e., successfully
acquiring and combing the ΔR/R and CTR maps to obtain
the thermal map of the activated device. A brief introduction
to the measurement methodology is presented, followed by
the new calibration system and advantages of using the
pixel-by-pixel calibration. The power of the method is
demonstrated for a microelectronic CMOS technology
device supplied by TIMA and manufactured by Austria
Microsystems. The data are checked against the results of a
verified and validated numerical simulation. The temperature
data obtained using a built in diode are also discussed.
II. METHODOLOGY
The temperature measurements using the
thermoreflectance thermography system are carried out in
several stages. First, the thermal image (change in
reflectivity) of a device is acquired. In this step the changes
in the surface reflectivity ΔR/R as a function of the changes
in temperature are measured at each point of interest with
submicron spatial resolution. Second, the calibration map is
obtained using the procedure that will be described in the
next paragraph. In this step, the thermoreflectance
coefficient, C TR , is determined at each point on the surface of
the DUT. Finally, in the third step, the resulting C TR and
ΔR/R maps are combined to obtain the surface temperature
map of the DUT. Details about each step are provided next.
The schematic of the TRTG is shown in Fig. 1. The
system is capable of acquiring temperature fields with a
512×512 point frame resolution, at 10 to 30 frames per
second, and with up to 0.2 µm spatial resolution. In the first
stage (mapping) the DUT is activated (pulse modulated),
then the change in the reflectance ΔR/R of the DUT is
captured as a change in the intensity of the reflected light on
each element (pixel) of the CCD camera and the captured
image is acquired and processed using the NI Labview on
a PC. In the second stage (calibration), the reflectivity map
(intensity of the reflected light) of the device is acquired at a
low temperature (T L ) as I L and then at a high temperature
(T H ) as I H . The thermoreflectance coefficient is then
computed for each pixel as,
C TR = [(I H – I L ) / I L ] / (T H –T L ) (1)
Finally the temperature map of each pixel is computed as,
ΔT = (ΔR / R) / C TR (2)
For the pixel-by-pixel calibration method to work
properly, it is essential that both the focus and the horizontal
position of the sample be maintained during the entire
process of acquiring the three sets of images needed for the
final temperature map: (i) thermal image, (ii) low
temperature image (calibration), and (iii) high temperature
image (calibration). The thermal expansion present during
the calibration stage of the measurement causes not only z-
axis (out of focus) movement but also horizontal movement
of the sample.
One way of controlling the z-axis movement is to reduce
the movement of the top surface of the sample by
constructing a heating stage/sample holder system where the
thermal expansion is directed away from the top area of the
device, such as the one presented by Vairac et al. at
Therminic 2005 [7]. However, since the system is a passive
system there are still going to be uncontrolled differences in
the elevation of the sample due to thermal expansion. Vairac
et al. reported a 50 nm/K movement due to the thermal
expansion while using an innovative way of controlling the
thermal expansion. For the typical values of temperature
difference, ΔT, of 30-50K generally used for the
thermoreflectance calibration process, thermal expansion
©EDA Publishing/THERMINIC 2009 131
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7-9 October 2009, Leuven, Belgium
results in 1.5 to 2.5 microns of movement of the top surface
of the sample. However, our sensitivity analysis
measurements show that the movement of the sample needs
to be limited to within a few tenths of nanometers for the
entire range of ΔT during the overall measurement process.
For the typical ΔT values of between 30 and 50K, this
translates to a movement of a few nanometers per K. The
authors believe that this level of movement control can only
be achieved by an active control system which must contain
nanometer level movement capabilities such as in high-end
piezo stages. The advantage of using an XYZ piezo stage is
that it allows the system to compensate for any movement in
the horizontal plane as well. It turns out that the movement
in the horizontal plane has to be controlled with deep subpixel
resolution (for 100X, the pixel size is 210 nm), which
translates to resolutions less than 100 nm with 10 nm or
better preferred.
In order to achieve the necessary level of thermal and
positioning control, a special module was constructed,
shown as a simplified schematic in Fig. 1. The heating stage
contains a thermoelectric element that heats up and cools
down the DUT; several temperature sensors – thermistors,
for control and overheating protection; a heat sink for
removal of the heat produced by the thermoelectric element;
a highly precise piezoelectric XYZ translation stage with
built-in thermally compensated position measurement;
vacuum lines, etc. Both the cooling and heating cycles were
significantly sped-up by the use of an intelligent PID
(Proportional-Integral-Derivative) control scheme to obtain
the smallest possible heating/cooling cycle times. A
Proportion-Integral scheme was also used to control the 3D
movement of the piezo-stage.
II.
RESULTS
A. Calibration Approaches
As mentioned above, in order to obtain the actual
temperature of the device the change in the reflectivity,
ΔR/R, needs to be divided by the thermoreflectance
coefficient. When only one surface material is involved and
only its temperature map is required this is a trivial algebraic
procedure. However, when investigating complex
microelectronic devices, that is rarely the case and typically
several materials need to be calibrated and factored in for the
final temperature map. To make matters even more
complicated, the thermoreflectance coefficient turns out to
be highly dependent not only on the material type but also on
the wavelength of the probing light (as depicted in Fig. 2)
and event the numerical aperture of the objective lenses,
focus level, light uniformity, and other measurement effects.
The C TR dependence on the wavelength of the light can be
utilized to the users’ advantage by building the system with a
variable wavelength light source and tuning the wavelength
to an optimal wavelength value that will offer the maximum
C TR value for a specific material. To exemplify, the
thermoreflectance coefficient of the polysilicon region of the
device shown in the top part of Fig. 3, which is embedded in
a transparent layer composed of several microns of field
oxide and passivation layers, was measured at various
wavelengths of the illumination light and the obtained data
Fig. 2 Thermoreflectance coefficient of oxide covered polysilicon
and gold versus the wavelength of probing light
are plotted in Fig. 2. The thermoreflectance coefficient of
Au is also plotted in Fig. 2. Since the value of the
thermoreflectance coefficient is close to zero at 500 nm for
both materials, obviously tuning the wavelength to a value in
the vicinity of this value will produce either no results at all
or extremely poor results. However, if one tunes the light
wavelength to a value of 485 nm for gold or either 605 nm or
640 nm for polysilicon, the C TR value becomes optimal and
thus the thermal map would have the highest accuracy.
In obtaining the final temperature map, i.e., while
combining the change in the reflectivity, ΔR/R, with the
thermoreflectance coefficient, C TR , the user has three
calibration approaches:
i) Whole-area calibration: If only one material is
considered, the ΔT map is obtained by dividing the ΔR/R
value of each pixel with the (fixed) C TR value of the
measured material.
ii) Zone-by-zone calibration: When multiple materials
are considered, a 2D map of the zones of different materials
can be built manually with the thermoreflectance coefficient
being determined separately for each zone. The temperature
map is obtained by combining the ΔR/R map with the final
C TR map.
iii) Pixel-by-pixel calibration: In the case of complex
devices using either one of the previous approaches could be
cumbersome and thus the pixel-by-pixel approach might be
more feasible. In this approach the both the calibration and
the change in the reflectivity data is obtained for each pixel
and the temperature map is obtained by combining the CTR
value with the ΔR/R value of the corresponding pixel on the
ΔR/R map.
The pixel-by-pixel calibration method is clearly preferred
to the other mentioned methods due to its automated nature
and being applicable to deal with any level of device
complexity. However there are instances for which there is
no single wavelength that will offer good C TR values for all
the measured materials and thus the zone-by-zone approach
©EDA Publishing/THERMINIC 2009 132
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7-9 October 2009, Leuven, Belgium
Fig. 4 Thermoreflectance thermography results for a polysilicon
resistor: left – calibration map, C TR x 10 -4 (1/K) at 460 nm
wavelength of probing light; right – contours
of temperature change, ΔT, °C
Fig. 3 Thermoreflectance thermography results for a polysilicon
microresistor: top – image of the DUT (light area is C-shaped poly
resistor; bottom – 2D map of the relative change in reflectivity,
ΔR/R × 10 4 , induced by the change in temperature ΔT, at 460nm
wavelength of probing light
could be more appropriate. In Fig. 2, the maximum value of
the C TR is obtained at 485 nm for gold and 640 nm for
polysilicon. However, in the case of the device containing
gold and oxide covered polysilicon, as evident from Fig. 2,
there is a large spectrum of wavelengths that will offer very
good C TR values for both materials, one of such wavelengths
being 485 nm. It is also worth mentioning that if one desires
to obtain the absolute best measurement uncertainties the
better way to proceed is to use the zone-by-zone calibration
and measure and calibrate twice at 485 nm (for best Au
region results) and 640 nm (for best polysilicon results) and
then combine the results to obtain the temperature change for
the device under test.
B. Temperature Results for a Representative Device
The temperature map of a polysilicon microresistor,
shown in the top part of Fig. 3, was measured and calibrated
and the results are presented here. The temperature was
probed through a layer of both field oxide and passivation
layer with a probing light wavelength of 460 nm. The value
of 460 nm was chosen because it produces good results for
all of the probed regions of the device.
The device was pulse modulated and a differential scheme
was used to obtain the map of relative change in reflectivity
of the device, ΔR/R. The ΔR/R results are presented on the
bottom part of Fig. 3. The electrical power applied to the
device was 250 mW, and 1,000 frames were averaged at a
mean frame rate of 10 frames/sec. As evident from Fig. 3
the value of the C TR coefficient is negative for the poly
region and positive for the rest of the materials. In other
words the device temperature increase caused by the Joule
heating produces a decrease in the reflectivity of the poly
region and an increase in reflectivity for the rest of the
regions.
Next, the calibration map of the device was obtained by
measuring the change in the reflectivity of the device at the
low temperature (T L = 30°C) and at the high temperature (T H
= 50°C) and then the C TR coefficient was computed using (1)
and the results are presented on the left side of Fig. 4. As
expected based on the results shown in Fig. 3 the
thermoreflectance coefficient of the poly is negative (-1.15 ×
10 -4 K -1 ) while its value is positive for the region containing
the diode leads with a value of 1.46 × 10 -4 K -1 .
Finally, the temperature map is obtained based on (2)
using the ΔR/R map (shown in the bottom side of Fig. 3) and
the thermoreflectance coefficient (shown in the left side of
Fig. 4) and the temperature change results are shown in the
right side of Fig. 4. The results indicate that the corners of
the poly-resistor are slightly cooler than the rest of the poly.
That is probably caused not only by the way that the device
cools but also the path that the current takes through the
resistor. The data shown in Fig. 4 also shows that the area
found at the center of the device, occupied by the diode,
appears to be much cooler than the microresistor area. More
on this aspect will be presented in the next section.
©EDA Publishing/THERMINIC 2009 133
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Fig. 5 Computed absolute temperature contours, T (°C), at the
surface level of the polysilicon resistor for P = 250 mW
activation power. Maximum computed temperature is 69.8°C
(the reference temperature was 20 °C and the shown area is a
54 by 54 μm square portion of the domain)
C. Validation of temperature results: numerical simulation
results
The experimental results obtained here were validated
using the authors’ ultra-fast self-adaptive numerical
simulation engine [8,9] A model was built based on the
device design data from Austria Microsystems and computed
using our solver with the results presented in Fig. 5, for an
activation power of 250 mW. The power was considered to
be uniform and covers the entire area of the polysilicon
resistor. The temperature presented in Fig. 5 is the absolute
temperature in °C; thus, to obtain the temperature change,
the reference temperature of 20°C should be subtracted from
this value. The computed maximum temperature difference
of 69.8°C agrees well, within 5%, with the experimentally
measured temperature plotted in Fig. 4.
D. Validation of temperature results: built-in diode results
In addition to comparing the experimental results to the
results of the numerical simulation, the results are also
Fig. 6 Temperature measured using the built-in diode versus
applied electrical power to the polysilicon resistor.
7-9 October 2009, Leuven, Belgium
checked against temperature readings obtained from an
embedded temperature sensor. A diode was used to measure
the temperature which is located in the center region of the
C-shaped microresistor.
First, the diode was calibrated using our thermoelectric
element based stage by measuring the change in the voltage
value with the change in the base temperature while the
current was kept constant at 1 μA. It was found that the
voltage decreases linearly with the temperature at a rate of
2.55 mV/°C for the range of temperature considered here.
After calibrating the diode, the polysilicon resistor was
activated at various power levels and the voltage of the diode
was recorded while again keeping the diode current constant
at 1 μA. The obtained data is plotted in Fig. 6 and shows
that the diode voltage is linearly proportional to the applied
microresistor power. For the 250 mW of applied power, the
diode reads a temperature gradient of 23.5°C which grossly
underestimates the computed 69.8°C maximum temperature
obtained for the polysilicon resistor. Nevertheless, by
investigating both the experimental results shown in Fig. 4
and the numerical results presented in Fig. 5 one might find
out that indeed the temperature at the center location of the
poly resistor is expected to be much lower than the
maximum temperature observed on the surface of the
resistor itself. Therefore, we must conclude that the
embedded diode sensor may not be as useful as initially
thought at determining the average temperature of the poly
resistor.
III. CONCLUSIONS
This work presented for the first time a successful method
for calibrating pixel-by-pixel and in-situ a CCD camerabased
thermoreflectance thermography system with
nanometer spatial resolution. This article described the
measurement system and methodology used and presents
relevant results. Using the thermoreflectance method to
determine the temperature map of an activated device
requires two steps: first, the thermal image is acquired using
a CCD camera and, second, the obtained thermal image is
converted to the actual temperature map by multiplying each
pixel of the thermal image with the corresponding
thermoreflectance coefficient. The critical aspect is that even
if the thermoreflectance coefficient is known, or measured
independently for each material present on the surface of the
sample, converting the thermal image to the temperature
map requires building manually the exact corresponding map
of the thermoreflectance coefficient, which in the case of
complex microelectronic devices might be difficult. In
addition, it turns out that the thermoreflectance coefficient is
highly dependent on the wavelength of the probing light,
numerical aperture, focus level, light uniformity, and other
measurement effects. To mitigate these issues, one must
obtain the thermoreflectance coefficient map of the same
measurement area of interest, while ensuring that the same
objective lens is used, the same focus level is maintained,
and the same exact position is kept for frame acquisition at
both the low and high temperature settings. To satisfy all of
these requirements, the position of the sample must be
adjusted in 3D space with nanometer spatial resolution.
©EDA Publishing/THERMINIC 2009 134
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A representative device was measured and the temperature
contours were presented. A computational tool as well as an
embedded diode was used to validate the results. While the
results of the numerical simulation validate the experimental
results, the diode readings were significantly off. After a
brief numerical investigation it was found that indeed the
location and construction of the diode sensor were not ideal,
and thus the embedded device could not be used in this case
to successfully validate the experimental data.
REFERENCES
[1] W. Claeys, D. Dilhaire, V. Quintard, J.P. Dom, and Y. Danto,
“Thermoreflectance Optical Test Probe for the Measurement of
Current-Induced Temperature Changes in Microelectronic
Components,” Reliability Engineering International, Vol. 9, pp.
303-308, 1993.
[2] Z. Bian, J. Christofferson, A. Shakouri, and P. Kozodoy, “High-
Power Operation of Electroabsorption Modulators”, Applied
Physics Letters - Vol. 83, No.17, pp. 3605-3607, 2003.
[3] P. L. Komarov, M. G. Burzo, and P. E. Raad, “A Thermoreflectance
Thermography System for Measuring the Transient Surface
Temperature Field of Activated Electronic Device,” Proceedings to
the 22nd Semiconductor Thermal Measurement, Modeling, and
Management Symposium (SEMITHERM), Dallas, Texas, March
14-16, 2006.
7-9 October 2009, Leuven, Belgium
[4] M. G. Burzo, P. L. Komarov, and P. E. Raad, “Thermal Transport
Properties of Gold-Covered Thin-Film Silicon Dioxide”, IEEE
Transactions on Components and Packaging Technologies, Vol.
26(1), pp. 80-88, 2003.
[5] G. L. Eesley, “Surface Raman Ellipsometry,” J. of Quantum
Electronics, Vol. 17, No. 7, p. 1285, 1981.
[6] P. E. Raad, P. L. Komarov, and M. G. Burzo, ”Thermal
characterization of embedded electronic features by an integrated
system of CCD thermography and self-adaptive numerical
modeling,” Microelectronics Journal, Vol. 39, Issue 7, pp. 1008-
1015, 2008.
[7] P. Vairac, B. Cretin, B., M. Genix, B. Charlot, S. Dilhaire, S.
Gomès, G. Tessier, N. Trannoy, and S. Volz, , “Ultra-local
temperature mapping with an intrinsic thermocouple,” 11th
International Workshop on Thermal Investigations of ICs and
Systems (THERMINIC), Belgirate, Lake Maggiore, Italy, 27 - 30
September 2005
[8] P. E. Raad, J. S. Wilson, and D. C. Price, “System and Method for
Predicting the Behavior of a Component,” U.S. Patent No.
6,064,810 (2000), Korean Patent No. 0501053 (2005), Japanese
Patent No. 3,841,833 (2006).
[9] J. S. Wilson and P. E. Raad, “A Transient Self-Adaptive Technique
for Modeling Thermal Problems with Large Variations in Physical
Scales,” International Journal of Heat and Mass Transfer, Vol. 47,
pp. 3707-3720, 2004.
©EDA Publishing/THERMINIC 2009 135
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7-9 October 2009, Leuven, Belgium
Practical Study of Temperature Distribution
in a Thermal Test Integrated Circuit
M. Janicki, M. Szermer, S. Klab, Z. Kulesza, A. Napieralski
Department of Microelectronics and Computer Science, Technical University of Lodz
Wolczanska 221/223, 90-924 Lodz, Poland
Abstract-This paper presents measurements and simulations
of a test integrated circuit. The circuit contains a matrix of heat
sources and a set of temperature sensors, what renders possible
measurement of circuit temperature in real cooling conditions
inside a closed package. The measurements are validated for
different patterns of power dissipation and cooling conditions
with numerical simulations. Based on the presented results, the
influence of circuit topology on temperature distribution and its
impact on the possibility of heat source temperature estimation
are discussed.
I. INTRODUCTION
Due to high power densities dissipated in state-of-the-art
integrated circuits, there appeared the need for continuous
monitoring of circuit temperature. Because of significant
temperature gradients occurring in such circuits, it is not
enough to use a single temperature sensor and some more
sophisticated solutions should be developed for real time
temperature monitoring. Such monitoring circuits, integrated
together with the monitored ones within a single IC, would
not only protect circuits from overheat but also could provide
useful feedback for design engineers.
The concept of real time circuit temperature monitoring
for power circuits is known already from the early nineties.
However, recently an entirely new possible application has
emerged for such monitoring systems in the field of chip
multiprocessor design [1]-[3]. With the advent of multicore
architectures, the exploration of the entire design space has
become a task of extreme importance from the performance
point of view. Knowing the exact temperature distribution
within an operating chip, engineers could design much more
efficient architectures and multithread algorithms as well
as develop new strategies for active voltage and frequency
scaling so as to maximize performance while maintaining
chip temperature within allowed safety margins.
This paper, based on a practical example of a thermal test
circuit, examines the influence of power dissipation pattern
and circuit cooling conditions on temperature distribution.
The following section is devoted to the description of the test
circuit. Then, thermal simulation results are analyzed and
compared with measurements. Next, important conclusions
regarding the possibility of realizing real time temperature
monitoring circuit are provided.
Fig. 1. Thermal test chip photograph.
II. TEST CIRCUIT DESCRIPTION
The test circuit was designed entirely in the Department
of Microelectronics and Computer Science of the Technical
University of Lodz and manufactured in the 0.35 micron high
voltage technology by austriamicrosystems ® . The general
photograph of the chip is shown in Fig. 1. The die dimensions
are 4.83 mm x 4.11 mm. In this paper, the presentation of the
circuit is limited only to the description of the components,
which are the most important from the temperature profile
investigation point of view, that is the heat sources and the
temperature sensors. For a more complete description of the
design, refer to [4]. Additionally, it should be mentioned that
this circuit does not fulfil all the JEDEC requirements for
a standard thermal test chip, unlike those described in [5]-[6],
because it was developed also for other purposes.
A. Heat Sources
The 620 μm x 40 μm heat sources, visible in the above
photograph, form a 3 x 3 matrix and consist of compound
high voltage 50 V NMOS transistors. These sources operate
for power supply voltages 20÷50 V and can be individually
switched on or off at any of 7 current levels evenly spread
up to 21 mA. Owing to this solution, it was possible to attain
high flexibility of power dissipation inside the chip.
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7-9 October 2009, Leuven, Belgium
B. Temperature Sensors
The temperature of the entire chip can be monitored with
25 sensors organized in a 5 x 5 matrix. The sensors, marked
in Fig. 1 by the white circles, are placed in the middle of all
the heat sources and on the outer limits of the heat source
matrix in each row and column as well as in the four corners.
These sensors consist of 3 in-series connected base-emitter
junctions of BJTs available in the chosen technology. The
sensor output signal is the voltage drop across two junctions.
The sensor signals can be directly accessed outside the chip
in the analog form through the appropriate pins or, after the
A/D conversion, they can be stored in the on-chip RAM.
III. TEMPERATURE MEASUREMENTS
The circuit under investigation, placed in a 120-pin CQFP
surface mount package, was soldered to the standard JEDEC
high thermal conductivity board with a square opening made
inside the pin perimeter, so as to render possible temperature
measurements in the Dual Cold Plate (DCP) arrangements
proposed within the PROFIT project [7].
A. Sensor Calibration
Before the measurements, all the sensors were calibrated
using the DCP-1 configuration, i.e. with the package tightly
squeezed between two aluminum spacers and some thermal
grease applied. The temperature was measured at the analog
sensor outputs and additionally, for control purposes, by thin
wire thermocouples mounted inside the copper spacers. The
calibration results are presented in Fig. 2. The markers show
the dispersion between the individual diodes, whereas the
solid line is the average sensor characteristic which is almost
perfectly linear with the negative slope of 2.7 mV/K.
B. Measurement Setup
The measurements were carried out in 2 configurations.
First, the DCP-2 was used where the top metal spacer was
replaced by the polyamide one. Then, when investigating the
influence of cooling conditions, the circuit was measured
without the cold plates inside the standard still air chamber.
Voltage (V)
1.75
1.73
1.71
1.69
1.67
1.65
1.63
1.61
1.59
1.57
1.55
1.53
20 30 40 50 60 70 80 90 100
Temperature (˚C)
Fig. 2. Measured sensor calibration curves.
Fig. 3. Modeled structure geometry.
The measurements were performed maintaining the same
amount of dissipated power, i.e. 0.9 W, but its distribution
among the heat sources varied. The obtained results were
used to provide the data necessary to create the detailed
system thermal model presented in the next section. In all the
cases the temperature differences between the experiment
and the simulation across the entire structure did not exceed
0.5 K, which is within the actual temperature measurement
accuracy.
IV. NUMERICAL SIMULATIONS
Knowing the structure geometry and the material thermal
data, an adequate thermal model of the system was created.
The drawing of the modeled structure is presented in Fig. 3.
All the dimensions given in the figure are in millimeters. The
technical details of the package are available on the Kyocera
Corporate or the Europractice websites.
The solution of heat equation resulting from the thermal
model of the structure was computed using the Tulsoft finite
difference solver [8]. First, the 28,000 node non-uniform
temperature gradient dependent mesh was created and then
the temperature distribution in the entire structure was found.
The total execution time on a medium class PC was less than
15 seconds.
A. Single Heat Source
First, it was assumed in the experiments that all the power
is dissipated in a single heat source and only its location was
changed. The silicon die temperature rise maps obtained for
the cases when the source was placed in the corner and in the
middle are shown in Figs. 4-5.
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7-9 October 2009, Leuven, Belgium
Fig. 4. Temperature map for a single source located in the corner.
B. Multiple Heat Sources
Then, the same amount of power was distributed evenly
among three corner sources and all the nine sources. Such
a situation can is typical in multicore architectures where the
computation is divided between the particular cores, which
are surrounded by cache memories and buses. The obtained
simulation results for these two cases are shown in Figs. 6-7.
C. Cooling Conditions Influence
Finally, simulations were carried out for the same three
previously considered sources, but for the free convection
cooling in the standard still air chamber without the cold
plates. Obviously, this required the adjustment of the heat
transfer coefficient value at the outer structure surfaces. The
results of this simulation are shown in Fig. 8.
V. RESULT DISCUSSION
The result analyses are divided into two parts: the study of
temperature distribution and the discussion on the possibility
of practical realization of real time temperature monitoring.
Moreover, in order to facilitate all the analyses, the table
showing the extreme temperatures in the die is included.
Fig. 5. Temperature map for a single source located in the middle.
A. Temperature Distribution
The obvious conclusion from the first experiment is that
the location of a single source does not matter too much for
the hot spot temperature. Obviously, the source is a bit hotter
when it is placed close to a die corner and the temperature
is slightly more uniform with the centrally placed source, but
the differences are not really significant.
Quite the opposite, the distribution of power dissipation
among the power sources brings significant decrease of the
hot spot temperature, already for only three sources. Further
reduction of the maximal temperature can be attained with
more sources, but the gain is not so important any more.
Another interesting observation is that in all the considered
cases, independently from the number of heat sources, the
minimal chip temperature remains fairly unchanged.
When the change of cooling conditions is concerned, one
can clearly see that the hot spot temperature rise increases
more than three times, though the temperature difference
in the chip remains at around 4 K. Note that the map legends
are different for all the figures and that they are global ones,
i.e. their range is adjusted for the entire structure with the
package not only for the silicon die itself.
Fig. 6. Temperature map for 3 active sources.
Fig. 7. Temperature map for all 9 sources active.
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7-9 October 2009, Leuven, Belgium
TABLE I
TEMPERATURE RISE DIFFERENCES WITHIN THE DIE
Power dissipation pattern
Max.
(K)
Min.
(K)
One corner source - water cooling 13.47 3.596
One middle source - water cooling 12.98 4.048
Three distributed sources - water cooling 7.748 3.758
Nine distributed sources - water cooling 6.344 3.912
Three distributed sources - free convection 25.73 21.75
Fig. 8. Temperature map for 3 active sources with free convection cooling.
B. Real Time Temperature Monitoring
Both simulations and measurements confirmed the fact
that with the forced water cooling the resulting temperature
distribution profiles in the chip are much steeper than with
the free convection cooling. To be more specific, assuming
that the problem is linear, from the table it can be obtained
that for the same hot spot temperature rise of 25.73 K, the
coldest location in the die would have the temperature rise
of only 12.5 K, whereas for free convection the measured
one is 21.75 K.
This observation has serious implication on the possibility
of practical realization of real time temperature monitoring.
For the forced water cooling, the main problem is the socalled
temperature damping, i.e. the attenuation of thermal
response. Because of this effect, the temperature rise, even
very close to a source, might be already quite negligible and
then sensors have to be placed as close as possible to each
source in order to avoid excessive temperature estimation
errors.
On the other hand, for free convection cooling the whole
die surface has quite uniform temperature and the difficulty
during the estimation consists not in the estimation of actual
source temperature but in the correct allocation of dissipated
power among the sources. Similar conclusions were also
drawn based on simulated data in [9], where the problem
of real time source temperature estimation, even with remote
sensor measurements, was discussed in detail.
VI. CONCLUSIONS
The presented numerical simulations confirmed by the p-n
junction temperature measurements demonstrated that both
the distribution of dissipated power and cooling conditions
have important influence on the temperature profile inside
semiconductor chips.
The considerations presented in this paper are important
not only in thermal optimization of power integrated circuits,
but at the same time they can serve as a useful guide in the
chip multiprocessor design, which is at the moment a very
dynamically developing field of electronic engineering.
ACKNOWLEDGMENT
This research was supported by the grant of the Ministry
of Science and Higher Education No. N515 008 31/0331.
REFERENCES
[1] K. Skadron, M Stan, K. Sankaranarayanan, W Huang, S. Velusamy,
and D. Tarjan, “Temperature-aware microarchitecture: Modeling
and implementation,” ACM T. Archit. Code Op., vol. 1, pp: 94-125,
March 2004.
[2] W. Liao, L. He, and K.M. Lepak, “Temperature and supply voltage
aware performance & power modeling at microarchitecture level,”
IEEE T. Comput. Aid. D., vol. 24, pp. 1042-1053, July 2005.
[3] M. Monchiero, R. Canal, and A. Gonzalez, “Power/performance/
thermal design-space exploration for multicore architectures,” IEEE
T. Parall. Distr., vol. 19, 666-681, May 2008.
[4] M. Szermer, Z. Kulesza, M. Janicki, and A. Napieralski, “Design
of the test ASIC for on-line temperature monitoring and thermal
structure analysis” [Proc. 15 th Intl Conf. Mixed Design of Integrated
Circuits and Systems MIXDES, pp. 317-320, June 2008].
[5] A. Poppe, G. Farkas, M. Rencz, Z. Benedek, L. Pohl, V. Szekely,
K. Torki, S. Mir, and B. Courtois, “Design issues of a multifunctional
intelligent thermal test die,” [Proc. 17 th Annual IEEE
Symposium Semiconductor Thermal Measurement & Management
Semi-Therm, pp. 50-57, March 2001].
[6] B. Siegal, and Galloway, “Thermal test chip design & performance
considerations,” [Proc. 24 th IEEE Symposium Semiconductor
Thermal Measurement and Management Semi-Therm, pp. 59-62,
March 2008].
[7] H. Pape, D. Schweitzer, J.H.J. Janssen, A. Morelli, and C.M. Villa,
“Thermal transient modeling and experimental validation in the
European project PROFIT,” IEEE T. Compon. Pack. T., vol. 27,
pp. 530-538, September 2004.
[8] M. Kaminski, M. Janicki, and A. Napieralski, “Application of RC
equivalent networks to modeling of nonlinear thermal phenomena,”
[Proc. 14 th Intl. Conf. Mixed Design of Integrated Circuits and
Systems MIXDES, pp. 357-362, June 2007].
[9] M. Janicki, and A. Napieralski, “Real time temperature estimation
of heat sources in integrated circuits with remote temperature
sensors,” J. Phys. Conf. Ser., vol. 124, 012027, 2008.
©EDA Publishing/THERMINIC 2009 139
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CMOS Temperature Sensors Based on
Thermal Diffusion
Caspar van Vroonhoven, Mahdi Kashmiri, Kofi Makinwa
Electronic Instrumentation Laboratory
Delft University of Technology
Mekelweg 4 HB13.060
2628CD Delft, the Netherlands
c.p.l.vanvroonhoven@tudelft.nl
Abstract- This work presents an overview of recent research
into integrated temperature sensors based on thermal
diffusivity sensing. Such sensors make use of the fact that the
thermal diffusivity of highly pure IC-grade silicon has a welldefined
temperature dependence and is insensitive to process
spread. To measure thermal diffusivity, an on-chip thermal
delay can be defined and then used to define the frequency of a
VCO. Alternatively, this delay can be directly digitized. Several
proof-of-concept devices fabricated in 0.7μm CMOS technology
demonstrate good accuracy and reproducibility. They achieve
untrimmed inaccuracies in the order of ±0.6ºC (3σ) over the
military temperature range (-55ºC to 125ºC), based on the
measured performance of 16 samples per batch.
I. INTRODUCTION
The thermal management of large ASICs such as
microprocessors has become essential. This is because of the
steadily increasing power dissipation and device density of
modern CMOS chips. Effective thermal management
requires that die temperature be accurately measured at
several locations [1] by integrated temperature sensors.
However, conventional integrated temperature sensors are
rather inaccurate (2ºC – 5ºC). This is because they rely on
the temperature-dependent behavior of transistors, which
varies significantly, especially in nanometer CMOS
processes. The inaccuracy of such sensors can be improved
by individual or batch calibration [2, 3], but this requires a
temperature-stabilized test infrastructure, which increases
manufacturing time and costs. Ideally, the inaccuracy of
sensors for thermal management applications should be low
enough (< ±1ºC) to avoid the need for trimming.
Die temperature can also be sensed by measuring the
thermal diffusivity of bulk silicon, which has a temperature
dependence that is approximately proportional to 1/T n (n ≈
1.8) [5]. As already observed in [8], this is an attractive
solution for thermal management applications, because the
thermal diffusivity of IC-grade silicon is very well-defined,
and thus can potentially be used to realize accurate
temperature sensors.
Temperature sensors based on thermal diffusivity sensing
date back to the 1960’s and 70’s [6, 7], but their accuracy
was limited. Also, the low signal amplitudes associated with
thermal diffusivity sensing resulted in poor temperaturesensing
resolution [8, 9], even when a large amount of heater
power was dissipated (>10mW).
Advances in CMOS technology and interface circuit
design have enabled the development of high-precision
thermal diffusivity sensors. Key improvements include
significant power reduction, increased accuracy, direct
digitization and full, CMOS-compatible integration. This
paper presents an overview of several recently presented
integrated temperature-to-frequency and temperature-todigital
converters [10-18]. In Section II, the sensor and its
operation are discussed in more detail. Two implemented
readout architectures are described in section III. The
corresponding measurement results are presented in section
IV. The paper ends with conclusions.
II. THE ELECTROTHERMAL FILTER
The thermal diffusivity of silicon, D can be determined by
measuring the characteristics of an Electrothermal Filter
(ETF). Fig. 1 shows a simplified layout of a CMOS
implementation. An ETF consists of a heater and a relative
temperature sensor, separated by a distance s. The heater is
created using an n+-diffusion resistor, while the relative
temperature sensor consists of a number of series-connected
p+-diffusion/aluminum thermocouples, i.e. a thermopile.
s heater
thermopile
V tp
Figure 1: Schematic diagram of an Electrothermal Filter (ETF).
n-well
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7-9 October 2009, Leuven, Belgium
Because D is finite, there is a finite delay before AC
ETF
power dissipated in the heater creates temperature fluctuations
at the thermopile. As such, an ETF can be seen as a thermaldomain
low-pass filter with temperature-dependent filtering
φ constant
characteristics.
f ETF
(T)
(a)
The filtering characteristics of an ETF can be analyzed by
modeling the thermal transfer impedance between the heater
and the junctions of the surrounding thermopile. For complex
heater geometries, such as in the ETF of Fig. 2, this can be
done by approximating the heater’s volume by a number of
spheres, for which the heat equation is solvable [15, 19]. Using
this model, the hot and cold junctions of the thermopile can be
located on contours of constant phase shift [15], so that the
vector sum of the various thermocouple voltages, and hence the
ETF’s output amplitude, is maximized.
Heater
Thermopile
Phase shift in degrees
100
80
60
f constant
ETF
φ ETF
f ETF
φ ETF (T)
(b)
(c)
160
110
60
Frequency in kHz
S
-60
0 60 120
Temperature in °C
Figure 3: Temperature-dependent ETF output characteristics for both phaseand
frequency readout.
100 µm
Figure 2: Photo of a CMOS ETF; the thermocouple junctions are aligned to
have the same thermal impedance to the center of the heater.
To understand how an ETF can be used to measure
temperature, we consider a simplified ETF, consisting of a
point heater and a point temperature sensor. When such an ETF
is driven at a frequency f ETF , it has a phase shift φ ETF , which can
be approximated by:
φ ∝ s
ETF
fETF
D( T )
If either f ETF or φ ETF is kept constant, as shown in Fig. 3a
and 3b respectively, the other will be a function of temperature.
Simulation results are shown in Fig. 3c (for s =20 μm, f constant =
85kHz, φ constant = 90°, D(300K) = 0.89cm/s 2 ).
(1)
From Eq. 1, it follows that in constant phase mode, f ETF (T)
is proportional to 1/T 1.8 , and that in constant frequency
mode, φ ETF (T) is proportional to T 0.9 . The effect of thermal
expansion on s is at the 0.05% level, and is neglected here.
The absolute accuracy of an ETF depends on the accuracy
of its geometry, defined by s, and on D. For IC-grade bulk
silicon, D is well-defined. For low doping levels, it is also
insensitive to process spread [4]. The temperature-sensing
inaccuracy of an ETF is therefore defined by spread in the
distance s, which is caused by lithographic error (e.g. mask
misalignment). This error can be minimized by making s
sufficiently large.
III. ETF READOUT ARCHITECTURES
The main problem associated with reading out an ETF is
its low output amplitude. Self-heating and power
consumption issues limit the amount of power that can be
dissipated in the ETF heater. Since silicon is a good thermal
conductor, this means that, for a heater power of say 2.5mW,
the temperature gradient across the thermocouples is only in
the order of 40mK. Assuming a thermopile made up of 20
thermocouples, each with a sensitivity of 0.5mV/K, this
leads to a thermopile output voltage with an amplitude of
about 400μV pp . Due to the presence of wideband white noise
from the thermopile’s resistance, the measurement
bandwidth then needs to be limited to about 0.5Hz to obtain
a temperature-sensing resolution of 0.05ºC.
©EDA Publishing/THERMINIC 2009 141
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ETF
∫
VCO
f vco
(T)
output
7-9 October 2009, Leuven, Belgium
pin DIL package used, the chip’s 5mW power dissipation
heats the chip to about 0.5°C above ambient temperature,
which creates an offset in the output characteristic that is
intrinsic to using a heater. This offset is systematic, and so
does not introduce device-to-device spread. Errors due to
mismatch in power dissipation or thermal impedance of the
package are estimated to be at the 0.05°C level.
Figure 4: Constant-phase ETF readout architecture
As shown in Fig. 3, an ETF can either be driven at
constant phase or at constant frequency. To keep φ ETF
constant while limiting the measurement bandwidth, the
system shown in Fig. 4 can be used. An integrator adjusts the
output frequency of a voltage-controlled oscillator (VCO)
until the integrator’s average input becomes zero. Since this
is the output of a multiplier, this corresponds to a 90° phase
shift between its two inputs, and so φ ETF is forced to 90°. The
output frequency, f vco , is then proportional to 1/T 1.8 . The
integrator reduces the system bandwidth to a narrow band
around f vco [10-15].
A similar architecture can be used to operate an ETF at
constant frequency (Fig. 5). Here, f drive is derived from a
reference clock, e.g. the crystal oscillator available in most
digital systems. The use of a reference frequency enables a
direct digital output, since the ETF’s thermal delay can now
be compared to a reference. The ETF is now driven at a
constant frequency, so its phase shift is temperature
dependent. The ETF output signal is multiplied with a phaseshifted
copy of the driving frequency, in such a way that,
again, the integrator input becomes zero. This phase-shifted
signal is generated by a digital phase rotator that is driven by
an n-bit ADC. In this way, the output of this system will be a
digital approximation of φ ETF [16, 17].
f drive
ETF
n-bit digital
phase rotator
Figure 5: Constant-frequency ETF readout architecture.
∫
n
n-bit ADC
f s
digital output
For the constant-phase readout architecture, the frequency
versus temperature characteristic is shown in Fig. 6. The
measured phase shift of the ETF in constant frequency mode
(f drive = 85 kHz) is shown in Fig. 7 [16].
In constant frequency mode, the untrimmed device-todevice
spread, measured for 16 devices from a single batch,
corresponds to a worst-case temperature error of ±0.6ºC (3σ)
over the military temperature range (-55ºC to 125ºC) [16].
Fig. 9 shows the measured temperature error of each device
when compared to the average of all measured devices; the
3σ limits were calculated based on this data. The measured
spread is dominated by errors caused by lithographic
inaccuracy (i.e. spread in the distance s). Similar results were
obtained with the constant-phase architecture.
Thermal diffusivity sensors are insensitive to (high
temperature) leakage currents, because the temperature
information is in the time domain. Therefore, they also work
over a wide temperature range (-70ºC to 160ºC) [18].
Also, in contrast with traditional temperature sensors,
inaccuracy is expected to improve in more advanced CMOS
technology, as higher lithographic resolution will further
reduce device-to-device variations in the thermal delay.
frequency (kHz)
200
180
160
140
120
100
80
60
-55 -35 -15 5 25 45 65 85 105 125
Temperature (°C)
Figure 6: Measured output frequency as a function of temperature.
IV. MEASUREMENT RESULTS
Both the architectures described above have been fully
integrated in a 0.7μm CMOS technology (Fig. 8), and
measurements show good accuracy and reproducibility [12,
16]. The interfacing circuitry uses 2.5mW from a 5V supply,
and the power dissipated in the ETF was set to 2.5mW. At
this power level, the temperature resolution in a 0.5Hz
bandwidth was measured to be 0.05°C. For the ceramic 16
©EDA Publishing/THERMINIC 2009 142
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Temperature error in ºC -->
φETF (degrees)
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
100
95
90
85
80
75
70
65
60
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
Figure 7: Measured phase shift as a function of temperature.
Figure 8: Chip photo of one of the proof-of-concept devices.
-1
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature in ºC -->
Figure 9: Temperature error over temperature for 16 devices; the black lines
indicate 3σ limits.
CONCLUSIONS
This paper has presented an overview of recently
developed integrated temperature sensors based on thermal
diffusivity. The thermal diffusivity of bulk silicon is a welldefined
function of temperature, and as such can be used to
create accurate temperature sensors. An Electrothermal Filter
(ETF) can be used to realize a temperature-dependent
7-9 October 2009, Leuven, Belgium
thermal delay, which can then be measured in various ways.
Proof-of-concept devices, realized in 0.7μm CMOS
technology, provide either a frequency or a digital output
that is a function of temperature. Without trimming, the
measured device-to-device spread is ±0.6°C (3σ) over the
military temperature range (-55°C to 125°C). This error is
dominated by lithographic inaccuracy, and is expected to be
much less in nanometer CMOS technology, as higher
lithographic resolution will reduce the device-to-device
variations in the thermal delay. Therefore, thermal
diffusivity sensors are well-positioned as temperature
sensors for thermal management in large ASICs and
microprocessors.
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7-9 October 2009, Leuven, Belgium
High-Level Thermal Profiling of Mobile Applications
Marius Marcu
“Politehnica” University of Timisoara
2 V. Parvan Blv.
Abstract- Power consumption and heat dissipation are the
major factors that limit the performance and mobility of battery
powered devices. As they become key elements in the design of
mobile devices and their applications, different power and
thermal management strategies have been proposed and
implemented during the last years in order to overcome the
mobility limitation due to the battery lifetime. These design
strategies are usually implemented at the lower levels of the
systems, but one research direction in software development is to
implement thermal and power control techniques at the higher
levels of the system. The work presented in this paper evaluates
the thermal response of the mobile system components related to
the running software applications.
I. INTRODUCTION
Thermal behavior is expected to be an important design
consideration for the next generation of microprocessors,
both for high-performance computing and mobile computing
[1]. Proper thermal management depends on two major
elements: thermal packaging and thermal management.
Thermal packaging includes heat-sink properly mounted to
the processor and effective fans directing airflow through the
system chassis [2]. Dynamic thermal management (DTM)
strategies are used to reduce packaging cost without
unnecessarily limiting performance, the package is designed
for the worst typical application and any application that
dissipate more heat should activate an alternative, run-time
thermal management technique [3].
Dynamic thermal management (DTM) has been a hot
topic in last years [4]. The purpose of DTM is to achieve
high-performance computing while maintaining the chip
below a safe temperature [5]. However DTM techniques
usually address the low-level layers in a computing system:
hardware level, BIOS level and OS level. Addressing
thermal management at higher levels of a computing system
does not replace the DTM already implemented at lower
levels, but extends these techniques to user applications and
permits applications to adapt themselves in order to reduce
the heat dissipation of the whole software and hardware
system.
The present paper tries to describe thermal profiling of
software applications. In fact we want to know the thermal
impact on different system components due to the running
software applications. The final goal of our work is to
establish a set of rules for thermal-aware applications and to
implement them in mobile applications.
This section will continue with a brief description of other
recent or important papers in this research field. The authors
of [1] investigate in their work the benefits of thermal-aware
task scheduling with minimum performance degradation.
Timisoara, Romania
They consider that the task scheduler in a multi-tasking
system can use thermal metrics when running different
active tasks in order to reduce the number of cycles above
the thermal threshold allowed for the microprocessor [1].
Multicore architectures are becoming the main design
paradigm for current and future processors, including mobile
processors, because these architectures provide increased
parallelism within the energy and thermal limits needed by
such devices. The authors of [6] present an detailed study of
different DTM techniques that can be used in multicore
designs. They consider that thread migration and dynamic
voltage and frequency scaling techniques are the most
promising methods to control temperature in multicore
architectures.
Software level thermal management becomes an attractive
extension to low level management techniques. In [7] the
authors describe a software solution for temperature sensing
methodology that can be used for thermal profiling of
software applications. The temperature model is based on the
interface with some system components parameters through
performance counters.
In [8] a software framework for dynamic energy
efficiency and temperature management for computing
systems is presented. The authors address both energy and
temperature in a unified approach which combines a suite of
energy-management techniques that can be activated
individually or in groups according to a given policy. The
evaluation has shown that the proposed framework [8] is
very effective, because it delivers a 40% energy reduction
with only a 10% application slowdown.
In the core of dynamic thermal management schemes lies
accurate reading of on-die temperatures [9]. Thermal
management techniques based on on-line temperature
sensing depend on monitoring sensors placement inside the
processor chip and cores. In [9] the authors propose three
techniques to create sensor infrastructures for monitoring the
maximum temperature on a multicore system. They
investigate the number of sensors and their placement, the
number of active sensors and their selection in order to
collect and predict the maximum temperature of each core in
the microprocessor.
An important aspect addressed also in our work is the
unification of power consumption and thermal management
[8,10]. The paper is organized as follows. In the next section
we define the thermal profiling concepts and the software
tool we implemented to characterize the thermal behavior of
a mobile device and its applications. Some experimental
results are presented in Section 3 and Section 4 contains our
concluding remarks.
©EDA Publishing/THERMINIC 2009 144
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II.
THERMAL PROFILING OF MOBILE DEVICES
A. Thermal benchmark software
We build the thermal profiles for mobile applications
using the concept of thermal benchmarks. We defined
thermal benchmark as a software application that
characterizes the thermal behavior of the system, component
or application with respect to certain stimulus (workload). A
thermal benchmark must by able to distinguish the way a
hardware device temperature is increasing with workload
and the way its temperature decrease when the workload is
finished [11]. We address with our tests the CPU cores
temperatures.
7-9 October 2009, Leuven, Belgium
software applications has a big influence on the temperature
generation.
Temperature [oC]
100
90
80
70
60
50
40
30
20
10
CPU thermal profile
0
0 100 200 300 400 500 600 700 800 900
Time [s]
Fig. 2. Thermal signature for a processor
CPU Temp
100
90
CPU usage profile
Time [s]
80
70
60
50
40
CPU Usage
Fig. 1. Thermal benchmark definition
A thermal benchmark is composed from three components
(Fig. 1):
- The first range [0-t1), is intended for idle mode
temperature. During this time interval the CPU is in the idle
state, the power management and saving mechanisms of the
CPU are prevented to occur and the system’s and
component’s parameters are monitored. This interval is used
to estimate the idle state temperature of the CPU cores and to
let them to achieve their idle state temperature.
- The second range [t1-t2) represents the warming
phase, when a certain workload is executed. SPEC CPU2000
or any type of software applications can be executed as
workload. We used in our tests one integer benchmark for
the CPU. During this time interval, the component executes
its job and the system’s and component’s parameters are
continuously measured. While the CPU is running the
benchmark its temperature increase in time until its cores
achieves their equilibrium state.
- The last range [t2-t3) represents the cooling phase
intended for the component to reach again the idle state
temperature. Within this step, the CPU is idle and the
parameters are monitored. During this interval the CPU
cores’ temperatures decrease until the idle temperature is
reached.
Running the benchmark on the same system a large number
of times and averaging the measured temperatures we obtain
the standard thermal signature of a certain processor for the
selected workload (Fig. 2 and Fig. 3).
B. Thermal profiling test cases
The thermal dissipation problem of computing systems is
in general a very complex one because each physical
component from the system has its own temperature values
depending especially on the execution operation type, so that
we can say that together with the physical components, the
30
20
10
0
0 100 200 300 400 500 600 700 800 900
CPU Usage [%]
Fig. 3. CPU load when integer benchmark was applied
For every heat source in the system we can establish
different thermal profiles (or thermal signatures) which
express the thermal dissipation of the component for a given
utilization profile (e.g. applied stimuli or workload). Every
thermal profile is identified by a set of temperature values
corresponding to different component usage models. A
component usage model assumes a certain workload level of
the running component. The temperature profiles we define
establish a relationship between power states, workloads and
energy consumed by the device or component being in these
states.
The process of extracting temperature profiles for a
computing system is called system thermal profiling or
characterization. In order to extract thermal profiles for CPU
we propose a set of test that can be run multiple times for
every system.
CPU thermal profiles present a description of the CPU
heat dissipation over the time when it executes different
workloads with well known parameters. CPU thermal
profiles are considered as a characteristic feature of the CPU
because when it executes a specific workload a number of
times with the same parameters, the same temperature
profiles are obtained. In order to produce the CPU thermal
profiles a number of tests are further introduced. CPU
thermal profiling test cases are based in the thermal
benchmarks introduced before. During thermal
characterization the tests are running for a certain amount of
time when the measurements and efficiency metrics are
collected and recording by the framework.
- CPU idle temperature: The CPU idle state thermal
©EDA Publishing/THERMINIC 2009 145
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profile describes the temperature variation over the
time when the CPU is idle and do not execute any
application, except the default operating system
services. When the idle test is executed the CPU
configuration parameters are set to default values, no
workload is applied and no other user application or
interaction is allowed. CPU default parameters mean
that all cores are active and idle.
- CPU workload type temperature: The CPU generates
distinct heat levels for any instruction it executes.
Some complex instructions generate higher
temperatures to complete than the simple CPU
instructions. However, at the higher levels the system
cannot seize the differences between the thermal
levels of two instructions, but we need an idea of heat
dissipation of different instruction classes: integer,
memory, floating point, etc. In case we know what
kind of operations an application thread uses we can
estimate its temperature for a specific workload.
- CPU usage level temperature: The same workload the
CPU can execute at different usage levels which may
imply different temperature levels for the same type
of workload. Using this profiling test we want to
emphasize the relation between temperature and CPU
usage or CPU time for certain workloads. Inside this
test the same workload is repeatedly executed with
different sleeping times in order to achieve different
values for CPU usage.
- CPU multithreading temperature: Another proposed
CPU profile test is to launch the same algorithm
workload on different thread counts using one single
core. Using this test the OS task scheduling and
switching operations along with workload operations
are observed in order to get their temperature. In a
multithreading test case it creates a number of threads
running the same workload in order to see how thread
count influence the overall temperature.
- CPU multicore temperature: For multicore processors
two new tests are needed to establish the relation
between the number of active cores and their
individual and cumulated temperatures. First, the test
is used to activate every core one at the time to run
the same workload, in order to see how much heat
generates every active core. Next, the test activates
successively step by step one more core while
keeping the previous active and run the same
workload on every active core, in order to emphasis
the increasing temperatures for every new active
core.
C. Thermal profiling tool
We implemented the thermal benchmarks and thermal test
cases in a software application. Fig. 4 presents the overall
architecture of this application. From the beginning we
intended to build a portable monitoring application in order
to run benchmarks on different platforms characterized by
different hardware devices and operating systems. A design
constraint was that we required the application to be scalable
in order to easily support new types of sensors and chipsets,
7-9 October 2009, Leuven, Belgium
new types of measurement parameters and new types of
workloads to be applied. In order to achieve a portable and
scalable application we split it in a number of specialized
modules: battery monitor, external power consumption
monitor, thermal monitor, CPU and cores monitor and task
monitor. More detailed data on the profiling application can
be found in [12].
Battery
monitor
Workload
generator
Power
monitor
Power-Thermal framework
Thermal
profiler
Power-Thermal framework core
Thermal
monitor
Chipsets and sensors
CPU
monitor
Thermal
profile logger
Task
monitor
Fig. 4. Thermal profiling application architecture
A thermal benchmark can be applied to every hardware
device with built-in thermal monitoring capability (such as
microprocessor, hard disk or video). The majority of
microprocessors produced in last years include at least one
built-in thermal sensor to aid in thermal management of
servers, workstation or portable systems. As this thermal
sensor is connected to a thermal diode on the processor core,
it provides the earliest indication of thermal variation that
can be read through our hardware monitor module.
III. THERMAL PROFILES OF SOFTWARE APPLICATIONS
The proposed test cases were run on one device: Fujitsu
Siemens laptop, E series, Intel Core Duo Mobile processor, 2
GHz, 1.5 GB memory, production year 2006. Every test case
was run a number of times as much as possible at the same
external conditions (e.g. temperature). Every test last 15
minutes and follows the same pattern: 5 minutes idle - 5
minutes workload and 5 minutes idle. While a test is run, the
system parameters are continuously monitored: battery
discharge rate, CPU temperatures and core temperatures,
CPU usage and cores usages, CPU usage for the benchmark
application. These parameters were logged and were
processed and analyzed after the test.
A. CPU Thermal Profiles
Thermal profile of a processor when executing high
intensive computations is shown in Fig. 2. The CPU load is
100% and CPU temperature increase in time until the heat
balance is achieved. When the workload is executed on a
multicore architecture the single treaded benchmark
application is continuously switched from one core to
another. The overall CPU usage for the single threaded
integer test application is 50% and the application receives
different processor time from every core (Fig. 5). Thermal
profiles of CPU and CPU cores when the same integer
workload is executed are presented in Fig.6. The CPU cores
are not at the same temperature because they are not
balanced used.
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CPU Usage [%]
100
90
80
70
60
50
40
30
20
10
CPU usage
Core 0 usage
Core 1 usage
7-9 October 2009, Leuven, Belgium
- long delays (CPU usage = 50-75%) - Fig. 8, inside
the workload algorithm, with a selectable frequency,
long delays are introduced. Depending on the delays
periods and frequency different CPU loads could be
achieved, but we obtained also different thermal
profiles. Therefore, in some cases we can control and
adapt a software application in order to reduce the
heat dissipation due to this application (Fig. 8).
T [oC]
54
0
0 100 200 300 400 500 600 700 800
Time [s]
Fig. 5. CPU and cores usage for single thread test
51
48
0ms
25ms
40ms
50ms
100
90
80
45
t [s]
0 500 1000 1500 2000 2500
Temperature [oC]
70
60
50
40
30
20
CPU temp
Core 0 temp
Core 1 temp
CPU [%]
100
75
50
100%
75%
60%
50%
10
25
40
38
36
34
0
0 100 200 300 400 500 600 700 800
Time [s]
Fig. 6. CPU and cores temperatures for single thread test
The same CPU workload when executed at different CPU
loads could have different thermal profiles function of the
workload is implemented in software. For example the same
workload was implemented in three ways:
- full performance (CPU usage = 100%) - Fig. 7, the
workload is implemented for best performance.
- short delays (CPU usage = 50%) - Fig. 7, inside the
workload algorithm, after a number of iterations short
period Sleep function calls were introduced.
Depending on the frequency of Sleep calls different
CPU loads we could achieve.
T [oC]
42
0
t [s]
0 500 1000 1500 2000 2500
Fig. 8. Long sleeps workload implementations
Running the same test with different delay parameters, so
that a workload is executed with different CPU usage levels
the plots in Fig. 9 were obtained.
Core 0 Temperature [oC]
100
90
80
70
60
50
40
30
20
Core temperature vs. core usage
10
0
0 10 20 30 40 50 60 70 80 90 100
Core 0 usage [%]
CPU temperature vs. CPU usage
100%
90%
70%
32
30
t [s]
0 200 400 600 800 1000 1200 1400 1600
CPU [%]
100
75
50
25
0
t [s]
0 200 400 600 800 1000 1200 1400 1600
Fig. 7. Full performance and short sleeps workload implementations
CPU Temperature [oC]
100
90
80
70
60
50
40
30
20
10
0
0 10 20 30 40 50 60 70 80 90 100
CPU usage [%]
Fig. 9. (a) CPU core temperature versus CPU core usage;
(b) CPU average temperature versus CPU usage
50%
45%
35%
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In Fig. 9 (a) the same integer workload was run on core 0
at 100%, 90% and 70% CPU core usage levels. Four groups
of dots can be observed: one cluster for the idle state
temperatures and three clusters for the workload
temperatures. The same pattern we can observe for the
relation between CPU usage levels and average CPU
temperatures. There is direct relation between CPU core
temperatures and the CPU time (in terms of usage level) for
the same type of workload, therefore we can estimate the
contribution of the application to the CPU heat generation.
Another aspect we investigated was the influence of
different workload types on CPU cores’ temperatures. Fig.
10 shows the thermal profiles of four workload types:
integer, float, memory and SSE executed successively for
the same amount of time on the same CPU core. Based on
this test, in order to estimate the effect of a CPU intensive
application over the temperature we have to know the type
of operations the application implements.
Temperature [oC]
100
90
80
70
60
50
40
30
20
10
0
0 100 200 300 400 500 600 700 800 900
Time [s]
Integer
Float
Memory
SSE2
Fig. 10. Heat dissipation and power consumption
B. Heat dissipation and Power consumption
Part of the battery energy of a mobile device is
transformed into heat. The increase in temperature enforces
more energy to be consumed. In Fig. 11, power consumption
profile for the previous memory workload is presented.
40000
35000
Battery power consumption
7-9 October 2009, Leuven, Belgium
current profile. This increase of approx. 4W during the
workload execution is due to the heating of the device.
C. Multithreading and Multicore Thermal Profiles
First we run one single workload thread on every CPU
core available in the processor: when the workload was run
on core 0 the plot in Fig. 12 (1) was obtained and when it
was launched on core 1, the plot (2) describes the
temperature variation. When the workload thread set its
affinity to both CPU cores, we obtained the plot (3) in Fig.
12. For this case the operating system schedules the thread
on both cores uneven (in our presented test: 75% core 0 and
25% core 1). It can be also observed that the CPU cores’
temperatures are not equal even if they run the same
workload 100% (Fig. 12 (1) and (2)).
Temperature [oC]
Fig. 12. CPU cores temperatures
The second test presented in Fig. 13 describes the results
of (1) one workload thread executed by one core, (2) two
workload threads executed by one single core and (3) two
threads run by both CPU cores.
Temperature [oC]
120
100
80
60
40
CPU cores temperatures
100
90
80
70
60
50
40
30
20
10
0
0 100 200 300 400 500 600 700 800 900
Time [s]
CPU cores temperatures
(1) Core 0 100%
(2) Core 1 100%
(3) Core 0 75%
(3) Core 1 25%
(1) Core 0 100%
(2) Core 0 100%
(3) Core 0 100%
Power consumption [mW]
30000
25000
20000
15000
10000
5000
0
0 100 200 300 400 500 600 700 800 900
Time [s]
Fig. 11. Heat dissipation and power consumption
During the second phase of the benchmark, when the
workload is applied, the temperature of the processor and
also the temperature of the entire mobile device increase (in
our example the temperature increases from 60 to ~100 o C).
This increase in temperature of has an effect on power
consumption, and a smooth increase (from 30W to 34W)
during phase 2 of the benchmark can be observed in the
20
0
0 100 200 300 400 500 600 700 800 900
Time [s]
Fig. 13. CPU threads temperatures
D. Thermal-Aware Application
We implemented a database application with long
database processing tasks. The application was written in
Visual C++ 2005, uses MS SQL server. The database
processing task was implemented with different thermal
management operations. In Fig. 15 thermal signatures for the
same task workload implemented with different thermal
management techniques are presented. We can reduce
maximum CPU temperature with around 10 o C implementing
DTM at application level (AP) with a decrease in
performance of 40%.
©EDA Publishing/THERMINIC 2009 148
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T [oC]
55
50
45
40
35
30
t [s]
0 500 1000 1500 2000 2500
Fig. 15. Heat dissipation and power consumption
IV.
CONCLUSIONS
100% (SO)
75% (SO)
60% (SO)
60% (AP)
The work presented in this paper tried to evaluate the
thermal response of the mobile system CPU and its cores
related to the running software applications. We tried to
characterize the thermal impact of system CPU cores due to
the workload threads of the executed applications. We
investigated the possibility to identify the effect of every
running application in the system over the CPU, cores and
system temperatures. We proposed a set of test cases to
identify relation between different system’s and
application’s parameters and temperature. Based on our
experiments, the process of thermal effect split among
running applications is not a simple task and depends on
many factors. For certain cases and workloads we can do
that split based on workload type, CPU usage level and
threads and cores used.
ACKNOWLEDGMENT
This work was supported by Romanian Ministry of
Education CNCSIS grant 680/19.01.2009.
REFERENCES
[1] Eren Kursun, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip
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[2] S.H. Gunther, F. Binns, D.M. Carmean, and J.C. Hall, “Managing
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[3] K. Skadron, M.R. Stan, W. Huang, S. Velusamy, K.
Sankaranarayanan, and D. Tarjan, “Temperature-aware
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[4] Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy,
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[5] V. Szekely, M. Rencz, and B. Courtois, “Tracing the Thermal
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[6] Pedro Chaparro, Jose Gonzalez, Grigorios Magklis, Qiong Cai, and
Antonio Gonzalez, “Understanding the Thermal Implications of
Multicore Architectures”, Ieee Transactions On Parallel And
Distributed Systems, Vol. 18, No. 8, Aug. 2007.
[7] Kyeong-Jae Lee and Kevin Skadron, “Using Performance counters
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and Distributed Processing Symposium (IPDPS’05), 2005.
[8] Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep
Torrellas, “A framework for dynamic energy efficiency and
temperature management”, Proceedings of the 33rd annual
ACM/IEEE international symposium on Microarchitecture, pp. 202-
213, 2000.
[9] Jieyi Long, Seda Ogrenci Memik, Gokhan Memik, and Rajarshi
Mukherjee, “Thermal Monitoring Mechanisms for Chip
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[10] Ke Meng, Russ Joseph, Robert Dick, and Li Shang, “Multioptimization
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[11] Marcu Marius, Vladutiu Mircea, Moldovan Horatiu, Popa Mircea,
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[12] Marcu Marius, Dacian Tudor, Moldovan Horatiu, Sebastian Fuicu
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©EDA Publishing/THERMINIC 2009 149
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7-9 October 2009, Leuven, Belgium
Hotspot-adapted Cold Plates to Maximize System Efficiency
Thomas Brunschwiler, Hugo Rothuizen, Stephan Paredes, and B. Michel
IBM Research GmbH, Zurich Research Laboratory, 8803 Rüschlikon, Switzerland
tbr@zurich.ibm.com, +41 44 724 86 81
Evan Colgan
IBM T.J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY 10598, USA
Pepe Bezama
IBM East Fishkill, 2070 Route 52, Hopewell Junction, NY 12533, USA
This modeling study is focused on the potential and the
limitations of hotspot-adapted liquid heat removal to improve
on system pumping power and on the re-usability of output
heat, for various packaging schemes at the component level.
This is in particular important to improve the power efficiency
of datacenters with the consequence to reduce total cost of
ownership and their impact on the environment. Inefficient air
cooling is responsible for up to 40% of their total power
consumption. High-performance liquid cooling has the
potential to reduce this number substantially and makes the
direct re-use of produced heat in neighborhood-heating
networks viable. The application of normal-flow and crossflow
cold plate architectures is discussed.
Custom-tailored normal-flow cold plates can be produced with
high spatial contrast in heat transfer with a granularity of
1 mm 2 . For conventional processor chip packages this results
in a flow rate reduction and fluid temperature differential
(T fout -T fin ) increase of 28%. This also translates into a net
pumping power decrease of 43% for a server rack with
multiple heat sources.
Heat flux tailoring with cross-flow heat exchangers is subject
to the additional constraint of a fixed volume flow over the
length of the channels, which calls for modulation of the heat
transfer geometry along the channel in order to address hot
spots. In this study the fluid flows through a layered-mesh
network, in which the number of mesh layers is modulated.
For standard packages employing thermal grease interfaces,
we find that for a given flow rate, there is little benefit in terms
of maximal junctions temperature at the expense of a
significant increase in pressure drop. The parameter
improving is the on-chip temperature variation.
We conclude the study with recommendations on how to
design hotspot-adapted cold plates.
I. INTRODUCTION
Worldwide, the number, size, and power consumption of
datacenters doubled between 2000 and 2005 due to
information technology (IT) consolidation trends and
increased demand from Web2.0 applications, such as video
streaming. Large datacenters consume up to 200 MW of
electricity, of which 40% is used only to run the cooling
infrastructure and is representing a significant portion to the
operating cost [1]. This is the result of the use of inefficient
air-cooling technology, which relies on computer-room airconditioners.
The power usage effectiveness (PUE), defined
as the ratio of total datacenter power divided by the power
consumption of the IT equipment, can be improved by
implementing advanced liquid-cooling technology [2]. For
low thermal gradients from junction to the fluid of ≤ 20 K
and a junction temperature limit (T jmax ) of 85°C, the ITequipment
can be cooled without chillers all year long.
Moreover, in cold and moderate climates, the ≥ 65°C
“waste” heat from liquid cooling can be sold to district
heating networks [3]. The value of this available heat
depends strongly on the its quality, namely temperature
level.
In this study we report on the potential benefits of hotspotadapted
cold plates on the component level. Cooling the
spatially non-uniform power dissipation of processors [4] by
means of uniform heat transfer is not a efficient solution [5].
Too much pumping power is spent on chip areas with low
heat flux. Furthermore exergy is reduced as the cold and hot
fluids mix at the outlet manifold of the cold plate, reducing
the value of the available heat. Moreover, this type of
cooling also results in high temperature gradients on the die,
causing thermo-mechanical-stress-induced aging.
Tailored, steady-state normal-flow and cross-flow heat
transfer concepts on the component level are presented and
benchmarked against uniform heat removal. Their benefit in
different packages is discussed. Finally the cold-plate
efficiency in a complete server rack with multiple heatgenerating
devices is reported.
II. SPATIALLY RESOLVED HEAT REMOVAL
Non-uniform heat transfer for a given unit-cell heat-transfer
geometry can be realized in normal flow (Fig. 1a) and jet
array cold plates [10] by local flow throttling. The parallel
fluid feed allows each unit cell to be addressed
independently, by changing the fluid delivery diameter of
each unit cell. The modulation in cross-flow heat
exchangers [9] is constrained. The volume flow rate can
only be changed for zones transversal to the flow direction,
but is constant for subsequent unit cells. Therefore the heattransfer
geometry (such as the channel hydraulic diameter or
cavity porosity) is modified to modulate all unit cells
individually (Fig. 1b).
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Fig. 1. Package cross-section illustrating the spatially resolved heat transfer
modulation concept for a) normal-flow and b) cross-flow architecture.
The hotspot addressing efficiency strongly depends on the
spreading characteristics of a package. The heat-flux
contrast in the cold plate base compared with the source is
reduced in classical packages because of the 720-μm
silicon die, the bottleneck of the thermal interface material
(TIM), and the cooler base plate. For interlayer-cooled 3Dchip
stacks, where coolant picks up heat 10 to 50 μm from
its source, smaller hotspots can be treated [6]. The gain of
hotspot cooling for direct-attach (Fig. 2a) and TIM-attach
(Fig. 2b) packages are investigated and compared.
Fig. 2. Schematic of a (a) direct-attach and (b) TIM-attach package.
(HT: heat transfer)
To maximize the available exergy, the fluid temperature
increase from inlet to outlet of the cold plate (ΔT fout-in ) at a
given maximal junction temperature (T jmax ) and power
dissipation (P el ) needs to be maximized. This translates
according to the sensible heat ( Q ) definition (1) with fluid
density (ρ) and heat capacity (c p ) into the minimization of
the flow rate (V ):
Q
V =
. (1)
ΔT fout
⋅ c ⋅ ρ
−in
p
This parameter is then used as the cost function in the heattransfer
optimization process, representing the inverse of the
exergy accordingly.
Moreover, the pumping power efficiency of the cold plate
is benchmarked. Most publications compare the cold plate
performance isolated from the complete cooling system.
Considering server-rack liquid cooling with many power
sources and parallel coupled cold plates, this is not a
meaningful metric. Additional fluid loop pressure drops due
to secondary fluid-fluid heat exchanger, filters, and fluid
quick-connections all add up to the total pressure drop. The
total system pumping power for low flow rate cold plates
with moderately increased cold plate pressure drop still is
reduced because of the minimization of the total flow rate
and parasitic pressure drop.
7-9 October 2009, Leuven, Belgium
III. NORMAL-FLOW COLD PLATE STUDY
For this test case, experimentally defined unit cell flow rate
( V ) to heat transfer characteristics (h ) of a
n , m
n,m
commercially available high performance normal-flow cold
plate is used [7] (Fig. 3) (Mikros Technologies). It is
hn
m k
V ,
n, m
= g ⋅( ) ⋅ An
, m
h
, (2)
0
with coefficients g = 4.97 × 10 -11 L/min/cm 2 , k = 1.939 and
h 0 = 1 W/(m 2 *K) for the unit-cell area A. All unit cells are
coupled in parallel to the manifold. Therefore the cell with
the highest heat-flux need defines the pressure drop from
inlet to outlet, and not the size of the cold plate area as in
cross-flow heat exchange. The cold plate flow rate (V ) is
computed by adding the unit-cell flow rates
. (3)
V
= ∑
V n , m
n,
m
The server-rack cooling-loop flow rate ( V
system
) and
pressure drop (Δp loop ) depend on the number of cold plates
(n) coupled in parallel and the coefficient of flow (k v
[L/min]) of the cooling loop:
V
system
= n ⋅V
V
system
and Δp
( )
2
loop
= ⋅ p0
, (4)
kv
with p 0 = 1 bar. For one server rack, we assume 56 cold
plates (Fig.3, green curve). The total system pressure drop is
the server-cooling loop plus the cold-plate pressure drop
Δp system = Δp cp + Δp loop .
Fig. 3. Heat transfer coefficient (h eff) and pressure drop characteristics of
the uniform cold plate at normalized volumetric flow rates (Δp cp) and a
typical server fluid loop pressure drop (Δp loop) attached to 56 parallel cold
plates.
A simplified power map of a high-performance processor
was chosen as model input (Fig. 4). The peak heat flux is
three to four times higher than the average power density of
50 W/cm 2 . Total power dissipation is 120W and the hotspot
area fill-factor is 10%.
©EDA Publishing/THERMINIC 2009 151
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7-9 October 2009, Leuven, Belgium
Table 1. Detailed results of uniform vs. tailored heat-transfer cold plates.
TIM-attach: case 1; direct-attach: cases 2 and 3.
Fig. 4. Simplified processor power map with hotspot area (red, orange).
The heat transfer surface is discretized with a granularity of
1 mm 2 according to the fabrication limit of one unit cell.
The heat-transfer coefficients of these unit cells can be
changed independently (Fig. 5). The heat-conduction problem
is solved with finite-element analysis using the commercial
solver ANSYS. As initial value a uniform heattransfer
coefficient was applied calculated from the package
thermal impedance, total chip power and available thermal
budget. The spatial distribution of the heat transfer coefficient
after each iteration is adjusted in proportion to the heat
flux map at the cooler base obtained in the preceding
iteration. This factor is adjusted in the course of sub-sequent
iterations to reach a convergence stop condition given by a
predetermined threshold value for ΔT jmax = T jmax N+1 - T jmax N .
A less stringent thermal budget was chosen for TIM-attach
owing to the additional TIM thermal resistance of 12 K
mm 2 /W. In both cases, fluid outlet temperatures ≥ 60°C are
achieved while maintaining a maximal junction temperature
of 80°C.
The cost ratios for flow rate, pressure drop, and pumping
power of the cold plate and the server-rack cooling loop is
shown in Fig. 6. The ratio is defined as performance of the
custom-tailored divided by the uniform heat-transfer cold
plate with the same package configuration. As expected
non-uniform heat transfer results in a reduced flow rate and
an increased fluid outlet to inlet temperature. This is
especially pronounced for heat removal close to the heat
source, such as case 3, corresponding to a quasi-onedimensional
heat flux. For the realistic case 1, the reduction
is 28%. Heat-transfer coefficient tailoring results in an
increased cold-plate pressure drop because of the need for
higher peak heat-transfer coefficients. Moreover, also an
increased cold-plate pumping power is needed in cases 1
and 2. Nevertheless, the system pumping power is reduced
by 43% for case 1 and by up to 97% for case 3 because of
the total flow rate reduction.
Fig. 5. Definition of boundary condition for the finite- element analysis.
Spatially resolved heat flux and heat transfer coefficients are applied on the
chip (orange) bottom side and cooler base (blue) back-side, respectively.
The resulting heat flux map at the cooler is the base for heat transfer
scaling for the next iteration.
The resulting flow rates and pressure drops for uniform and
tailored heat transfer for the TIM-attach (case 1) and directattach
(cases 2, 3) mode with a temperature gradient budget
of 20 and 10 K, respectively, is presented in Table 1.
Fig. 6. Cost ratios (parameter for tailored cold plate divided by that for
uniform cold plate) of cold-plate volumetric flow rate and pressure drop
(dp cp), as well as pumping power for the individual cold plate (P cp) and the
complete system (P system). TIM-attach: case 1, direct-attach: cases 2 and 3.
IV. CROSS-FLOW COLD-PLATE STUDY
The cross-flow cold plate is built of several 0.4-mm-thick
copper sheets (referred to as mesh layers) patterned using
©EDA Publishing/THERMINIC 2009 152
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photolithography and subsequent isotropic wet-etching. A
unit cell with a longitudinal and transversal periodicity of
1.5 mm and 0.87 mm, respectively, is shown schematically
in Fig. 7a. The individual copper sheets are oxidized,
aligned, compressed and annealed to form the cold-plate
cavity. Detailed information concerning the direct copper
bonding (DCB) process and the unit-cell geometry can be
found in [8] and [9], respectively.
a) b)
7-9 October 2009, Leuven, Belgium
The same power map as used in section III was the design
and modeling base (Fig. 4). A two-zone cold-plate
architecture is chosen to deliver the low-temperature inlet
fluid directly to the hotspots. The inlets are placed along the
long chip edge to minimize the pressure drop by reducing
the fluid flow distance to the central outlet (Fig. 9). The
flow rate in parallel zones can be modulated by changes in
mesh numbers. To prevent fluid bypassing, individual zones
are separated by solid walls.
Fig. 7. (a) Schematic of a single heat-transfer unit cell. (b) Stack of four
heat-transfer unit-cell layers (mesh layers).
Local heat transfer and fluid velocity can be modulated by
the number of mesh layers. This has the consequence of
changing fluid velocities and wetted surface area. We
computed the pressure gradient as well as the effective heat
transfer coefficient by means of detailed computational fluid
dynamic (CFD) modeling considering laminar flow in unit
cells having one to three mesh layers using the commercial
solver FLUENT. The CFD-mesh quality was assessed
and the residual target was set to 10 -5 as the convergence
criteria to minimize numerical artifacts. For a given flow
rate, the pressure need is monotonically reduced with the
number of mesh layers (Fig. 8). Reynolds numbers for the
considered pressure drop range are < 1000, therefore the
assumption of laminar flow is valid. The effective heattransfer
coefficient is maximal for two mesh layers because
of two competing heat transfer parameters: With increasing
mesh layer number, the wetted area responsible for heat
transfer is increasing linearly, while on the other hand the
fluid velocity is reduced.
Fig. 9. Top view of two-zone heat exchanger with two inlets at the chip
edge close to the hotspots and one outlet in the die center. Different mesh
densities represent different numbers of mesh layers. Flow rates are
throttled in low-power zones. Individual zones are separated by solid walls.
To efficiently model the heat transfer characteristic of such
non-uniform cold plates, a hybrid model was chosen and
implemented with ANSYS. The fluid flow and the
convective thermal resistance are represented with a lumped
resistor network. The resistor parameters are derived from
the detailed CFD modeling. Heat conduction in the solid is
computed by the finite-element method due to its simplicity.
One end of the convective thermal resistance is bound to the
wall temperature to realize heat flow between the solid and
fluid domain (Fig. 10).
Fig. 10. Schematic of the conjugated heat and mass transfer model using
lumped resistor elements for fluid flow (R fluid) and heat convection (R conv1,
R onv2). Heat conduction in the solid is computed by the finite-element
method. (a) Streamwise cross section showing the connection of the
lumped resistors to the solid. (b) Transversal cross section visualizing zone
separation and heat conduction path from cold-plate base to top plate
through solid walls. Solid-fluid heat transfer is only considered at the top
and the bottom plate.
Fig. 8. Pressure gradient (solid lines) and the effective heat transfer
coefficient (dashed lines) characteristic derived from CFD modeling for
mesh cavities having 1 to 3 layers.
Five test cases were defined with respect to the test power
map (Fig. 11). Case A) is the reference sample with uniform
flow rate and the largest heat transfer areas of 13.5 x 19
mm 2 . In cases B) and C), the flow is blocked completely or
throttled on low heat flux area. Changing mesh numbers in
streamwise direction is realized in design E). Two layer
©EDA Publishing/THERMINIC 2009 153
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meshes with highest heat removal rate are deployed on the
hot spots. Three layer meshes on low heat flux areas
minimize the pressure drop.
Fig. 11. Mesh design of test cold plates. Colors represent number of mesh
layers (pink 3, red 2, blue 1, turquoise no mesh). Dark blue squares are
inlets and outlets. In the lower left panel, the unit-cell alignment is shown.
With a silicon die size of 720μm and a thermal interface
resistance of 15 K*mm 2 /W the temperature gradient from
highest junction to fluid inlet temperature is not
significantly changed for all test cases (Fig. 12). Pressure
drop wise the uniform heat transfer utilizing all chip area for
heat transfer is performing best followed by the stream wise
cavity modulation experiment E). Non-uniform heat
removal only improves the temperature uniformity (ΔT j ) on
the die as indicated with the dashed lines. Case B)
outperforms uniform case A) by 5K.
7-9 October 2009, Leuven, Belgium
V. CONCLUSION
Tailored, steady-state normal-flow cold plate results clearly
demonstrate the potential of hotspot cooling in case of quasi
one-dimensional heat flux. Modeling suggests that the flow
rate can be reduced by 81% in case of 1μm die thickness
and direct-attach heat transfer mode. Both system pumping
power and fluid outlet temperature relevant for heat re-use
benefit from such low flow rate cold plates. However for a
realistic chip thickness of 720μm and thermal interface
(R TIM =12 K mm 2 /W) the benefit is shortened to a flow rate
reduction of 28% and system pumping power saving of
43%.
This pumping power and volumetric flow rate reduction
results in a improved power usage effectiveness in the
datacenter. Furthermore the increased fluid outlet
temperature increases the monetary value of the heat
potentially sold to a neighborhood-heating network.
In case of the presented cross-flow heat exchange
architecture the benefits for a realistic package including a
thermal interface are vanishing. The results show clearly,
that uniform heat transfer on the total chip backside is
resulting in equal peak junction temperature but reduced
pressure drop. The additional constraint of stream wise
constant flow rate in a certain fluid zone in combination
with the low change in heat transfer coefficient for varying
mesh cavity heights are responsible for poor heat transfer
contrast at the cold plate base. The only benefit of tailored
cold plates is the reduction in thermal gradient on the
processor die with the benefit of increased reliability.
We presented the benefits but also limits of hotspot cold
plates as a single component and applied in a server rack
with multiple processors. In standard TIM-attach packages
only cold plates with high heat transfer contrast in x and y
direction showed improved performance.
Further work on the normal-flow cold plate should
concentrate on eliminating the throttles by considering heat
transfer geometry modulation. For cross-flow heat
exchangers means to increase stream wise heat transfer
contrast have to be studied. We propose to change hydraulic
diameters instead of mesh cavity height.
Fig. 12. Maximal junction to fluid inlet temperature gradient (T jmax-
T fin)(full lines), chip temperature uniformity (ΔTj)(dashed lines with full
bullets), and pressure drop (full lines, empty bullets) of all cross-flow
heat exchange cases.
©EDA Publishing/THERMINIC 2009 154
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VI. NOMENCLATURE
A nm unit cell area [m 2 ]
c p specific heat capacity [J/(kg*K)]
g coefficient [L/min/cm 2 ]
h eff effective heat transfer coeff. [W/(m 2 *K)]
h nm unit cell heat transfer coefficient [W/(m 2 *K)]
HT heat transfer
k coefficient [-]
k v coefficient of flow [L/min]
n number of cold plates [-]
P cp cold plate pumping power [W]
P system total system pumping power [W]
total electrical processor power [W]
P el
Δp loop
Δp cp
Δp system
dp/dx
Q
rack cooling loop pressure drop [bar]
cold plate pressure drop [bar]
system pressure drop = Δploop + Δpcp [bar]
pressure gradient [Pa/m]
heat flow [W]
q
nm
unit cell heat flux [W/cm 2 ]
R fluid fluid resistance [kg/(s*m 4 )]
R conv convective thermal resistance [K*mm 2 /W]
R TIM thermal interface resistance [K*mm 2 /W]
T jmax maximal junction temperature [°C]
T fout fluid outlet temperature [K]
fluid inlet temperature [K]
T fin
ΔT fout-in
ΔT j
t nm
t Si
t TIM
V
fluid temp. difference from outlet to inlet [K]
T jmax - T jmin [K]
unit cell cavity height [mm]
silicon die thickness [mm]
bond-line thickness [mm]
cold plate volumetric flow rate [L/min]
V nm
unit cell volumetric flow rate [L/min]
V system
rack cooling loop vol. flow rate [L/min]
7-9 October 2009, Leuven, Belgium
Greek letters
ρ density of water [kg/m 3 ]
constants
h 0
p 0
reference heat transfer coefficient = 1 W/(m 2 *K)
reference pressure = 1bar
subscript/superscript
cp cold plate
el electrical
eff effective
j junction
fout-in fluid outlet minus inlet
fin fluid inlet
fout fluid outlet
loop server rack cooling loop
max maximal
m cell number in y-direction
n cell number in x-direction
ACKNOWLEDGMENT
We acknowledge Reto Wälchli, Urs Kloter, and Martin
Witzig for their technical contributions and John Magerlein
and Walter Riess for their continuous support.
REFERENCES
[1] J. Koomey, “Estimating Total Power Consumption by
Servers in the U.S. and the World”, A report by the Lawrence
Berkeley National Laboratory, February 2007, see http://
enterprise.amd.com/Downloads/svrpwrusecompletefinal.pdf.
[2] E. Colgan et al., “A Practical Implementation of Silicon
Microchannel Coolers for High Power Chips”, IEEE
Transactions on Components and Packaging Technologies, Vol.
30 No. 2., June 2007, pp. 218-225.
[3] T. Brunschwiler et al., “Towards Zero Emission Datacenters”,
IBM J. RES. & DEV., vol. 53 NO. 3 PAPER 11, 2009, see
http://www.research.ibm.com/journal/rd/533/brunschwiler.pdf
[4] H. Hamann et al., “Spatially-Resolved Imaging of
Microprocessor Power (SIMP): Hotspots in Microprocessors”,
Proc. 10th Intersociety Conf. on Thermal and Thermomechanical
Phenomena in Electronics Systems ITHERM 06, 30
May – 2 June, 2006, pp. 121-125.
©EDA Publishing/THERMINIC 2009 155
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[5] P. Lee and S. Garimella, “Hot-Spot Thermal Management with
Flow Modulation in a Microchannel Heat Sink”, Proc. of
IMECE2005 ASME, 5 – 11 November, 2005, Orlando, pp. 643-
647.
7-9 October 2009, Leuven, Belgium
[6] T. Brunschwiler et al., “Hotspot-Optimized Interlayer Cooling
in Vertically Integrated Packages”, Proc. MRS Fall Meeting
2008, 1 – 5 December, 2008, Orlando.
[7] J. Valenzuela et al., “Cooling High Heat Flux Devices with
Mikros”, Mikros Manufacturing Inc., White Paper,
http://www.mikrostechnologies.com.
[8] J. Schulz-Harder, “Efficient Cooling of Power Electronics”,
PCIM Conference, Shanghai, 2006, pp. 208-212.
[9] R. Wälchli et al., “Combined local microchannel-scale CFD
modeling and global chip scale network modeling for
electronics cooling design”, Int. Journal of Heat and Mass
Transfer, in press.
[10] T. Brunschwiler et al., “Direct Liquid-Jet Impingement Cooling
with Micron-Sized Nozzle Array and Distributed Return
Architecture”, Proc. ITHERM 2006, San Diego, CA, 196-203.
©EDA Publishing/THERMINIC 2009 156
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7-9 October 2009, Leuven, Belgium
Optimal Channel Width Distribution of Single-Phase
Microchannel Heat Sinks
T. Van Oevelen 1 , F. Rogiers, M. Baelmans
Katholieke Universiteit Leuven, Department of Mechanical Engineering,
Celestijnenlaan 300A, bus 2421
3001 Heverlee, Belgium
Abstract: The channel width distribution of single-phase
microchannel heat sinks is optimized based on 1D-modeling. Two
objectives are regarded, i.e. minimal thermal resistance and
minimal wall temperature gradient. The results differ significantly
from the present status in literature due to a new parameterization.
In addition the effects of axial conduction, fin width and pressure
drop are investigated.
Key words: microchannel, heat sink, optimal width distribution
I. INTRODUCTION
Single-phase microchannel heat sinks are considered as one
of the most promising cooling technologies to cope with the
increasing power densities in electronic chips. Hereby, a
cooling fluid flows through a large set of very small, parallel
channels in a heat sink mounted on the backside of the chip.
This provides a high surface area density and a high
convection heat transfer coefficient. As such, these systems
are capable of cooling large power densities, while keeping
the maximum chip temperature at an acceptable level.
Since the early work of Tuckerman and Pease [12] a lot of
optimization research has been conducted. Most authors used
analytical methods to search for the optimal width and/or
height of the microchannels ([3],[4],[5],[8],[11],[12]). Others
applied numerical optimization methods for this task
([2],[3],[9]), while some search for the optimum by scanning
the parameter field ([6],[7]).
Despite these efforts and the advantages of this cooling
technique, an important drawback of microchannel heat sinks
is still due to the fact that large temperature differences
between inlet and outlet regions may occur. This is caused by
a fluid temperature increase as it passes through the channels.
This phenomenon induces temperature gradients in the heat
sink and substrate, giving rise to thermal stresses.
Furthermore, since the maximum temperature occurs only at
the outlet of the channel, the substrate temperature in the
upstream part of the channel is generally far below this
maximum. As such, striving for higher wall temperatures in
this upstream part close to its maximal value yields a larger
effective temperature difference. This will facilitate heat
transfer. Therefore not exploiting this potential can be
considered as an unnecessary waste of performance.
Bau [1] presented a solution to exploit this potential by
introducing channels with a non-uniform cross-section. This
allows the entire channel width distribution to be optimized,
thereby increasing the number of degrees of freedom. It
appears that a reduction of the thermal resistance by 5%
compared to the uniform channels is possible. Also major
reductions in temperature gradients are shown.
The aim of this paper is to extend the analysis as presented
by Bau by introducing a more accurate parameterization of
the channel width distribution. This leads to a more detailed
description of optimal channel width distributions. As
objective, both minimal wall temperature gradient and
minimal thermal resistance are investigated. For the latter
objective, the effects of axial conduction are shown. Due to
the large number of design parameters, optimization is based
on numerical methods.
In the next section, two thermal-hydraulic models are
described: one with and one without axial conduction.
Subsequently, the objective functions and parameterization
are introduced. In section IV the optimization results are
presented and discussed, together with a sensitivity analysis
of fin width and pressure drop.
II.
MATHEMATICAL MODEL
The physics model that is used in this paper is a onedimensional
model, based upon integration of the flow and
heat transfer equations with respect to the cross-section of the
channels. A drawing of the channels cross-section is shown
in Fig. 1. In a real heat sink, this element can be repeated as
much as needed. The geometric variables of the cross-section
are also depicted in Fig. 1. The length of the channels is
denoted by L * . As a convention, dimensional variables are
marked with a star ‘*’, while dimensionless variables are not.
1 Corresponding author. Tel.: +32 16 322511; fax: +32 16 322985; email address: tijs.vanoevelen@mech.kuleuven.be
This work is sponsored by the IWT, The Institute for the Promotion of Innovation by Science and Technology in Flanders, Belgium, through project SBO 60830,
“HyperCool-IT”.
©EDA Publishing/THERMINIC 2009 157
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7-9 October 2009, Leuven, Belgium
For the simulation of global flow variables, the model from θ ( x)
and
s θ ( x)
are the non-dimensional solid and fluid
f
Bau is used, assuming fully developed laminar flow. This
temperatures; Nu ( α ) is the Nusselt number;
model calculates the non-dimensional mass flow rate m,
α
max
= maxα( x)
is
0≤x≤1
defined relative to the mass flow rate scale
* * * * *
m ( )
0
= hc Δp
ν L . the maximum aspect ratio of the channel; k s is the ratio
*
*
h is the channel’s height;
c
Δ p is the pressure drop over the
between the conductivity of solid and fluid k * s /k * f ; A s and A f
are the areas of the cross-sections of the solid and fluid
*
channels; ν is the kinematic viscosity of the coolant. The
*
region, non-dimensionalized with ( L ) 2
;
* * * *
χ = ( k
dimensionless mass flow m depends on the aspect ratio shape
f
L / c m
) with
0
profile
* *
α ( x ) = wc ( x) h c
along the channel:
c * the fluid heat capacity. The parameter χ is inverse
1
−1
*
proportional to
⎛ 1 (1 + α)²
⎞
Δ p .
m = ⎜ ( ) ⎟
8∫ Po α dx
(1)
³
The three terms in (3) represent respectively the heat
⎝ α
0 ⎠
source, the convective heat transfer from solid wall to the
*
Herein is Po (α ) the Poiseuille number and x = x * L is the coolant and axial conductive heat transfer in the solid wall.
In these equations –using
*'' * *
Q s
hc
k III. OPTIMIZATION PROCEDURE
f
The shape of the channels is optimized with respect to two
dimensionless axial coordinate. For the determination of the
Poiseuille number, following correlation for fully developed
flow is used [10] ( 0 ≤ α ≤1):
Similarly, the three terms in (4) represent convective heat
transfer from solid to coolant, the axial conductive heat
transfer in the coolant and the capacitive heating of the fluid.
2
3
Po ( α ) = 96(1 −1.3553α
+ 1.9467α
−1.7012α
(2)
A constant heat flux correlation for Nu ( α ) is used in the
4
5
+ 0.9564α
− 0.2537α
).
assumption of fully developed flow with three-wall heating
The simulation of the axial temperature profiles introduces [10] ( 0 ≤ α ≤1):
2
3
some differences with the model from Bau. In this model, Nu ( α ) = 8.235(1 −1.883α
+ 3.767α
− 5.814α
(5)
axial temperature distribution is calculated for both the fluid
4 5
+ 5.361α
− 2α
).
and the solid wall region including axial conduction. The set of modeling equations (3)-(4) is solved numerically
Therefore, a set of 2 dimensionless heat transfer equations – using finite volume discretization with appropriate boundary
one for each region– is introduced.
conditions. The fluid inlet has a specified temperature. The
The equation describing heat transfer in the solid wall is:
Nu
( )
( α )( 1+
α )( 2 + α ) fluid outlet and both ends of the solid wall have adiabatic
d ⎛ dθ
s ⎞
α
max
+ w
f
−
⋅ ( θ
s
−θ
f
) + ⎜ks
As
⎟ = 0 boundary conditions.
2α
dx ⎝ dx ⎠
If the axial conduction terms in (3)-(4) are ignored, the
(3) modeling equations of Bau are retrieved. It is recalled in (6):
The heat transfer in the fluid region is described by:
Nu( α )( 1 + α )( 2 + α ) ⎛ 2α
χ ⎞
θ
d ⎛ dθ
f ⎞ m dθ
s
( x)
= ( α + w ) ⎜
+ ⋅ x⎟ (6)
max f
f
⋅ ( θ
s
−θ
f
) + ⎜ A ⎟
f
= ⋅ (4)
⎝ Nu( α )( 1+
α )( 2 + α ) m ⎠
2α
dx
dx
⎝ ⎠ χ dx
objectives. The first objective J consists of the
1
minimization of the wall temperature gradient. This is
formulated as the Euclidian norm of the local wall
temperature gradient dθ s
(x)
:
dx
2
⎛ ⎞
= 1 dθ
s
J ∫ ⎜ ⎟ ( ) 0
⎝ dx
dx
α x ⎠
(7)
The second objective J that is regarded is the
2
minimization of the thermal resistance, which is defined as
the maximum dimensionless wall temperature along the
channel:
J = min maxθ
( )
s
α ( x)
x
(8)
The primary variable describing the shape of the channels
is the aspect ratio profile α (x), which is a dimensionless
representation of the channel width. This shape profile is in
fact a continuous function defined over the entire length of
the channel. Conventional optimization routines are only
suitable for a finite number of variables. Therefore a
Fig. 1: Schematic of the channels cross-section
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7-9 October 2009, Leuven, Belgium
parameterization of the shape is necessary. This is realized
by defining the shape on a number of equidistant locations
along the whole channel length. A piece-wise linear shape
profile is then assumed between these points. Thus,
intermediate values can be obtained by interpolation.
This method has the advantages that it resolves the profile
at a high spatial accuracy and that every variable has only
local influence on the shape. This is in contrast with the
parameterization that was used in [1], where the shape is
represented by a smooth quadratic polynomial function. The
coefficients of this polynomial were used as variables subject
to optimization. Every variable has therefore an influence
along the whole channel length. As we will show later on, the
thermal resistance minimization shows a non-smooth optimal
shape profile that cannot be captured by the parameterization
by [1].
The optimization problems (7) and (8) are solved
numerically using a conjugate gradient method.
IV.
RESULTS AND DISCUSSION
A. Minimal wall temperature gradient – minimization of J
1
Optimization of the microchannel heat sink is performed on
an illustrative case, using a channel height of 600 µm,
minimal fin width of 30 µm and chip length of 1 cm. The
pressure drop is fixed at 0.6 bar and water was used as a
coolant. Material properties are evaluated at 20 °C. This
gives rise to the following model parameters: w = 0. 05 and
f
−6
χ = 1.851⋅10
. The simplified model without axial
conduction (6) is used since in the optimum there is nearly no
axial temperature gradient and thus negligible axial
conduction. In addition this reduces the required
computational effort.
When optimizing with respect to a minimal temperature
gradient, using objective function J 1
, it is observed that a
unique solution does not exist in particular circumstances.
This occurs when the resulting shape has uniform wall
temperature, which is the absolute optimum. We will refer to
this later.
A similar observation was encountered in [1]. To
circumvent the non-uniqueness of the optimization problem,
Bau made a linear combination with the thermal resistance
objective function using a weighting factor. This
methodology resulted in a well-posed optimization problem,
but no justification on the choice of the weighting factor was
made.
In order to keep the distinction between the two objectives,
we perform the optimization in another way. In our research,
the inlet width and its corresponding aspect ratio α are set to
0
a fixed value. Since this value is directly related to the
resulting wall temperature, the optimal solution becomes
unique.
The results of this optimization are shown for 2 values of
the inlet aspect ratio α in Fig. 2. The top curves of the figure
0
show the dimensionless width distribution α (x), the bottom
curves show the dimensionless wall θ
s
( x)
and fluid θ
f
( x)
temperature profiles. These results reveal that it is possible to
reduce the temperature gradient to zero when the inlet width
is broad enough (e.g. corresponding to α = 0. 0
20 for this case,
indicated with solid lines). This is possible because the
increase of the capacitive thermal resistance with x:
⎛ χ ⎞
Rcap
( x)
= ( α + w
f
) ⎜ ⋅ x⎟ , (9)
max
⎝ m ⎠
is then fully compensated by the convective thermal
resistance:
⎛ 2α
( )
( )( )( ) ⎟ ⎞
R ( x)
= α
max
+ w ⎜
. (10)
conv
f
⎝ Nu α 1+
α 2 + α ⎠
Therefore R conv
(x)
must be a decreasing function.
A special property of the demoninator Nu ( α )( 1+ α )( 2 + α )
was furthermore observed. For 0 ≤ α ≤ 0. 4 , this group is
almost constant: 16.23±0.24. From (6), (9) and (10) it can
then be seen that the optimal shape profile α (x)
is a linear
decreasing function. Indeed since R cap
(x)
is a linear
increasing function, R conv
(x)
must be a linear decreasing
function with the opposite slope to result in a uniform wall
temperature. This is found from (6) with θ
s( x) = θ . From the
s
aforementioned property of Nu ( α )( 1+ α )( 2 + α ) and (10), it
follows that α (x)
decreases linearly with x.
However, a uniform wall temperature cannot be obtained
for channels with too small inlets (e.g. α = 0. 0
16 for this case,
indicated with dot-dashed lines). With small inlets there is
too much restriction of the flow, resulting in a low mass flow
rate. Therefore R cap
(x)
would become very high, making it
impossible to compensate with R conv
(x)
. The increased slope
Fig. 2: Optimal channel shape and wall temperature profiles w.r.t.
objective J for 2 values of
1
α .
0
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of the fluid temperature profile in Fig. 2 is due to a reduced
mass flow rate.
B. Minimal thermal resistance – minimization of J
2
The same case as in A was considered for optimizing the
thermal resistance, using objective function J . When axial
2
conduction was modeled, the following parameters were
used: heat conductivity ratio between solid and fluid
k
s
= 241.4 , ratio of total height to channel height h
t
= 1. 5 and
ratio of length to channel height L = 16. 7 . Fig. 3 shows the
results for three different optimization settings. In the first
setting, a uniform channel is optimized to allow comparison.
The second and third setting concern the optimization of a
non-uniform channel using respectively a model without and
with axial conduction. The top of the figure shows the
optimal width distribution in each of the three cases; the
bottom shows the accompanying wall temperature profiles.
Unexpectedly, the optimal non-uniform channel appears to
have two distinct parts. The first part of the channel has a
uniform width and thus an increasing wall temperature. The
second part is similar to the profile observed in subsection A:
the width is decreasing to keep the wall temperature at a
uniform level. Again the decrease in width towards the end
of the channel improves the local convective heat transfer,
thereby preventing the maximal wall temperature from
getting too high. At first sight, it seems suboptimal that this
trend does not fully continue towards the beginning of the
channel. Not all potential of pushing the wall temperature
against the maximum is being used. However would this
trend continue, the inlet width of the channel would become
very broad. This would make α max
and thus the total width
very large, thereby increasing the amount of heat that each
single channel of the cooler has to get rid of. Equation (6)
incorporates this effect.
The first part of the resulting profile therefore stems from a
trade-off between enlarging α to allow more mass flow and
reducing α to reduce the heat load of a single channel. It is
logical that this results in a part with uniform width. Indeed,
only the maximal width has an influence on the channel
density. This is similar to what happens in the second part.
Here, the trade-off is between a large α to increase mass flow
and a low α to increase the convective heat transfer.
In the last optimization setting, the effect of axial
conduction is investigated. This introduced only a minor
difference in the channel shape. At the breakpoint between
the two lines, a truncated peak is added to compensate for the
flattening of the wall temperature profile due to the axial
conduction.
Table I presents a comparison between the three obtained
shapes in terms of their thermal resistance. The table also
shows the inlet and outlet widths of the optimized channel in
each of the cases. It is obvious that using the most accurate
model including axial conduction and the largest number of
degrees of freedom (for a non-uniform channel) gives the best
result. We see however that the improvement compared to
the model without axial conduction is negligible. Therefore,
taking into account practical considerations such as
computational effort etc., leads to the conclusion that the
optimization with a model without axial conduction will lead
to sufficiently accurate results for technical implementation.
C. Parameter sensitivity analysis
The main model parameters determining the solution are
the dimensionless quantities w and χ . The influence of both
f
parameters on the optimal result was investigated by scanning
the parameter field, for both objectives J and
1
J .
2
One can see from Fig. 1 that w has an influence on the
f
density of the channels only. This characterizes the amount
of heat to be cooled by a single channel. An increase in w
f
will result in a larger total width, thereby reducing the density
of the channels and a corresponding increase in heat transfer
to each individual channel.
For objective J 1
, we observe that
w does not have any
f
, at least when the inlet
effect on the width distribution α (x)
width is wide enough to allow a uniform wall temperature
profile. It can be easily seen from (6) that w f
does not
influence the temperature gradient if this is already zero.
There is off course an effect on the actual level of the wall
temperature, which increases when w increases.
f
Fig. 3: Optimal channel shape and wall temperature profiles w.r.t.
objective J for 3 different optimization settings.
2
TABLE I
COMPARISON OF 3 SHAPES OPTIMIZED FOR THERMAL RESISTANCE
Optimization setting α0
α
e θ max (10 -3 )
s
∆ (10 -3 ) / %
Uniform channel 0.1253 0.1253 4.806 - / -
No axial conduction 0.1313 0.0979 4.511 0.295 / 6.1 %
Axial conduction 0.1319 0.0980 4.508 0.298 / 6.2 %
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Fig. 4: The effect of
w on the optimal channel shape w.r.t.
f
J .
2
The effect on the result of objective J is more
2
complicated, as can be seen from Fig. 4. An increase of w
f
has the effect of increasing the channel’s heat load. This
shifts the balance between mass flow and total width as
already explained in subsection B, towards a larger width
distribution. Doing so, the increase in thermal resistance is
tempered.
The effect of the dimensionless quantity χ can be most
easily understood by recalling that it is inverse proportional to
the frictional pressure drop over the channels. We can
therefore understand that an increase in χ will have a
negative effect on the mass flow rate through the channels.
This will furthermore increase the slope of the capacitive
thermal resistance R cap
(x)
, which can also be seen from (9).
Fig. 5 shows the effect of χ on the optimization problem
J . This figure again shows that
1
J 1
has a dual behaviour.
The optimization was performed for a number of values for χ
with the fixed inlet width of α = 0. 0
2 . For low values of χ ,
*
when Δ p is high enough, it is possible to obtain shapes with
a uniform wall temperature. As shown earlier, this gives rise
to a linear decreasing width profile α (x). The increase in the
slope of R cap
(x)
is counteracted by an increase in (negative)
slope from α (x), to keep the wall temperature uniform.
These cases are drawn with solid lines.
*
However when χ becomes too high –or equivalently Δ p
too low– the mass flow rate is so low that a uniform wall
temperature can no longer be achieved. This has the same
reasoning as before when we showed that a uniform wall
temperature profile is not possible for too small inlets. These
cases are drawn with dashed lines. In this regime, the channel
width increases with χ , so that m increases to compensate the
increase in χ .
Fig. 6 shows that increasing values of χ , i.e. decreasing
pressure drop, result in broader width profiles. This measure
serves as a way to temper the decrease in mass flow rate by
using larger channels, which have less friction.
V. CONCLUSION
A 1D-model for the simulation of wall and fluid
temperatures in a microchannel heat sink was presented,
including axial conduction. The width distribution of this
microchannel was optimized for two objectives, i.e. minimal
wall temperature gradient ( J 1
) and minimal thermal resistance
( J ).
2
With the wall temperature gradient objective it was found
that a fully uniform wall temperature profile is achievable if
the inlet width is large enough. The results for the thermal
resistance objective are found to consist of two parts: one
representing a bound on the aspect ratio, the other
representing a bound on the wall temperature. By using the
full model (3)-(4) in the optimization, the best performance
was obtained, with an improvement of 6.2% compared to an
optimal uniform channel.
Fig. 5: The effect of χ on the optimal channel w.r.t. J .
1
(Low χ : solid line / High χ : dashed line)
Fig. 6: The effect of χ on the optimal channel shape w.r.t.
J .
2
©EDA Publishing/THERMINIC 2009 161
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In contrast to earlier results presented in [1], the new
parameterization reveals non-smooth results. Furthermore,
sensitivities of these optimization results with respect to the
fin width w f
and inverse pressure drop number χ were
discussed.
REFERENCES
[1] H. H. Bau, “Optimization of conduits’ shape in micro heat
exchangers,” Int. Journal of Heat and Mass Transfer, vol. 41, pp.
2717-2723, 1998.
[2] A. Husain, K.-Y. Kim, “Optimization of a microchannel heat sink
with temperature dependent fluid properties,” Applied Thermal
Engineering, vol. 28, pp. 1101-1107, 2008.
[3] S. J. Kim, “Methods for thermal optimization of microchannel
heat sinks,” Heat Transfer Engineering, vol. 25, no. 1, pp. 37-49,
2004.
[4] R. W. Knight, J. S. Goodling, and D. J. Hall, “Optimal thermal
design of forced convection heat sinks-analytical,” Journal of
Electronic Packaging, vol. 113, pp. 313-321, 1991.
[5] R. W. Knight, D. J. Hall, J. S. Goodling, and R. C. Jaeger, “Heat
sink optimization with application to microchannels,” IEEE
Trans. on Components, Hybrids and Manufacturing Technology,
vol. 15, no. 5, pp. 832-842, October 1992.
[6] H.-S. Kou, J.-J. Lee, and C.-W. Chen, “Optimum thermal
performance of microchannel heat sink by adjusting channel
width and height,” Int. Communications in Heat and Mass
Transfer, vol. 35, pp. 577-582, 2008.
[7] J. Li, G. P. Peterson, “Geometric optimization of a micro heat sink
with liquid flow,” IEEE Trans. on Components and Packaging
Technologies, vol. 29, no. 1, March 2006.
[8] D. Liu, S. V. Garimella, “Analysis and optimization of the
thermal performance of microchannel heat sinks,” Int. Journal for
Numerical Methods in Heat & Fluid Flow, vol. 15, no. 1, pp. 7-
26, 2005.
[9] J. H. Ryu, D. H. Choi, and S. J. Kim, “Numerical optimization of
the thermal performance of a microchannel heat sink,” Int.
Journal of Heat and Mass Transfer, vol. 45, pp. 2823-2827, 2002.
[10] R. K. Shah, A. L. London, “Laminar flow forced convection in
ducts,” Advances in heat transfer, supplement 1, Academic press,
1978.
[11] T. Stevens, F. Rogiers, M. Baelmans, “Optimization of microchannel
heat sink geometry”, Proceedings of the 13 th International
Heat Transfer Conference, Sidney, Australia, August 13-18, 2006.
[12] D. B. Tuckerman, R.F. W. Pease, “High-performance heat sinking
for VLSI,” IEEE Electron. Device letters, vol. 2, no. 5, pp. 126-
129, May 1982.
7-9 October 2009, Leuven, Belgium
©EDA Publishing/THERMINIC 2009 162
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7-9 October 2009, Leuven, Belgium
Heat transfer enhancement due to pulsating flow
in a microchannel heat sink
T. Persoons * , T. Saenen, R. Donose, M. Baelmans
Katholieke Universiteit Leuven, Department of Mechanical Engineering (TME)
Celestijnenlaan 300A, P.O. box 2421, 3001 Leuven, Belgium
Abstract – Heat sinks with liquid forced convection in
microchannels are targeted for cooling microelectronic devices
with a high dissipated power density. Given the inherent
stability problems associated with two-phase microchannel heat
transfer, this paper investigates experimentally the potential for
enhancing single-phase convection cooling rates by applying
pulsating flow. To this end, a pulsator device is developed
which allows independent continuous control of pulsation
amplitude and frequency. For a single microchannel geometry
and a range of parameters (steady and pulsating Reynolds
number, Womersley number), experimental results are
presented for the overall heat transfer enhancement compared
to the steady flow case. Enhancement factors up to 40% are
observed for the investigated parameter range (50 < Re < 400,
35 < Re p < 225, 2 < Wo < 17).
Key words – Pulsating flow; single-phase heat transfer
enhancement; boundary layer redevelopment
I. INTRODUCTION
Heat exchangers with microchannels are targeted for high
heat flux applications such as microelectronics cooling [1].
Research attention is divided between operation in single
and two-phase flow. Due to the high boiling heat transfer
rates, two-phase systems are considered the most promising
technique for high-end microelectronics cooling [1].
Single phase flow in microchannels remains an active
research area [2], also since micro scale two-phase flow is
characterised by stability problems. In a microchannel (with
hydraulic diameter of a few 100 μm) the Reynolds number
typically ranges from 100 to 1000. In these conditions,
nucleate boiling is the dominant heat transfer mode. This
regime is characterised by a high wall superheat which
causes rapid evaporation and bubble growth after nucleation.
The sudden volume expansion disturbs the microchannel
flow and may cause flow reversal [3].
Different regimes have been identified in two-phase
microchannel flow using water and other working media
[4,5]. Depending on the heat and mass flux conditions,
irregular transitions occur between single-phase liquid and
two-phase liquid/vapour flow in various modes (e.g. bubble,
slug, annular flow) and pure vapour flow (i.e. dry-out),
causing sudden excessive peak wall temperatures [4].
These studies [3-5] illustrate the stability problems in twophase
flow in microchannels, even when applying an ideal
uniform heating load. In reality, high-end microelectronics
are characterised by strongly non-uniform heating, which
aggravates the instability and the risk for periodic dry-out
and related damage to the electronics [6].
Although some researchers are striving to stabilise twophase
operation using flow restrictions and artificial
nucleation sites [7], alternatives are also being investigated
to enhance the cooling performance of single-phase systems.
When superimposing pulsation on a steady channel flow,
the hydrodynamic and thermal boundary layers are affected,
which in turn affects the overall convective heat transfer
rate. Some analytical studies of laminar pulsating flow show
a frequency-dependent influence on the heat transfer
compared to steady flow, yet overall the effect on the
average heat transfer rate is found to be negligible [8,9].
However, some numerical and experimental studies found
enhancement factors of up to 11% for laminar and 9% for
turbulent pulsating flow [10,11] in smooth channels.
Some recent experimental heat and mass transfer studies
using pulsating flow in channels with cross-stream ribbed
walls report enhancement factors of 100% up to 250%
compared to steady flow [12,13]. The enhancement is more
pronounced in laminar compared to turbulent flow, and
increases with Prandtl number [14].
Impinging jets are another configuration where the effect
of flow pulsation on the heat transfer enhancement has been
investigated. Using synthetic jets (zero net mass flux), heat
transfer rates comparable to steady impinging jets have been
obtained [15-17].
Given the encouraging findings in similar applications,
this paper aims to determine experimentally the potential for
heat transfer enhancement using pulsating flow in a
microchannel heat sink in single-phase operation. This study
uses a single rectangular channel to serve as a reference case
for subsequent studies using pulsating flow in parallel
microchannels.
II. EXPERIMENTAL APPROACH
Microchannel heat sink and flow loop
This reference case heat sink contains a single rectangular
channel milled in an aluminium base (Fig. 1). The channel is
H = 1 mm deep, W = 16 mm wide and L = 32 mm long. The
channel is covered by an aluminium plate with fluidic
connections on either side (4 mm internal diameter).
The heat sink is bonded with thermal paste (10 W/(mK))
to a copper block with embedded cartridge heater (up to
40 W/cm 2 ). Based on a thermocouple measurement on the
block and heat sink cover, the channel wall temperature T w is
estimated using a lumped resistance model.
* Corresponding author: tel +32 16 322546, fax +32 16 322985, email: tim.persoons@mech.kuleuven.be
Present address: Mechanical Engineering dept., Parsons Building, Trinity College, Dublin 2, Ireland (tim.persoons@tcd.ie)
©EDA Publishing/THERMINIC 2009 163
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7-9 October 2009, Leuven, Belgium
(a) (b) (c) (b) (a)
Fig. 1. Microchannel heat sink ((1) aluminium cover plate with fluidic
connections, (2) aluminium channel plate, (3) insulated heater block).
Pulsator
Microchannel
heat sink
p,T
p,T
Fig. 3. Pulsator for generating pulsating flow component with adjustable
amplitude and frequency; (a) manifolds with check valves, (b) two pumping
chambers with opposite phase, (c) piezoceramic actuator disk.
Cooler
Mass flow
meter
Pump
Fig. 2. Microchannel heat sink test facility with pulsating flow device.
Inlet and outlets with pressure and temperature taps are
connected to a flow loop, driven by a variable speed gear
pump (Fig. 2). A Coriolis flow meter (Bronkhorst CORI-
FLOW, 50 kg/h) is used as mass flow measurement. The
water temperature is kept constant during testing using a 2
litre reservoir at atmospheric pressure and a fan-driven platefin
heat exchanger as cooling section.
Pulsating flow generator
A pulsating velocity component of continuously
adjustable amplitude and frequency is generated using an
inline pulsator device. The pulsator consists of a miniature
membrane pump with two pumping chambers in opposite
phase (Fig. 3), driven by a piezoelectric bending disk
actuator. Fast acting check valves ensure the oscillating flow
component is restricted to the heat sink test section (see Fig.
2).
Its operating range covers frequencies from 0 to over
1000 Hz, with maximum displacement of 10 mm 3 per stroke.
At 50 Hz, this yields a pulsating velocity amplitude up to U p
= 0.2 m/s (Re p ≅ 500) in this microchannel heat sink
geometry.
The pulsator does not yet contain a fast-response sensor to
monitor the displaced volume or pressure. As such, the
resulting pulsating velocity amplitude is estimated based on
the applied actuator voltage, neglecting the dynamics of the
inertia of accelerating fluid and pump shaft, membrane
stiffness and viscous damping. A displacement sensor will
be incorporated shortly however for the results in this paper,
the values of Re p are likely to exhibit some overestimation at
higher frequency. As such, the frequency range has been
limited between 0 and 40 Hz.
The Womersley number, a dimensionless frequency in
pulsating channel flow, is defined as Wo = ½D h (2πf/ν) 1/2 ,
where f is the pulsation frequency and ν is the kinematic
viscosity. The objective of the study is to match the
Womersley number range of other studies [9-11], with a
typical maximum of Wo = 10. Here, a frequency range of 0
to 40 Hz corresponds to a range in Wo between 0 and 17.
III. DISCUSSION OF HEAT TRANSFER RESULTS
The heat transfer is quantified by the heat transfer
coefficient h defined as q/ΔT lm where q is the surface heat
flux. The logarithmic mean temperature difference ΔT lm is
defined as
( Tw −To) −( Tw −Ti)
Δ Tlm
=
(1)
log (( Tw −To) ( Tw −Ti)
)
where T i and T o are the inlet and outlet mean fluid
temperature respectively. The wall surface temperature T w is
estimated based on a lumped resistance model as described
above. The Nusselt number is defined as Nu = hD h /k, where
k is the thermal conductivity of water at the mean fluid
temperature.
Steady flow
Experimental heat transfer results for steady flow are
presented in Fig. 4. In the Reynolds number range under
investigation (50 < Re < 500), the heat sink length L (32
mm) is shorter than the thermal entrance length (L < 0.04 D h
Re Pr). As such, Fig. 4 also presents some existing
correlations established for thermally developing flow
between parallel plates [18-20]. In Fig. 4, the labels Nu q and
Nu T indicate whether the correlation is valid for constant
wall heat flux or temperature respectively.
The heat transfer results for this heat sink are considerably
higher than the parallel plate correlations. This can be
attributed to the collector geometry (see Fig. 1), which does
not provide a smooth transition for the flow into the channel.
Furthermore, the heat is supplied to only one side of the
channel, although via conduction within the heat sink walls a
fraction of the heat can also be transferred into the flow from
the non-heated side.
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10 2 (L/D h /(ReP r)) 1/2
20
15
Shah & London 1978 (Nu q )
Shah & London 1978 (Nu T )
Stephan 1959 (Nu T )
Edwards et al. 1979 (Nu T )
fitted correlation (R 2 = 0.995)
Nu
10
Shah & London 1978 (Nu q )
5
Shah & London 1978 (Nu T )
Stephan 1959 (Nu T )
Edwards et al. 1979 (Nu T )
fitted correlation (R 2 = 0.995)
0
0 100 200 300 400 500
Re
Fig. 4. Heat transfer results for steady flow through the heat sink, compared
to existing heat transfer correlations for developing thermal and hydraulic
boundary layers between parallel plates. Circular markers are experimental
results, fitted with correlation described in Eq. (2).
This conjugate heat transfer problem is too complex to
compare quantitatively to the simple cases of the established
correlations [18-20]. Nevertheless, the same functional form
of the correlation established by Edwards et al. [20] is used
in Fig. 4 to fit the experimental data:
−1 −2 3
⎛LD
⎞ ⎛ ⎛ ⎞ ⎞
h
LDh
Nu = a+ b⎜ ⎟ 1+
c
⎜ ⎜ ⎟
⎝Re Pr ⎠ ⎝ ⎠
⎟
(2)
⎝ Re Pr
⎠
where a = 7.5, b = 0.265, c = 0.0661 (R 2 = 0.995).
Figure 5 shows the same data presented differently, as a
function of the dimensionless entrance length L/D h /(Re.Pr)
as is typical of correlations for thermally developing flow.
Pulsating flow
The results for pulsating flow have been analysed as
dimensionless heat transfer enhancement factors, i.e. the
ratio of the increase of the averaged heat transfer coefficient
in pulsating flow with respect to the steady flow case at the
same steady Reynolds number Re s , or
Nu
p
− Nus
δ Nu =
(3)
Nus
where the subscripts s and p denote steady and pulsating
flow respectively. The steady heat transfer coefficient Nu s is
evaluated from Re s using the correlation given in Eq. (2).
Figure 6 shows the enhancement factors for a range of 50
< Re (= Re s ) < 400 and 35 < Re p < 225. The results show a
higher enhancement for higher pulsation amplitude, and a
tendency to peak at a low steady flow rate. This is not
unexpected, given the definition of the enhancement factor
in Eq. (3), comparing the increase in heat transfer coefficient
to the heat transfer coefficient in steady flow Nu s .
Nu
10 1
Fig 5. Identical to Fig. 4, yet plotted as a function of dimensionless thermal
entrance length.
Figures 7 and 8 present the same data in a different form,
as a function of the ratio of pulsating to steady flow
component Re p /Re. This was found to be the best form to
collapse the heat transfer enhancement factor results. For all
practical purposes, the remaining scatter in the data points in
Figs. 7 and 8 is considered within the uncertainty margins.
For now, the main contribution to the uncertainty is in the
pulsating flow magnitude, thus the value of Re p .
δNu
10 2 10 1 10 0
0.5
0.4
0.3
0.2
0.1
Re p =35
Re p =60
Re p =75
Re p = 115
Re p = 150
Re p = 225
0
0 100 200 300 400 500
Re
Fig. 6. Dimensionless heat transfer enhancement for pulsating flow through
the heat sink as a function of the steady flow Reynolds number Re (=Re s ).
Markers indicate different values of the pulsating Reynolds number Re p .
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0.5
0.4
δNu =0.18(Re p /Re) 0.7
(R 2 = 0.696)
0.5
δNu =0.18(Re p /Re) 0.7
(R 2 = 0.696)
0.2
δNu
0.3
0.2
δNu
0.1
0.02
0.1
0
0
0.05
0 0.5 1 1.5 2 2.5 3
Re p /Re
Fig. 7. Dimensionless heat transfer enhancement for pulsating flow through
the heat sink as a function of the ratio of pulsating to steady flow
component Re p /Re. Markers indicate the entire set of measurements for 35 <
Re p < 225. Solid line indicates correlation in Eq. (4).
The enhancement factors collapse satisfactorily when
plotted versus Re p /Re. Besides the ratio Re p /Re, other
dimensionless quantities and combinations have been
explored to better collapse the results, e.g. dimensionless
stroke length or Womersley number Wo. However none
seemed to outperform the ratio Re p /Re.
Figure 7 shows the following power law correlation fitted
to the entire set of experimental results for pulsating flow:
0.7
⎛Re p ⎞
δ Nu = 0.18⎜ ⎟ (R 2 = 0.696) (4)
⎝ Re ⎠
The above expression provides an adequate fit which at least
shows the existence of a trend, however does not seem
accurate enough to use as a prediction.
Moreover, when plotting the same results on a nonlinear
scale as in Fig. 8, a significantly different behaviour
becomes apparent for a low and high ratio of pulsating to
steady flow. Within the investigated range (0.09 < Re p /Re <
4.4) and for increasing pulsating flow magnitude, the
enhancement is first slightly negative albeit only a few
percent. In this regime, pulsating flow seems to decrease
cooling performance in this heat sink. Beyond Re p /Re > 0.2,
the enhancement is positive and increases with Re p /Re. Only
in this region does the correlation in Eq. (4) predict the
experimental results with an acceptable degree of accuracy.
The negligible enhancement or even slight deterioration of
heat transfer for small pulsation amplitudes (Re p /Re < 0.2)
reminds of findings by other authors [8,9], although the
present case with an actual heat sink geometry (including
conjugate heat transfer, hydraulically and thermally
developing laminar flow) is difficult to compare to the cases
presented in the literature.
0.02
0.05
0 0.05 0.2 0.5 1 2 3
Re p /Re
Fig. 8. Identical to Fig. 7, yet with nonlinear plot scaling to reveal different
behaviour at low and high pulsation magnitude Re p /Re.
IV. CONCLUSIONS
This paper has shown the potential for overall heat transfer
rate enhancement using pulsating flow in single-phase liquid
flow heat sink, for use in microelectronics cooling.
This initial study uses a single rectangular channel serving
as a reference case for subsequent studies of pulsating flow
in parallel microchannels.
Further improvements to the pulsating flow generator
should significantly narrow the uncertainty margins on the
parameters e.g. stroke length and pulsating Reynolds number
Re p . Nevertheless by limiting the actuation frequency in this
study, the results are deemed sufficiently reliable.
For the investigated range (50 < Re < 400, 35 < Re p < 225,
2 < Wo < 17), an enhancement factor of up to 40% is
observed with respect to steady flow heat transfer at the
same steady flow component.
The data show a consistent trend for heat transfer
enhancement as a function of the ratio of the pulsating to
steady flow component Re p /Re. For small pulsation
amplitude (Re p /Re < 0.2) a negligible yet slightly negative
enhancement is observed. For larger pulsation amplitudes
(Re p /Re > 0.2), the heat transfer enhancement increases with
Re p /Re and can be predicted (yet with limited accuracy) by
the power law expression in Eq. (4).
ACKNOWLEDGMENTS
This work is sponsored by the Institute for the promotion
of Innovation by Science and Technology in Flanders (IWT),
project SBO 60830 “HyperCool-IT”, as well as travel
funding by Research Foundation Flanders (FWO). The
authors explicitly thank Dr. Suresh V. Garimella, Benjamin
J. Jones and Tannaz Harirchian from Purdue University,
West Lafayette, In. for helpful discussions on this topic.
©EDA Publishing/THERMINIC 2009 166
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7-9 October 2009, Leuven, Belgium
NOMENCLATURE
D h channel hydraulic diameter (m)
f
flow pulsation frequency (Hz)
h
heat transfer coefficient, q/ΔT lm (W/(m 2 K))
H channel depth (m)
k
thermal conductivity of water (W/(mK))
L channel length (m)
Nu Nusselt number, h D h /k
δNu relative heat transfer enhancement, (Nu p -Nu s )/Nu s
Pr Prandtl number, ν/α
q surface heat flux (W/m 2 )
Re Reynolds number, U D h /ν
Re p pulsating Reynolds number, U p D h /ν
T i water inlet mean temperature (°C)
T o water outlet mean temperature (°C)
T w channel wall temperature (°C)
logarithmic mean temperature difference,
ΔT lm
( Tw −To) −( Tw −Ti)
(°C)
log (( T −T ) ( T −T)
)
w o w i
U mean channel steady velocity component (m/s)
U p mean channel pulsating velocity amplitude (m/s)
W channel width (m)
Wo Womersley number, ½D h (2πf/ν) 1/2
Greek symbols
α thermal diffusivity (m 2 /s)
ν
kinematic viscosity (m 2 /s)
Subscripts
p
q
s
T
pulsating flow component
constant wall heat flux
steady flow component
constant wall temperature
REFERENCES
[1] B. Agostini, M. Fabbri, J.E. Park, L. Wojtan, J.R. Thome, B. Michel,
“State of the art of high heat flux cooling technologies,” Heat Transfer
Eng., vol. 28 (4), pp. 258-281, 2007.
[2] P.S. Lee, S. V. Garimella, D. Liu, “Investigation of heat transfer in
rectangular microchannels,” Int. J. Heat Mass Transfer, vol. 48 (9), pp.
1688-1704, 2005.
[3] S. G. Kandlikar, “Heat transfer mechanisms during flow boiling in
microchannels,” J. Heat Transfer-Trans. ASME, vol. 126 (1), pp. 8-16,
2004.
[4] H.Y. Wu, P. Cheng, “Boiling instability in parallel silicon
microchannels at different heat flux,” Int. J. Heat Mass Transfer, vol.
47 (17-18), pp. 3631-3641, 2004.
[5] G. Hetsroni, A. Mosyak, Z. Segal, G. Ziskind, “A uniform temperature
heat sink for cooling of electronic devices,” Int. J. Heat Mass Transfer,
vol. 45 (16), pp. 3275-3286, 2002.
[6] G. Hetsroni, A. Mosyak, Z. Segal, “Nonuniform temperature
distribution in electronic devices cooled by flow in parallel
microchannels,” IEEE Trans. Components Packaging Technol., vol.
24 (1), pp. 16-23, 2001.
[7] S.G. Kandlikar, W.K. Kuan, D.A. Willistein, J. Borrelli, “Stabilization
of flow boiling in microchannels using pressure drop elements and
fabricated nucleation sites,” J. Heat Transfer-Trans. ASME, vol. 128
(4), pp. 389-396, 2006.
[8] T. Moschandreou, M. Zamir, “Heat transfer in a tube with pulsating
flow and constant heat flux,” Int. J. Heat Mass Transfer, vol. 40 (10),
pp. 2461-2466, 1997.
[9] H.N. Hemida, M.N. Sabry, A. Abdel-Rahim, H. Mansour, “Theoretical
analysis of heat transfer in laminar pulsating flow,” Int. J. Heat Mass
Transfer, vol. 45 (8), pp. 1767-1780, 2002.
[10] O.I. Craciunescu, S.T. Clegg, “Pulsatile blood flow effects on
temperature distribution and heat transfer in rigid vessels,” J. Biomech.
Eng.-Trans. ASME, vol. 123 (5), pp. 500-505, 2001.
[11] E.A.M. Elshafei, M.S. Mohamed, H. Mansour, M. Sakr,
“Experimental study of heat transfer in pulsating turbulent flow in a
pipe,” Int. J. Heat Fluid Flow, vol. 29 (4), pp. 1029-1038, 2008.
[12] T. Nishimura, N. Oka, Y. Yoshinaka, K. Kunitsugu, “Influence of
imposed oscillatory frequency on mass transfer enhancement of
grooved channels for pulsatile flow,” Int. J. Heat Mass Transfer, vol.
43 (13), pp. 2365-2374, 2000.
[13] B. Olayiwola, P. Walzel, “Cross-flow transport and heat transfer
enhancement in laminar pulsed flow,” Chem. Eng. Proc., vol. 47 (5),
pp. 929-937, 2008.
[14] B. Olayiwola, P. Walzel, “Experimental investigation of the effects of
fluid properties and geometry on forced convection in finned ducts
with flow pulsation,” J. Heat Transfer-Trans. ASME, vol. 131 (5),
051701, 2009.
[15] A. Pavlova, M. Amitay, “Electronic cooling using synthetic jet
impingement,” J. Heat Transfer-Trans. ASME, vol. 128 (9), pp. 897-
907, 2006.
[16] P. Valiorgue, T. Persoons, A. McGuinn, D.B. Murray, “Heat transfer
mechanisms in an impinging synthetic jet for a small jet-to-surface
spacing,” Exp. Therm. Fluid Sci., vol. 33 (4), pp. 597-603, 2009.
[17] T. Persoons, T.S. O'Donovan, D.B. Murray, “Heat transfer in adjacent
interacting impinging synthetic jets,” Proc. ASME Summer Heat
Transfer Conf., San Francisco (CA), 19-23 Jul 2009
[18] R.K. Shah, A.L. London, “Laminar flow forced convection in ducts”,
Suppl. to Adv. Heat Transfer, New York: Academic Press, 1978.
[19] K. Stephan, “Wärmeübertragang und Druckabfall beinichtausgebildeter
Laminarströmung in Röhren und in ebenen Spalten”, Chem.
Ing. Tech., 31, 773-778, 1959.
[20] D.K. Edwards, V.E. Denny, A.F. Mills, Transfer processes. 2nd Ed.
Washington, DC: Hemisphere, 1979.
©EDA Publishing/THERMINIC 2009 167
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7-9 October 2009, Leuven, Belgium
Hot Spot Targeting with a Liquid Impinging
Jet Array Waterblock
D. Nikolić, M. Hutchison, P.T. Sapin, A.J. Robinson
Department of Mechanical & Manufacturing Engineering
Trinity College Dublin
Dublin 2, Ireland
Abstract-Liquid cooling of electronic devices is widely
accepted as the next logical step for electronics thermal
management as board level air cooling becomes insufficient to
meet the needs of next generation components and devices. One
promising technology is liquid jet array impingement as it can
achieve exceptionally high area averaged heat transfer
coefficients. In this work the use of arrays of liquid impinging
jets in a waterblock configuration is posed as one possible
technology for on-chip hot spot targeting. A simple test case is
posed and an optimization strategy is employed to distribute
jets in the hot spot and outer regions differently in order to
reduce the maximum temperature difference and/or the root
mean squared deviation of the temperature on the chip. It is
concluded that with a priori knowledge of the heat flux
distribution on-chip, this method of hot spot targeting offers an
uncomplicated and potentially cost effective means of bulk
cooling and temperature homogenization.
I. INTRODUCTION
The increase in device density and clock speeds in
electronic components and devices has led to escalating
demand for dissipation of the waste heat generated by the
active devices. In many applications the power densities far
exceed the capabilities of conventional low-tech fan-finned
heat sinks. This is due to several constraining issues which
includes, but is not limited to, fin efficiency, fan acoustic
emissions, fan power consumption and electronic
packaging/miniaturization issues. A further issue is that
devices operating at moderate overall power can in some
cases generate local hot spots with power densities in the
order of kW/cm 2 [1]. For example, Figure 1 shows a thermal
image of hot spots generated on a Pentium 4 2.8GHz in a
desktop PC. To obtain this image a purpose built liquid
cooler was fabricated in which the CPU is cooled by IR
transparent oil (Fluka 69808) flowing within a 1.0 mm
channel sandwiched between the CPU and a ZnSe IR
transparent window and IR images were collected with a
FLIR 840 thermal imaging camera. For this case and others,
if adequate thermal management is not provided, premature
device failure can be expected either by direct failure of the
semiconductor or more likely by progressive accumulation
of thermomechanical damage and eventual cracking of
interconnect structures [1].
Active liquid cooling shows very good potential for
electronics thermal management of next generation
electronic components. In particular, microfluidic devices
such as microchannels and microjets can achieve exceptional
overall heat transfer coefficients with very low energy
consumption [2]. A very attractive benefit of liquid cooling
is that if it is deployed in large numbers such as may be
required for data centres, the heat energy, now stored in a
liquid opposed to air, can easily be reused (e.g. for space or
process heating), which reduces the overall combined energy
consumption and carbon footprint of the scenarios.
As noted by Robinson [2] microjet arrays can provide
exceptional temperature uniformity whereas microchannels
are at a disadvantage on this point due to the singular
direction of the microchannel flow which can cause large
axial temperature gradients. Another beneficial aspect of
impinging jets is that the jet orifices can be arranged
strategically to concentrate jets in areas of high local heat
flux which makes them ideal for hot spot targeting whereas
microchannels are a more global cooling strategy.
Fig. 1. Top: Thermal image of hot spot generated on the CPU of a
conventional desktop PC. Bottom: IR transparent liquid
minichannel heat sink.
©EDA Publishing/THERMINIC 2009 168
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In this work, the Nusselt number correlation recently
developed by Robinson and Schnitzler [3] is implemented to
investigate the feasibility of hot spot targeting using
submerged liquid jet arrays. The case under consideration is
a waterblock heat sink opposed to direct liquid cooling. A
waterblock-type of heat sink is preferable for many reasons
since the heat sink does not need to be integrated into the
electronics package which would increase the cost and
complexity of the system, albeit at a disadvantage with
regard to thermal performance since it will still require a
thermal interface material between in and the electronic
component. The waterblock alternative is also a pluggable
solution making it suitable for retrofitting existing systems.
II.
LIQUID JET ARRAYS
A. Thermal Hydraulics of Impinging Liquid Jet Arrays
There are surprisingly few correlations available for
predicting the heat transfer and pressure drop characteristics
of liquid impinging jet arrays although some do exist for
both free jets [3 4, 5, 6] and submerged jets [3, 5]. The
Robinson-Schnitzler correlation for the confined submerged
scenario will be used in this work as it was developed for
large numbers of confined and submerged liquid jets
arranged in arrays, it considers variations in jet Reynolds
number, jet-to-target spacing as well as the jet-to-jet spacing
and also included information about the pressure drop
characteristics. The correlation is,
−0.442
−0.00716
Nu
0.46⎛
⎞ ⎛ ⎞
L
S H
= 23.39Re
0.4
Pr
⎜
⎟
⎜
⎟
(1)
d n
⎝ dn
⎠ ⎝ dn
⎠
which is valid for jet to target spacings of 2≤H/d n ≤3 and
interjet spacings of 3≤S/d n ≤7. Since low hydraulic pumping
power is crucial for energy efficient water cooled devices,
Robinson and Schnitzler also developed a correlation for the
friction factor as,
229.9
f = 0 .51 +
(2)
Re
dn
which agreed with a previous correlation developed in [6],
albeit strictly for free jet arrays. With regard to the pressure
drop and pumping power, Whelan and Robinson [7] showed
that simple modifications to the inlet geometry can reduce the
pressure drop without significantly affecting the heat transfer.
B. Liquid Jet Array Waterblock Concept
One embodiment of the liquid jet array waterblock
concept is illustrated in Fig. 2. The main performance
indicator of this type of waterblock cooler is that it can
achieve exceptional heat transfer with very low hydraulic
pumping power. Compared with other commercially
available waterblocks, which almost invariably use low
velocity water impinging onto miniature surface extensions
machined into copper, this concept achieves the desired
thermal resistance by using tens to thousands of high
velocity jets which impinge on a flat copper surface. Since
the main body of the waterblock is easily manufactured from
plastic by injection molding, it is envisaged that this
7-9 October 2009, Leuven, Belgium
waterblock will be very inexpensive compared with the
competition which require CNC micromachining of complex
features which adversely affects overall cost. For a target
thermal resistance, increasing the number of jets, i.e. by
decreasing the jet orifice diameter, causes the pumping ower
to continually decrease. However, there are practical limits
such as jet clogging and manufacturability which limit the
minimum size of the jets.
The waterblock illustrated in Fig. 2 operates as follows;
water enters the foremost port shown in Fig. 2 and flows
through a section of internal tubing into a lower plenum. The
water stagnates in this plenum section and is then forced
across the jet nozzle plate through which many miniature to
micro-sized jet orifices are situated. The jets impinge upon
the topside of a copper plate whose lower face is in thermal
communication with the electronic component via a layer of
thermal interface material (not shown). Subsequent to
impinging on the surface the jets are forces laterally outward
and exit at four channels at the outer edges of the
impingement zone. The water is then forced to flow upward
along the side channels into an upper collection chamber and
subsequently forced out of the device to a remote heat
exchanger through the rear exit port shown in Fig. 2. The
waterblock housing was designed in a 3-D CAD package
and subsequently printed using a 3D Systems InVision 3D
Printer.
Fig. 2. Impinging jet waterblock concept drawing.
C. Prototype Waterblock Testing
A simple test facility has been commissioned in order to
obtain the relevant thermal hydraulic measurements for
testing different waterblock design concepts. To simulate an
active electronic device a copper block with exposed surface
area of 28.7 mm x 28.7 (commensurate with a Pentium 4
CPU) was imbedded in a block of nylon which provided
insulation as well as a rigid body for mounting the
waterblocks. The copper block was fitted with two cartridge
heaters with a total combined power of 350W as well as
three thermocouples near the upper exposed face in order to
monitor the surface heat flux. These thermocouples also
facilitated the extrapolation of the surface temperature.
The test facility also included an instrumented flow
delivery system in which the plumbing components (pumps,
©EDA Publishing/THERMINIC 2009 169
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hosing fittings etc.) were ‘off the shelf’ from popular
electronics cooling equipment distributors. The flow loop
consisted of a Laing DD12V-D5 variable speed pump which
drew deionized water from a 1.5L water reservoir
manufactured by Danger Den. In order to monitor the flow
rate, a rotameter, with a flow range of 2-10 LPM ± 1.5% FS,
was installed within the system. Two 1.5 mm diameter
sheathed T-type thermocouples, coupled with Fluke54ΙΙ
Thermometers (±0.3°C), were used to measure and record
the water temperatures at the inlet and outlet of the water
block as well as the outlet of the remote heat exchanger.
Pressure taps were installed on either side of the water block
to measure the pressure drop with a Digitron 2083P (0-200
kPa ± {0.1% rdg + 0.1% FS}) differential pressure meter.
The heat absorbed by the waterblock was dissipated to the
room air by a Thermochill PA120 remote heat exchanger
fitted with a Yate Loon D12SH-12 fan.
7-9 October 2009, Leuven, Belgium
III.
A. Problem Statement
HOT SPOT TARGETING
The evaluate the efficacy of hot spot targeting using an
impinging liquid jet array waterblock a simple test case was
selected. Here a 50mm x 50mm overall surface area is
chosen with one hot spot which is chosen arbitrarily, as
depicted in Fig. 5. The lower face of a copper block is
exposed to this heat source, representing an electronic
component. The imposed heat flux at the hot spot reaches
200 W/cm 2 while in other areas is uniform at 30 W/cm 2 . The
heat is transferred by conduction through the copper slab,
including the influence of lateral heat spreading. The
opposite side of the copper block, depicted in the far right
diagram in Fig. 5, is exposed to three different cooling
scenarios:
Case I: Cooling using some traditional method, for
instance an efficient heat sink with forced convection, with
constant thermal resistance of 0.1 K/W.
Case II: Cooling by only one impingement jet array
covering the whole copper block area.
Case III: Tailored cooling by applying two impingement
jets configurations: one focussed at the hot spot and the
second cooling the rest of the heated surface.
The performance indicators by which each method is
evaluated are the maximum temperature and the temperature
uniformity of the bottom surface of the copper i.e. the
electronic component.
Fig. 3. Test facility for water block characterization.
The waterblock was fixed to the instrumented copper
block with a layer of thermal grease sandwiched between
them. As it is cumbersome to continuously measure the
thermal resistance of the TIM layer which can change from
test-to-test, a 50 μm wire diameter bare thermocouple was
fastened to the lower face of the waterblock so that the
average surface heat transfer could be calculated without
having to subtract out the thermal resistance of the TIM
Fig. 4 shows a adequate comparison of predicted thermal
resistance versus experimental measurements for an array of
of 0.3 mm jets with a density of 81 jets/cm 2 .
Thermal resistance, o C/W
0.25
0.20
0.15
0.10
0.05
0.00
0 1 2 3 4
Rth
Water flowrate, lpm
Rth, predicted
Fig. 4. Measured and predicted heat transfer performance.
Fig. 5. The hot spot targeting problem.
B. Modelling Framework
The problem posed here is simply the solution to the
steady 3D energy equation within the solid copper block,
given as,
2 2 2
∂ T ∂ T ∂ T
+ + = 0 (3)
2 2 2
∂x
∂y
∂z
Equation 3 was solved using the finite difference technique
with second order approximations of the spatial derivatives.
Along the four edge boundaries adiabatic boundary
conditions were applied. At the bottom boundary a
distributed heat flux boundary condition was imposed,
∂T
− k = Qin
( x,
y)
(4)
∂z
z=
0
where Q in is spatially distributed according to the profile
illustrated in Fig. 5. On the opposite face a convective
boundary condition was imposed which depended on the
scenario under consideration. For Cases I and II the thermal
resistance is spatially uniform so that the boundary condition
is simply,
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7-9 October 2009, Leuven, Belgium
∂T
maximum surface temperature dropping to about 80°C,
− k = h[ T ( x,
y,
L)
− T∞
] (5)
∂z
which is acceptable, and almost doubling of the maximum
z=
L
heat removal rate on the back face as the impinging jets are a
where h can be considered an effective thermal conductance
much stronger heat sink compared with the previous
for Case I and the surface averaged heat transfer coefficient
scenario. As such there is reduced lateral conduction and
for Case II and T ∞ =25°C which is held fixed for all scenarios
heat spreading within the copper as depicted in the middle
for comparison purposes. For Case III the situation is
right plot in Fig. 6. Even still, Figs. 6 and 7 indicate that
somewhat more complex since there are two different jet
there are still notable temperature non-uniformities as the
configurations with different surface averaged heat transfer
temperature in the outer regions is about 40°C representing a
coefficients which can be expressed in the form,
maximum to minimum temperature differential of
∂T
⎧hi
[ T ( x,
y,
L)
− T∞
] inner jets
− k = ⎨
(6) ΔT max =T max -T min ~ 40°C.
∂z
z = L ⎩ho[
T ( x,
y,
L)
− T∞
] outer jets
where the jets are configured such that h i >h o in order to
provide preferential cooling in the region of high heat flux so
as to create a more uniform temperature distribution on the
simulated electronic component.
C. Base Case Scenario
To begin, base case scenarios for the Cases I, II & III have
been posed in order to gain a general feel for their
performance characteristics as well as providing the starting
points for a preliminary optimization strategy for minimizing
the temperature non-uniformities for Cases II & III. The
base case considered for Case I is a conventional heat sink
with a uniform thermal resistance of 0.1 K/W. This
corresponds with an effective thermal conductance of
h=4000W/m 2 °C or a specific thermal resistance of
R // th=2.5x10 -4 m 2 K/W, which can be considered a very high
performance fan assisted heat sink. For Case II the base case
was selected which populates the nozzle plate with 0.5 mm
orifices with a dimensionless interjet spacing of S/d n =2.5 and
jet-to-target spacing of H/d n =2.5. The total volumetric flow
rate was initially selected to be 3.5 LPM which resulted in a
net surface averaged heat transfer coefficient of h=21,296
W/m 2 °C (R // th =4.696x10 -5 m 2 K/W). For Case III the jet size
and layout was kept identical to that of Case II although two
separate regions are considered. In the low heat flux the total
flow rate was reduced so as to achieve the same surface
averaged heat transfer coefficient as in Case II. For
illustrative purposes the net flow rate through the inner hot
spot region jets was increased to achieve a surface averaged
heat transfer coefficient of h=62,490 W/m 2 °C (R // th
=1.600x10 -5 m 2 K/W) in this region. The same net effect
could have been achieved by populating the nozzle with
more jets of smaller diameter though this is inconvenient
with regard to a starting point for an optimization strategy.
Thermal performance indicators of the three base case
scenarios are illustrated in Fig. 6 and 7. On the far left of
Fig. 6 as well as in Fig. 7 it is clear that the maximum
temperature in the vicinity of the hotspot for the Case I
cooling solution (top) approaches 170°C which far exceeds
the typical maximum allowable temperature, which is of the
order of 100°C. The accompanying heat flux distribution at
the top surface shown in the left figure indicates strong
lateral conduction within the copper block as it acts as a heat
spreader since the heat sink in this case is not a strong one.
For the uniform jet configuration (Case 2: middle of Fig. 6)
the cooling performance is drastically improved with the
Fig. 6. Thermal performance indicators of the three scenarios for cases
under consideration.
Temperature, o C
190
170
150
130
110
90
70
50
30
0 10 20 30 40 50
y axis, mm
1 jet base 2 jets base Fan
Fig. 7. Comparison of temperature profiles through the centreline of the
hot spot zone (Base cases I, II and III).
©EDA Publishing/THERMINIC 2009 171
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7-9 October 2009, Leuven, Belgium
For base Case III the jet cooling is now concentrated at the with decreasing T max .
hot spot and it is evident that not only has the maximum
temperature diminished to ~60°C due to the high heat
90
removal rates in this region, but so also has the magnitude of
80
the thermal gradients at the heat source as represented by
T max -T min ~ 20°C. These are both desirable outcomes with
70
regard to component performance and reliability.
D. Optimization of Jet Cooling
The next logical step is to attempt to further improve the
performance of impingement jet array configurations by
reducing the difference between the highest and the lowest
temperature, ΔT max =T max -T min, whilst maintaining the
maximal temperature, T max , under the given threshold. This
should be a simple method which could distribute
temperatures more uniformly along the surface. As a first
approximation an uncomplicated measure of the quality of
the temperature distribution was chosen to be the deviation
from the average value as given by the normalized root mean
square deviation (NRMSD) given as,
RMSD
NRMSD = (7)
T − msx
T min
where the root mean square deviation (RMSD) is given by,
2
∑(
T(
x,
y)
− T )
RMSD = (8)
N po int s
The average temperature on the surface is,
x = 1, y 1
∑ =
T
x=
0, y=
0
( x,
y)
T = (9)
N
po int s
and the number of points are,
N ( N + 1)( N 1)
(10)
po int s
=
x
y
+
Based on the abovementioned requirements, the problem
can be formulated as the minimization of the NRMSD for
given maximal allowed temperature and given maximal
allowed temperature difference while optimizing design (d n ,
s, h) and operating parameters (V H20 ). Thus, the
mathematical formulation of the problem for Case II
involves minimizing the NMRSD using the appropriate heat
transfer correlation (Eq. 1). The design and operating
parameters space (which were selected based on practical
manufacturing considerations) is given by; d n Є [0.3, 1.5]
mm, h/d n Є [2, 3], s/d n Є [2.2, 7], V H2O Є [0.1, 50] LPM and
the constraints T max ={60, 70, 80}°C are implemented to
investigate the influence of the maximum target operating
temperature.
The results are illustrated in Fig. 8 for a cross section
through the hot spot zone. Table 1 shows the design and
operating parameters for each case. Since this is a global
cooling strategy i.e. the surface averaged heat transfer
coefficient is uniform for each scenario, the maximum
allowable temperature is achieved though the temperature
profiles still show significant non-uniformity in the region of
the hot spot. Some improvement in the temperature
uniformity is observed for decreasing T max as evident in
Table 1 where both the RMSD and ΔT max tend to decrease
Temperature, o C
60
50
40
30
0 10 20 30 40 50
y axis, mm
Tmax=60°C Tmax=70°C Tmax=80°C Base
Fig. 8. Comparison of optimal and base case temperature profiles
through the centreline of the hot spot zone (Case II)
TABLE I
Optimization results for Case II
Property T max=80 0 C T max=70 0 C T max=60 0 C
RMSD, 0 C 8.097 6.891 5.546
ΔT max, 0 C 37.89 32.76 26.87
d n, mm 0.426 0.403 0.300
h/d n 2.41 2.38 2.23
s/d n 2.87 2.98 3.55
V H2O, LPM 2.372 4.914 8.958
R // th, m 2 K/W 4.825E-5 3.288E-5 1.954E-5
Q pump, W 0.0102 0.0634 0.6978
In Case III the problem is formulated in a similar manner
as in Case II except the design and operating parameters of
the inner hot spot zone and the outer region can be varied
independently. The results are presented in Fig. 9 and Table
2. Comparing Figs. 8 & 9 and Tables 1 & 2 it is evident that
this simple technique of modifying the jet configuration in
the hot spot region improves the temperature uniformity both
by decreasing the RMSD from ~ 7°C down to ~1.4°C as
well as decreasing ΔT max from ~ 30°C down to ~9.5°C. Even
still there exists a temperature rise in the hot spot region
since T max is a constraint which occurs at the peak heat flux
of the hot spot and T is used in Eq. 8. As a result, relaxing
the heat transfer in the outer region is not feasible within the
constraints of the optimization strategy adopted in this
particular scenario. However, additional simulations were
performed whereby T=55°C and 60°C were used instead of
T in Eq. 8. The results are presented in Fig. 10 and 11 for
the case of T max =60°C. It is evident that for these two cases
the surface averaged temperature increases as expected.
Nevertheless, the temperature uniformity, quantified here in
terms ΔT max and RMSD, tends to improve, in particular for
the 55°C case. For the 60°C case the RMSD tends to worsen
as a result of the depression in the temperature distribution at
the edge of the hotspot.
The temperature depressions occur since the assumed hot
spot is a piece-wise continuous function increasing from
30W/cm 2 in the outer region to 200W/cm 2 at the peak of the
hot spot. At the hot spot there is a step change (increase) in
the surface averaged heat transfer coefficient on the opposite
face of the copper block which causes local minima to occur
©EDA Publishing/THERMINIC 2009 172
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7-9 October 2009, Leuven, Belgium
in the temperature distribution which in turn induces lateral
(Case III).
heat flow within the copper slab. Since the specific thermal
70
resistance in the hot spot zone is largely determined by the
requirement that T max =60°C and does not vary considerably
60
for each scenario in Fig. 10, decreasing the specific thermal
50
resistance in the low heat flux region, i.e. increasing the
40
averaged surface temperature, causes the local minima to
become progressively more pronounced. This occurs to the
30
point that the RMSD tends to be largest for the highest
20
averaged surface temperature even though ΔT max is lowest.
90
80
Temperature, o C
10
0
Base case Ṫ=Actual Ṫ=55°C Ṫ=60°C
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
RMSD, o C
Temperature, o C
70
60
50
40
30
0 10 20 30 40 50
y axis, mm
Tmax=60°C Tmax=70°C Tmax=80°C Base
Fig. 9. Comparison of optimal and base case temperature profiles through the
centreline of the hot spot zone (Case III).
Temperature, o C
TABLE II
Optimization results for Case III
Property T max=80 0 C T max=70 0 C T max=60 0 C
RMSD, 0 C 1.446 1.387 1.304
ΔT max, 0 C 9.84 9.48 8.97
Inner Jets
d n, mm 1.176 0.422 0.306
h/d n 3.00 2.41 2.23
s/d n 3.23 2.84 3.482
Q pump, W 0.1445 0.0803 0.5305
R // th, m 2 K/W 2.738E-5 2.042E-5 1.355E-5
Outer Jets
d n, mm 0.795 0.703 0.668
h/d n 2.31 2.64 2.73
s/d n 2.467 2.56 2.448
Q pump, W 0.1445 0.0002 0.0007
R // th, m 2 K/W 1.568E-4 1.237E-4 9.095E-5
90
80
70
60
50
40
Taverage ΔTmax RMSD
Fig. 11. Performance indicators for different average surface
temperatures
IV.
CONCLUSIONS
An uncomplicated technique of using impinging jet arrays
of different configuration within a waterblock has been
shown to predict improvement in the temperature uniformity
of an electronic component with a single hot spot. Future
work should involve the characterizing hot spots for real
devices, perhaps using the IR thermography techniques.
ACKNOWLEDGMENT
The authors acknowledge Roger Kempers (Alcatel-
Lucent) and John Mullins (Bell Labs Ireland) for rapid
prototyping the waterblocks.
REFERENCES
[1] DTI Global Watch Mission Report, “Developments and trends in
thermal management technologies - a mission to the USA,”
December 2006.
[2] A. J. Robinson, “A Thermal-Hydraulic Comparison of Liquid
Microchannel and Impinging Liquid Jet Array Heat Sinks for High
Power Electronics Cooling,” IEEE Transactions on Components
and Packaging Technologies, in press.
[3] A.J. Robinson, E. Schnitzler, "An Experimental Investigation of
Free and Submerged Liquid Miniature Jet Array Impingement Heat
Transfer", Experimental Thermal and Fluid Science, vol. 32, pp. 1-
13, 2007.
[4] Y. Pan, B.W. Webb, “Heat transfer characteristics of arrays of freesurface
liquid jets,” Journal of Heat Transfer, vol. 117, pp. 878-883,
1995.
[5] D.J. Womac, F.P. Incropera, S. Ramadhyani, “Correlating equations
for impingement cooling of small heat sources with multiple
circular liquid jets,” Journal of Heat Transfer, vol. 116, pp. 482-
486, 1994.
[6] M. Fabbri, V.K. Dhir, “Optimized heat transfer for high power
electronics cooling using arrays of microjets,” Journal of Heat
Transfer, vol. 127, pp. 760-769, 2005.
[7] B.P. Whelan, A.J. Robinson, (2009) “Nozzle Geometry Effects in
Liquid Jet Array Impingement”, Applied Thermal Engineering, 29
(11-12), pp. 2211-2221.
30
0 10 20 30 40 50
y axis, mm
T=T T=55°C T=60°C Base
Fig. 10. Temperature profiles through the centreline of the hot spot zone
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7-9 October 2009, Leuven, Belgium
Heat transfer and film thickness measurements in a
closed loop spray cooling system with R134a
Eduardo Martínez-Galván, Juan Carlos Ramos, Raúl Antón
TECNUN - University of Navarra
Paseo de Manuel Lardizábal, 13
San Sebastián, Guipúzcoa 20018 Spain.
Björn Palm, Rahmatollah Khodabandeh
Royal Institute of Technology, KTH, Department of Energy Technology
Stockholm, Sweden.
Abstract - Experimental measurements in a spray cooling test
rig have been carried out for different heat fluxes in the heater
and different volumetric spray fluxes of the refrigerant. Results
of the thermal parameters and the sprayed refrigerant liquid
film thickness over the heater are presented. The film thickness
measurements have been made with a high speed camera
equipped with a long distance microscope. It has been found
that there is a relation between the variation of the heat
transfer coefficient and the film thickness along the spray
boiling curve.
I. INTRODUCTION
Spray cooling is a powerful heat transfer technique, due to
the combined effect of forced convection and nucleate
boiling, used to remove large amounts of heat keeping lower
operating temperature. Spray cooling could be applied in:
electronic cooling, combustion technology, to cool human
skin during laser therapy, metallurgical processes, etc.
Another mechanism which also combines forced
convection and phase change is jet cooling. Estes and
Mudawar [1] made a comparison between both these
techniques and found that jet cooling produces a larger
temperature gradient in the heater surface than spray cooling,
because the latter disperses the fluid over the heater more
uniformly than the former. They also show in their
experiments that for the same flow rate the spray cooling
technique achieves a larger critical heat flux (CHF) than that
achieved using the jet cooling technique. Finally, they also
found that the CHF had a larger dependence on sub-cooling
with jets than with sprays. In jet cooling, at low sub-cooling,
the great amount of vapour generated leads to separation of
the liquid film.
Some spray characteristics which have a large effect on
the CHF are the mean droplet density, the Sauter mean
diameter and the mean droplet velocity. The most efficient
combination of these parameters is a large value of the mean
droplet velocity with a small value of the Sauter mean
diameter and the mean droplet density [2], in other words,
sprays with low density, low droplet diameters and large
velocity would have a high CHF.
The experiments made by Estes and Mudawar [3] showed
spray cooling to be more efficient at a low Weber number,
which implies a light spray. Chen et al. [2] results are in
agreement with the ones from Estes and Mudawar [3].
However, the latter concluded that the volumetric flux is a
better parameter than the droplet velocity to characterize the
spray, because it takes into account the commutative effect
of multiple drops impingement.
Estes and Mudawar also concluded that in order to
increase the CHF there are three alternatives: increasing the
flow rate, increasing the sub-cooling or decreasing the drops
size.
There is a technique employed to measure the film
thickness which uses the diffraction phenomenon through
the liquid film, but the test heater must be transparent in
order to measure with a laser beam from the bottom of it [4].
As this technique is based in the refractive index, which is
temperature dependent, and in spray cooling there is a large
temperature gradient in the film, it could not be very suitable
to measure the film thickness.
Hsieh and Tien [5] also made film thickness
measurements in the non-boiling regime for R134a coolant
which ranged between 0.93 and 1.35 mm for spray mass
fluxes between 1.33 and 1.4 kg/(m 2·s). They also
characterized the drop velocity and velocity distribution
within the spray and found that the velocity reduction
through the centreline was similar to a conventional jet.
Another parameter that has an important effect on spray
cooling is the coolant sub-cooling. Hsieh et al. [6] made
some experiments with two liquids: R134a and water. The
Weber numbers (We) and the sub-cooling degree were the
parameters that they analyzed for several heat fluxes. They
found that We had a stronger effect over the spray cooling
performance than the sub-cooling degree.
In this paper, the results of thermal and film thickness
measurements in a spray cooling system with refrigerant
R134a are presented. This refrigerant has been selected by
its high dielectric properties, because the application of this
study is electronic cooling. The film thickness measurements
were motivated to understand better the heat transfer
mechanisms which take place in the spray cooling. The film
thickness has been measured directly from images obtained
by means of a high speed camera with a long distance
microscope. It has been found that there is a relation between
©EDA Publishing/THERMINIC 2009 180
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the variation of the heat transfer coefficient and the film
thickness along the spray boiling curve.
II.
TEST RIG DESCRIPTION
Figure 1 shows a sketch of the test rig which consists of
the test chamber, with the nozzle and the heater; the
refrigerant flow loop; the sub-cooling and the condenser
water systems.
The refrigerant used was R134a, which has been sprayed
over the heater (the target surface) with a nozzle
manufactured by Spraying Systems Co. The model used has
0.56 mm orifice diameter. The pressure drop across the spray
nozzle was the parameter used to fix the volumetric flow. A
pressure transducer is connected before the nozzle in order to
measure the working pressure.
The heater consists of a copper block heated by a square
resistance heater; both have a side of 12.7 mm. In order to
measure the heater temperature, five thermocouples are
embedded in the copper block, at 1 mm beneath the surface.
The surface temperature has been calculated assuming onedimensional
heat conduction.
A variac was used to supply voltage to the heater. The
heat flux was calculated from the voltage, the resistance and
the heater area.
Figure 1. Diagram of the test rig.
In order to measure the saturation condition in the
chamber, one pressure transducer and two thermocouples,
(one in the liquid phase and the other one in the vapour)
phase, were used.
A data acquisition unit HP 34970A with a multiplexor
module HP 34901A were fed with the signals of the
thermocouples, the pressure transducers and the refrigerant
flow-meter.
Although there is a sub-cooling system, it only has been
used to sub-cool the refrigerant before the pump in order not
to have cavitations. After the pump the coolant was heated to
the saturation temperature corresponding to the chamber
pressure.
The liquid used in the condenser circuit was water. The
water temperature was fixed with an external chiller, so as to
condense all the steam generated by the heater and to keep
the pressure in the chamber constant.
7-9 October 2009, Leuven, Belgium
In order to measure the film thickness, a high speed
camera model MotionXtra HG-LE equipped with a long
distance microscope was used.
Figure 2 shows a photograph of the complete test rig with
the high speed camera.
III.
Figure 2: Test rig installation.
RESULTS AND DISCUSSION.
A. Thermal results.
It is commonly acknowledged that the spray boiling curve
seems to have the same behaviour as the pool boiling curve
[7]. This is to say, when the heat flux is low the heat transfer
mechanism is by surface evaporation, there is no bubble
generation at the heater. But as the heat flux increases,
nucleation starts over the heater; this heat transfer regime is
called nucleate boiling. As the heat flux increases, the
number of nucleate boiling sites does as well until the CHF
is reached.
The results presented here are only until the CHF is
reached, because after this point the heater surface
temperature increases drastically and the maximum
operating temperature of the resistance is 100 ºC.
As was mentioned earlier the volumetric flux is the best
parameter to characterize the spray density and the
volumetric flow. In this paper, the volumetric spray flux
(Q’’) has been defined as the ratio between volumetric flow
of liquid through the nozzle and the heater area.
The experiments were made at a chamber pressure of 5.77
bar, corresponding to a saturation temperature of 20.3 ºC.
Three different pressure drops across the nozzle have been
used: 1.5, 2 and 3 bar. The corresponding volumetric spray
fluxes were 0.018, 0.021 and 0.026 m 3 /m 2·s, respectively.
Some parameters are going to be expressed in
dimensionless form in order to compare the results with
other refrigerant spray boiling curves in future work.
The heat flux has been divided by the maximum heat flux
that can be dissipated by the latent heat, equation (1):
q"* = q"/(
ρ
f
Q"
λ)
(1)
where q” is the heat flux, ρ f is the liquid density and λ is the
latent heat.
The temperature difference between the heater surface and
the sprayed liquid has been defined as shown in the next
equation:
Δ T = T heater
−T nozzle
(2)
©EDA Publishing/THERMINIC 2009 181
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The spray boiling curves obtained in the tests are shown in
Figure 3. It can be seen that the lower the volumetric spray
flux, the higher the dimensionless heat flux at any given
temperature difference. In order to analyze the repeatability
of the measurements two of the tests have been carried out
twice, one at 2 bar (Q”=0.021 m 3 /m 2·s) and the other one at 3
bar (Q”=0.025-0.026 m 3 /m 2·s). This result is in concordance
with the results presented in [2] and [3] concluding that a
spray with a lower density is more efficient, in the sense
defined by equation (1), that is, the ratio of heat flux
removed by the spray to the maximum latent heat flux.
Dimensionless Heat Flux
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Q"=0.018 (m3/(m2s))
3 /m 2·s)
Q"=0.021 (m3/(m2s))
3 /m 2·s)
Q"=0.021 (m3/(m2s))
3 /m 2·s)
Q"=0.026 (m3/(m2s))
3 /m 2·s)
Q"=0.025 (m3/(m2s))
3 /m 2·s)
0 5 10 15 20 25 30 35 40 45
Temperature difference (ºC)
Figure 3. Spray boiling curves.
Although in Figure 3, the spray boiling curves at a high
volumetric spray flux seems to be worse than at low
volumetric flux, a higher CHF is achieved with a higher
volumetric flow, as can be seen in Figure 4 and Table I.
Critical Heat Flux (W/cm 2 )
800
700
600
500
400
300
200
Q"=0.026 (m3/(m2s))
3 /m 2·s)
Q"=0.025 (m3/(m2s))
3 /m 2·s)
Q"=0.021 (m3/(m2s))
3 /m 2·s)
Q"=0.021 (m3/(m2s))
3 /m 2·s)
Q"=0.018 (m3/(m2s))
3 /m 2·s)
Maximum heat flux
7-9 October 2009, Leuven, Belgium
linear tendency but its slope is lower than the slope of the
maximum heat flux.
Figure 5 shows the efficiency as a function of the Weber
number and the comparison of the present results with those
obtained by Visaria and Mudawar [8]. Equations (3) and (4)
have been used to calculate the efficiency and the Weber
number, respectively:
η = CHF /( ρ
f
Q"
λ + ρ
f
Q"
C
p, f
ΔTsub
)·100 (3)
where C p,f is the liquid specific heat at constant pressure and
ΔT sub is the temperature difference between the saturation
temperature and the spray temperature. As in our
experiments there is no sub-cooling, ΔT sub = 0 and equation
(1) and (3) are equal.
We = ρ Q" 2
d /σ
(4)
f 32
where Q " is the average volumetric spray flux over the
impact area [8], d 32 is the Sauter mean diameter and σ is the
surface tension.
Estes and Mudawar [3] suggested a correlation based on
Reynolds and Weber numbers to obtain d 32 , in order to
employ it in equation (4). This correlation is shown in
equation (5):
1/ 2 −0.259
d / d = 3.67( We )
32 0
d
Re
(5)
0 d0
where d 0 is the nozzle orifice diameter and We and are
d 0
Re d 0
defined as:
Wed
= ρ ( 2 P / ρ ) d
0
/ σ
0 g
Δ
(6)
f
where ρ g is the gas density and ΔP is the pressure drop
across the spray nozzle.
2
Re = ( 2ΔP
/ ρ )
1/
d / υ
(7)
d0 f 0 f
where υ is the kinematic viscosity of the liquid.
f
The equation (5) has been used to make a comparison
between our results and the Estes and Mudawar results [8].
1000
100
0
0.0020 0.0025 0.0030 0.0035 0.0040 0.0045 0.0050 0.0055 0.0060
Mass Flow (kg/s)
Figure 4. CHF vs. maximum heat flux at different spray mass flows.
TABLE I
VALUES OF THE CHF AT DIFFERENT SPRAY MASS FLOWS
AND THE CHF UNCERTAINTY.
Mass flow (g/s) CHF (W/cm 2 ) U CHF (%)
3.60 161.01 ± 2.25
4.13 174.22 ± 2.18
4.25 174.22 ± 2.18
4.97 181.02 ± 2.1
5.16 192.23 ± 2.15
In Figure 4 is also shown the maximum heat flux
calculated considering the ideal situation in which all the
refrigerant evaporates, that is, the heat transfer is only due to
the latent heat as in equation (1). In this figure, as in Figure
3, it is shown that for a low mass flow the difference
between the CHF and the maximum heat flux is lower than
for a high mass flow. Figure 4 also shows that the CHF has a
Efficiency (%)
100
10
Q"=0.026 (m3/(m2s))
3 /m 2·s)
Q"=0.025 (m3/(m2s))
3 /m 2·s)
Q"=0.021 (m3/(m2s))
3 /m 2·s)
Q"=0.021 (m3/(m2s))
3 /m 2·s)
Q"=0.018 (m3/(m2s))
3 /m 2·s)
Visaria and Mudawar [8]
1
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10
Weber number
Figure 5. Efficiency as a function of the Weber number.
The efficiency of our results shows the same trend as
those obtained by Visa and Mudawar [8].
The Nusselt number has been used to obtain the
dimensionless form of the heat transfer coefficient. This has
been calculated with equation (8).
Nu L
= hL / κ
(8)
where L is the heater length, κ is the thermal conductivity of
the liquid coolant and h is the heat transfer coefficient which
is defined as:
h = q" / ΔT
(9)
©EDA Publishing/THERMINIC 2009 182
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The highest Nusselt number was obtained with a
volumetric flux of 0.021 m 3 /m 2·s, as can be seen in Figure 6.
Apparently at 0.021 m 3 /m 2·s the combination of liquid phase
forced convection and nucleate boiling is the optimum. That
is, for the same heat flux applied the Nusselt number is the
maximum.
Nusselt number
14000
12000
10000
8000
6000
4000
2000
0
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35
Dimensionless heat flux
Q"=0.026 (m3/(m2s))
3 /m 2·s)
Q"=0.025 (m3/(m2s))
3 /m 2·s)
Q"=0.021 (m3/(m2s))
3 /m 2·s)
Q"=0.021 (m3/(m2s))
3 /m 2·s)
Q"=0.018 (m3/(m2s))
3 /m 2·s)
Figure 6. Nusselt number as a function of the dimensionless heat flux at
different volumetric spray fluxes.
7-9 October 2009, Leuven, Belgium
because the high density of the spray prevents distinguishing
the liquid film from the spray cone. Although the measure
zone is outside the spray cone, we suppose that the heat
transfer regimens which take place in the impact area are the
same in these bots areas.
The film thickness has been measured directly from
photographs taken with a high speed camera. All the images
were taken at 4000 frames per second with 448 x 448 pixels
of resolution. In order to have a good average of the film
thickness, 5 sets of samples have been taken at different
times, each of them having 1000 images.
A re-scaling of the pixel grey intensity has been made by
using the MATLAB function “imadjust” in every picture in
order to facilitate the film thickness definition. An algorithm
has also been implemented to select the heater and the film
thickness boundaries.
In Figure 8 an example is shown where the film thickness
boundary (yellow line) can be seen as well as a green line
which is the heater boundary. The heater edge has been
previously determined from a picture without spray.
B. Liquid film thickness measurement.
The sprayed refrigerant film thickness has been measured
in a zone just outside of the spray cone but over the square
heater, as represented schematically in Figure 7 (a) and
shown in the photograph in Figure 7 (b). In this picture it can
also be seen a reference target placed close to the heater in
order to know how many micrometers that corresponds to
each pixel.
Figure 8. Example of a photograph used to measure the film thickness: the
yellow line is the film thickness limit and the green line is the heater limit.
Figure 9 shows some results of the local film thickness for
different heat fluxes and a volumetric flux of 0.026 m 3 /m 2·s.
It can be seen that the film thickness increases from the
corner of the heater to the spray cone.
Figure 9 also shows that as the heat flux increases, so does
the film thickness, as expected because high heat fluxes
generate more vapour inside the film and therefore a larger
film thickness.
1200
(a)
1000
176 (W/cm 2 )
176 [W/cm2] (W/cm 2 )
147 [W/cm2] (W/cm 2 )
Film thickness ( μm)
800
600
400
124 [W/cm2] (W/cm 2 )
99 [W/cm2] (W/cm 2 )
80 [W/cm2] (W/cm 2 )
61 [W/cm2] (W/cm 2 )
45 [W/cm2] (W/cm 2 )
32 [W/cm2] (W/cm 2 )
21 [W/cm2] (W/cm 2 )
200
5 (W/cm 2 )
12 [W/cm2] (W/cm 2 )
5 [W/cm2] (W/cm 2 )
(b)
Figure 7. Measurement zone of film thickness: (a) sketch of heater base and
spray cone impact area; (b) picture of the spray cone impinging over the
heater.
The film thickness measurements were made in this zone
0
0 500 1000 1500 2000 2500 3000 3500 4000 4500
Distance from the corner of the heater to the spray cone (μm)
Figure 9. Local film thickness at 0.026 m 3 /m 2·s of volumetric flux for
different heat fluxes.
The dimensionless film thickness is the ratio between the
film thickness and the Sauter mean diameter, d 32 , calculated
with equation (5).
Figure 10 shows the dimensionless average film thickness
©EDA Publishing/THERMINIC 2009 183
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along the measure zone over the heater as a function of the
dimensionless heat flux at two different volumetric fluxes.
As previously mentioned, the larger the heat flux, the thicker
the film. But also as the volumetric flux increases, so does
the average film thickness over the heater.
Dimensionless average film thickness
20
18
16
14
12
10
8
6
4
2
0
0.00 0.05 0.10 0.15 0.20 0.25 0.30
Dimensionless heat flux
Q"=0.026 (m3/(m2s))
3 /m 2·s)
Q"=0.021 (m3/(m2s))
3 /m 2·s)
Figure 10. Dimensionless average film thickness as a function of the
dimensionless heat flux.
In Figures 11 and 12 the dimensionless average film
thickness and the Nusselt number curves are shown as a
function of the dimensionless heat flux for two different
fixed volumetric fluxes. These plots have been made in order
to see the relation of both variables during the different heat
transfer regimes.
As expected, in the forced convection zone the
dimensionless average film thickness can be considered
constant. This is because in this zone there are no vapour
bubbles in the liquid film.
After the forced convection regime, the increase in the
liquid film thickness is due to the nucleate boiling over the
heater. Figures 11 and 12 show that the nucleate boiling
regime could be divided into three zones considering the
variation of the average film thickness and the Nusselt
number with the heat flux.
In the first zone of the nucleate boiling regime, the sites
over the heater where the vapour nucleation takes place
increase as the heat flux increases. Due to that in this zone
both the average film thickness and the Nusselt number
increases with the heat flux.
Dimensionless Film thickness
20
18
16
14
12
10
8
6
Forced convection
Incrase of
heat
transfer
coefficient
Q"=0.026 (m 3 /m 2· s)
Maximun heat
transfer
coefficient
Decrase of
heat
transfer
coefficient
14000
12000
10000
4
2000
2
Nucleate boiling
0
0
0.00 0.05 0.10 0.15 0.20 0.25 0.30
Dimensionless Heat Flux
Figure 11. Dimensionless average film thickness and Nusselt number as
functions of the dimensionless heat flux for a volumetric flux of 0.026
m 3 /m 2·s.
In the second zone of the nucleate boiling regime, the
amount of nucleation sites is the optimum. Here the Nusselt
8000
6000
4000
Nusselt number
7-9 October 2009, Leuven, Belgium
number is the maximum and the film thickness seems to be
constant.
Finally, before the CHF is reached, there is a third zone in
the nucleate boiling regime: as the heat flux increases, so
does the film thickness but, unlike the other zones, the
Nusselt number decreases. Since the heat flux increases
beyond the second zone it produces a more vigorous boiling
over the heater surface with more vapour generation and,
therefore, an increase of the film thickness and a decrease of
the heat transfer coefficient. The CHF is reached when the
vapour generated over the heater surface forms dry zones
where the heat transfer coefficient drops sharply and the
heater temperature shoots up.
Dimensionless Film thickness
20
18
16
14
12
10
8
6
4
2
Forced convection
Incrase of
heat
transfer
coefficient
Q"=0.021 (m 3 /m 2·s)
Maximun
heat transfer
coefficient
Nucleate boiling
0
0
0.00 0.05 0.10 0.15 0.20 0.25 0.30
Dimensionless Heat Flux
Decrase of
heat transfer
coefficient
14000
12000
10000
Figure 12. Dimensionless average film thickness and Nusselt number as
functions of the dimensionless heat flux for a volumetric flux of 0.021
m 3 /m 2·s.
C. Uncertainty analysis.
The uncertainties from the thermal experimental
measurements are the following: ± 1.12 ºC for the
temperatures; ± 0.8% of the reading in the voltage; ± 1.1% in
the reading of the refrigerant volumetric flow; and ± 0.04 bar
for the pressure. In the measurement of the local film
thickness the maximum uncertainty is ± 29.6% and the
average is ± 11%. In the heat flux values the maximum
uncertainty is ± 10.3% at the lowest voltage and the
minimum uncertainty is ± 2.1% at the highest voltage.
IV. CONCLUSIONS.
Spray cooling experiments with R134a have been carried
out with measurements of the thermal parameters and of the
film thickness.
The spray boiling curves obtained are consistent with the
results presented in [2] and [3] about the spray density: a
lighter spray has a higher efficiency than a denser spray.
Moreover, the values of the spray cooling efficiency in the
CHF point obtained in our experiments are in good
agreement with the results presented in [8].
Although the efficiency of a dense spray is lower than for
a light spray, its CHF is larger. This is because the increase
of the volumetric spray flux entails an increase in the liquid
forced convection heat transfer capacity.
A technique based on high speed photography (or video)
has been used to measure the refrigerant film thickness over
the heater surface.
It has been found that there is a relation between the
variation of the heat transfer coefficient and the refrigerant
8000
6000
4000
2000
Nusselt number
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7-9 October 2009, Leuven, Belgium
average film thickness along the spray boiling curve. Three
zones can be defined in the nucleate boiling regime of the
curve based on the variation of both parameters.
The film thickness in the highest Nusselt number zone is
more or less 3 times the film thickness in the liquid forced
convection regime. The highest Nusselt number was
obtained for the volumetric spray flux of 0.021 m 3 /m 2·s.
Apparently, the combination between forced convection and
latent heat transfer is the best for this volumetric flux.
The analysis of the film thickness variations during the
spray cooling provide a good qualitative explanation of the
heat transfer mechanisms which take place on the liquid film
over the heater.
ACKNOWLEDGMENTS
This research was partially funded by Eusko Jaurlaritza-
Gobierno Vasco, Spain through grants SAIOTEK 2006-07.
The authors wish to acknowledge the financial support of
Cátedra Fundación Antonio Aranzábal–Universidad de
Navarra and Asociación de Amigos de la Universidad de
Navarra.
REFERENCES
[1] K. A. Estes and I. Mudawar, “Comparison of two- phase electronic
cooling using free jests and sprays,” Advances in Elec. Packaging,
ASME., vol. 10-2, 1995, pp. 975-987.
[2] R-H Chen, L. C. Chow and J. E. Navedo, “Optimal spray
characteristics in water spray cooling,” Int. J. Heat Mass Transfer,
vol. 47, 2004, pp. 5095-5099.
[3] K. A. Estes and I. Mudawar, “Correlation of Sauter mean diameter
and critical heat flux for spray cooling of small surfaces,” Int. J.
Heat Mass Transfer, vol. 38, No. 16, 1995, pp. 2985-2996.
[4] J. Yang, L. C. Chow and M. R. Pais, “Liquid film thickness and
topography determination using Fresnel diffraction and
holography,” Experimental Heat Transfer, vol. 5, 1992, pp. 239-
252.
[5] S.-S. Hsieh and C.-H. Tie, “R-134a spray dynamics and
impingement cooling in the non-boiling regime,” Int. J. Heat Mass
Transfer, vol. 50, 2007, pp. 502-512.
[6] S.-S. Hsieh, T.-C. Fan and H.-H. Tsai, “Spray cooling
characteristics of water and R-134a. Part I: nucleate boiling,” Int. J.
Heat Mass Transfer, vol. 47, 2004, pp. 5703-5712.
[7] J. Kim, “Spray cooling heat transfer: The state of the art,”
International J. Heat and Fluid Flow, vol. 28, 2007, pp. 753-767.
[8] M. Visaria and I. Mudawar, “Effects of high subcooling on twophase
spray cooling and critical heat flux,” Int. J. Heat Mass
Transfer, vol. 51, 2008, pp. 5269-5278.
©EDA Publishing/THERMINIC 2009 185
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7-9 October 2009, Leuven, Belgium
Thermal Management of a 3D Chip Stack using a
Liquid Interface to a Synthetic Jet Cooled Spreader
Krishna Kota, Pablo Hidalgo, Yogendra Joshi, and Ari Glezer
The George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology
771 Ferst Drive NW, Atlanta, GA 30332-0405 USA
Phone: (404) 894-3266, Fax: (404) 894-8496, Email: Ari.Glezer@me.gatech.edu
Abstract – The present investigation focuses on the design of
a unique liquid interface thermal management solution for a 3-
D chip stack that is embedded within a cavity, in a heat
spreader cooled by an array of synthetic jet actuators. The
heat sink module was previously reported by the authors, who
achieved an overall heat transfer coefficient of ~70 W/m 2 .K.
The radial heat sink exploits enhanced, small-scale heat
transfer that is affected by a central array of synthetic jet
actuators. This approach is very effective due to the short
radial thermal path of the cooling air along the fins which
couples rapid, time-periodic entrainment and ejection of cool
and heated air, respectively to increase the local heat transfer
coefficient on the air-side. The key focus of this paper is the
numerical simulation of the dielectric liquid interface used to
efficiently transmit the heat from the high power 3D stacked
electronics to the heat sink base. The coupled natural
convection in the fluid and conduction in solid spreaders
sandwiched between the tiers of the stack form a novel efficient,
passive and scalable thermal management solution.
I. INTRODUCTION
The demand for future electronics to exhibit enhanced
functionality with a small form factor has led to many
innovations in device and assembly technologies. A popular
assembly technique that is recently gaining prominence is
stacking multiple electronic modules vertically as
tiers/layers, thus reducing the lateral footprint of the
assembly. This provides ample scope to miniaturize
electronics but with the penalty of significant thermal
management issues. The rate of heat generated per unit
volume increases significantly with each added tier and heat
removal from the ICs (Integrated Circuits) sandwiched in the
middle of the stack is a major challenge under such
scenarios.
Thermal management of chip stacks is typically based on
cooling of the outermost tiers (or layers), which poses
thermal gradients within the stack because of heat
concentration in the middle tiers. Package-level thermal
management solutions have included the use of thermal vias
through the substrate material for vertical heat transfer and
the use of high thermal conductivity substrates. While these
approaches involve complex electrical connections, they
often provide only a marginal improvement in thermal
performance (e.g., [1]). Integrated microchannel cooling has
been reported in recent years, wherein the microchannels are
formed directly in one or more of the components that
constitute the package [2]. Flow and pool boiling were also
proposed for cooling 3D stacked electronics recently [3].
But, integrated microchannel technology requires external
power to pump the cooling fluid against large pressure drops
(owing to narrow flow passages) and atypical fabrication
methods for the components (usually, substrates). Boiling
involves increased pressure inside enclosures and
undesirable vapor pocket formation. Single phase liquid
immersion natural convection cooling of electronics in
enclosures has been widely researched (e.g., [4-9]). While
natural convection immersion cooling is passive, it is
difficult to promote it in narrow passages. Since typical
stacking of most electronics is implemented in the vertical
direction, the resulting enclosure is a narrow horizontal one.
Studies until now have focused on immersion cooling of
stacked electronics in vertical enclosures in which natural
convection heat transfer cooling is relatively easy to
accomplish compared to horizontal enclosures. A few
studies have focused on natural convection in horizontal
enclosures but are mostly limited to heat sources placed in a
single plane/layer [10,11], instead of stacked in 3D.
A novel conduction-natural convection based cooling
solution for thermal management of 3D stacked electronics is
presented in this paper. Numerical simulation of the heat
transfer phenomena are carried out, when the concept is
coupled with a radial finned heat sink cooled by an array of
synthetic jet actuators.
II.
CONCEPT
In the proposed implementation, internal copper spreader
layers are integrated with the stack to form a pyramid-like
structure for lateral heat transfer from the stacked devices, as
shown in Fig. 1. The stack is submerged in dielectric liquid
so that heat is transferred from the external surfaces of the
lateral spreaders to the liquid by natural convection. In the
present implementation, the stack is designed to promote
natural convection flow, and the heat is ultimately
transferred to the heat spreader through the internal surfaces
of the cavity as shown in Fig. 2. Though direct conduction
cooling methods avoid the complexities associated with
liquid containment and handling, they pose significant
mechanical and stress challenges in applications that require
very compact and relatively high-power thermal
©EDA Publishing/THERMINIC 2009 186
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management solutions. The present direct liquid immersion
interface significantly reduces thermal resistance, allows for
extremely compact packaging, alleviates thermo-mechanical
stresses, and is easily scalable.
Fig. 1. Immersion cooling of 3D stack in FC-77 using sandwiched solid
spreaders arranged in truncated pyramid shape
An important aspect of the integration of a 3-D chip stack
to the heat sink is the thermal interface between the stack and
the heat spreader. This interface is complicated not only by
the need to implement a low-resistance thermal interface in a
3-D configuration that includes significant internal and
external connections, but also by the need to minimize
thermally- and assembly-induced mechanical stresses.
7-9 October 2009, Leuven, Belgium
convection is laminar with Gr based on the height of the
enclosure (which is the largest value compared to individual
heights of the spreaders from the enclosure top surface) was
3x10 6 and Gr based on the lateral extension of each spreader
was found to be ~1x10 4 , both of which are

7-9 October 2009, Leuven, Belgium
for some cases. Therefore, to save computational time and
memory, grids consisting of element count around 18,161
were used for all the simulations.
Sudden spikes in the numerical solution (in both velocity
and temperature fields), especially at the solid-fluid
of the tiers that are closely spaced, resulting in a very narrow
gap for the fluid to circulate in the vertical direction. Hence,
the only mode of heat transfer is natural convection to the
sides in the narrow vertical region between the ends of the
tiers and the enclosure, which is weak and results in
interface, were dampened by introducing numerical unacceptably high temperatures. It must be noted that for
diffusion in the equation system. This was done by this simulation, the geometry setup was assumed to have no
manually adding a diffusion coefficient to the electrical connections between two successive tiers as a
flow/thermophysical property/diffusivity of the dielectric simplification.
fluid. This technique enabled stability and convergence of
the solution. Reducing the numerical diffusion coefficient
below 0.5 was found to not alter the solution field
significantly but allowed substantially large mesh sizes.
Therefore, a value of 0.5 was used for numerical diffusion
for all the simulations.
IV.
RESULTS AND DISCUSSION
The developed numerical model was used to study the
effect of key enabling features on the functionality of the
proposed thermal management solution.
A. Importance of solid spreaders
The effectiveness of sandwiched solid spreaders between
the tiers was first studied. Table I gives the material and
thermophysical property data used for all the simulations in
this paper. Thermophysical properties of the dielectric fluid
were considered as functions of temperature [14].
Part
TABLE I
MATERIAL AND THERMOPHYSICAL PROPERTY DATA
Material
Thermal
Conductivity
(W/m.K)
Density
(kg/m 3 )
Specific
Heat
(J/kg.K)
Substrate FR-4 0.3 1900 1369
IC Si 163 2330 703
Heat
Spreader
Dielectric
Fluid
Dielectric
Box
Heat Sink
Base
Cu 400 8700 385
FC-77
[14]
Dynamic
Viscosity
(Pa.s)
0.065-8x10 -5 T * 1838-2.45T 1014+1.554T 56.25x10 -5
Cu 400 8700 385
Cu 400 8700 385
Heat Sink Cu 400 8700 385
Solder
Bumps
Epoxy (to
join IC to
the
Spreader)
Pb-Sn 50
Pyroduct
®597A
[15]
9
* T is the temperature in 0 C
Fig. 4 shows the geometry of the stack enclosure. A
maximum allowable chip temperature, T max , of 350 K (77
0 C) was assumed. The maximum chip temperature can be
observed as 358 K (at the end of first 300 s) for the dielectric
fluid in natural convection. The steady state value was
found to be over 400 K. Therefore, natural convection alone
was found to be inadequate for effectively removing heat
from the tiers. This is because of the horizontal orientation
Fig. 4. Natural convection cooling of the 3D stack – geometry and results
Following this, the heat transfer in stack integrated with
solid spreaders sandwiched between the circuit tiers (Fig. 5)
was investigated for comparison.
Fig. 5. Immersion cooling of 3D pyramid-structures stack submerged in a
dielectric liquid.
In Fig. 1, the assumed values are, A=42.5, E=15, F=7.48,
G=0.5, H=0.87 and I=1, all in mm. The remaining values
are chosen from case V as described in the next subsection.
The induced natural convection velocity field between the
edges of the stack and the cavity surfaces is shown in Fig. 6.
It is remarkable that even though the height of the stack
enclosure is only 8 mm, strong natural convection of the FC-
77 is prevalent over the entire fluid domain. This effect is
due to the truncated pyramidal arrangement. This is not
possible if no spreaders are used, or if all the spreaders have
the same size.
Fig. 6. The 3D velocity field associated with natural convection of the
dielectric fluid
Of particular note is a vortical structure that forms near the
corner of the cavity. It appears that the appearance of the
secondary flow is enabled by the stepwise edge of the
pyramid. The recirculating flow results in effective
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spreading of the heat to the cavity walls, and the resulting
lower temperatures. Fig. 6 also indicates that the flow above
the top surface of the stack is primarily dominated by local
natural convection cells, with relatively little communication
with the bulk flow around the sides of the pyramid. The
resulting temperature distribution is shown in Fig. 7.
7-9 October 2009, Leuven, Belgium
used to spread heat more effectively and hence the proposed
idea is easily scalable.
TABLE II
SPREADER SIZE EFFECT ON MAXIMUM CHIP TEMPERATURE
Case
B C D J T max
(mm) (mm) (mm) (mm) (K)
I 60 73.5 85 90 332.7
II 47.5 52.5 57.5 60 340.4
III 45 47.5 50 52.5 343.1
IV 47.5 52.5 57.5 60 334.6
V 45 47.5 50 52.5 337.8
Tmax (K)
355
350
345
340
335
330
Fig. 7. Temperature distribution (in K) in the integrated heat sink
In this example, the maximum temperature within the chip
stack is 337.8 K, which is considerably lower than the
maximum allowable operating temperature of 350 K. At the
same time, the volume footprint of the entire assembly is
only 76.2 mm square by 43.2 mm height. In this
arrangement, the bottom surface of the heat spreader is
insulated and therefore the bottom tier is the warmest, but
this effect is minimized by the pyramid structure, which
helps in achieving more uniform temperatures in the stack.
Note that if the power dissipation of the stack tiers varies,
the heat spreaders can be designed or rearranged to achieve a
more uniform temperature distribution by exploiting local
convection currents within the dielectric fluid.
B. Impact of spreader size
Various platform dimensions of the copper spreaders were
explored with a goal of minimizing the lateral dimension of
the module for optimal heat transfer. The results are
summarized in Table II, where cases I to III are for an
arrangement as shown in Fig. 1 and cases IV and V are for
the setup shown in Fig. 5. It is interesting to note the
usefulness of solid copper filling the no/low-convection
zones between the lateral spreader extensions. T max is
reduced by filling the spaces with extra copper. It is also
noteworthy that the existence of no gaps between the stack
levels prevents the dielectric fluid from accumulating in
domains where the flow is restricted and thus avoids stagnant
localized air pockets that may form due to degassing, or
vapor pockets in two-phase flow.
Fig. 8 shows T max with increasing stack power (combined
power from all the four ICs in the stack). As expected, it
was found to increase nearly linearly with total chip power.
The assumed spreader size (case V) was found to be capable
of dissipating up to 50 W to the fluid, without exceeding the
allowable temperature limit. It can be concluded from Table
II and Fig. 8 that a design with large spreader sizes can be
325
25 30 35 40 45 50 55 60
Total Chip Power (W)
Fig. 8. Total stack power vs. maximum chip temperature (T max)
C. Impact of epoxy thermal conductivity
The foremost path of heat transfer in the proposed solution
is between the chip and the copper spreaders. A large
thermal resistance between these two entities is a bottleneck
for effective heat removal from the chip. Fig. 8 shows the
effect of thermal contact resistance, R c , between the spreader
and the chip on the maximum chip temperature. It can be
seen from the figure that thermal resistance at the contact
between the spreader and the clamp is significant only when
an air gap is present. If an interface material with a thermal
conductivity > 0.1 W/m.K is used to fill the gap (assumed as
125 micrometers), the resistance becomes negligible.
Fig. 8. Effect of contact resistance (R c) between the spreader and the chip on
chip maximum temperature (T max)
The insignificant effect of R c on T max is because of its
small value, compared to the thermal resistance to heat
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7-9 October 2009, Leuven, Belgium
transfer in dielectric fluid. This can be better observed in It can be seen that if the number of holes, N, in the
Fig. 9 and Table III, where the volume-averaged temperature spreader is >5000, only then T max increases very rapidly. For
values of various components in the heat transfer path from N < 5000, having holes in the spreader around the chip
the heat source to the final heat sink are provided.
contact zone has negligible effect on the heat removal.
E. Impact of synthetic jet heat transfer coefficient
As mentioned before, the heat transfer coefficient, h,
obtained by synthetic jets can vary depending on the
operating conditions. Hence, simulations were run for a
typical range of h. From Fig. 11 it can be observed that T max
is well within the assumed operating limit of the stack even
for h as low as 50 W/m 2 .K.
Fig. 9. Isosurface temperature (in K) plot for the heat sink – base –
enclosure assembly
TABLE III
AVERAGE TEMPERATURES OF VARIOUS COMPONENTS OF THE ASSEMBLY IN
THE MAJOR HEAT TRANSFER PATH
Component Average Temperature (K)
IC 335
Cu. Spreaders 329
FC-77 320
Base 315
Finned heat sink 313
D. Impact of interconnect holes
3D stacking of electronics needs electrical connections
between the layers of the stack for data transfer and signal
communication. Accordingly, a provision in the form of
holes needs to be provided in the sandwiched heat spreaders
to facilitate passing of wires. Fig. 10 shows the effect of
number of interconnecting holes, N, on heat spreading
through the bottommost spreader.
Fig. 10. Effect of number of holes (N) on chip maximum temperature
(T max)
Fig. 11. Effect of synthetic jet heat transfer coefficient (h) on the chip
maximum temperature (T max)
V. CONCLUSION
The present work has numerically demonstrated that the
liquid thermal interface can result in effective heat transfer
from 3D IC stack, while alleviating the difficulties
associated with packaging and assembly. The suggested
design is highly suitable for compact applications and is an
ideal candidate for scaling. The number of pyramidal solid
spreaders can be simply increased with each additional tier
and their size can be tailored to suit the power requirements
and promote natural convection at the same time, all without
changing the base concept design.
The heat spreader is integrated with an efficient, synthetic
jet based radial heat sink to reject the heat to the ambient.
Numerical simulation was used to demonstrate the
workability of the concept. It was shown that promoting
natural convection effectively in narrow horizontal
enclosures (with 8 mm height in the present case) is viable,
effective and is capable of removing a few tens of Watts of
heat. The effectiveness of the concept depends on the heat
removal path on the air-side. With a sufficiently high heat
transfer coefficient on the air-side (when coupled with a
radial heat sink cooled by synthetic jets as shown in the
paper), thermal resistance in the dielectric liquid is a major
hindrance to heat transfer but can be reduced by providing
additional circulation in the fluid.
Some of the key impediments to effective implementation
of the concept were identified and a parametric study was
performed with corresponding parameters. It was found that
they only have a marginal impact on the performance under
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7-9 October 2009, Leuven, Belgium
typical operating conditions. The concept and the numerical
model will be validated by experiments that are currently
underway.
ACKNOWLEDGMENT
The authors wish to acknowledge DARPA Microsystems
Technology Office for funding the work through the 3D
MINT program and Irvine Sensors Corporation.
REFERENCES
[1] D. Pinjala, M.K. Iyer, C.S. Guan, and I.J. Rasiah, “Thermal
characterization of vias using compact models,” Proc. EPTC 2000,
pp. 144-147, 5-7 Dec 2000.
[2] T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle,
H. Oppermann, and H. Reichl, “Forced Convective Interlayer
Cooling in Vertically Integrated Packages,” Proc. ITHERM 2008,
pp. 1114-1125, Orlando, Florida, 28-31 May 2008.
[3] A. Bar-Cohen, K. Geisler, and E. Rahim, “Pool and Flow Boiling
in Narrow Gaps – Application to 3D Chip Stacks,” Proc. Fifth
European Thermal-Sciences Conference, Eindhoven, The
Netherlands, 18-22 May 2008.
[4] D.E. Wroblewski, Y. Joshi, “Liquid Immersion Cooling of a
Substrate-Mounted Protrusion in a Three-Dimensional Enclosure:
The effects of Geomotry and Boundary Conditions,” J. Heat Tran.,
vol. 116, pp. 112-119, February 1994.
[5] Y. Joshi, M.D. Kelleher, M. Powell, and E.I. Torres, “Natural
Convection Heat Transfer from an Array of Rectangular
Protrusions in an Enclosure Filled with Dielectric Liquid,” J.
Electron. Packaging, vol. 116, pp. 138-147, June 1994.
[6] T.J. Heindel, S. Ramadhyani, and F.P. Incropera, “Conjugate
Natural Convection from an Array of Discrete Heat Sources: Part 1
– Two- and Three-Dimensional Model Validation,” Int. J. Heat and
Fluid Flow, vol. 16, pp. 501-510, 1995.
[7] T.J. Heindel, S. Ramadhyani, and F.P. Incropera, “Conjugate
Natural Convection from an Array of Discrete Heat Sources: Part 2
– A Numerical Parametric Study,” Int. J. Heat and Fluid Flow, vol.
16, pp. 511-518, 1995.
[8] S.K.W. Tou, C.P. Tso, and X. Zhang, “3-D Numerical Analysis of
Natural Conevctive Liquid Cooling of a 3x3 Heater Array in
Rectangular Enclosures,” Int. J. Heat Mass Tran., vol. 42, pp. 3231-
3244, 1999.
[9] Y.L. He, W.W. Yang, and W.Q. Tao, “Three-Dimensional
Numerical Study of Natural Convective Heat Transfer of a Liquid
in a Cubic Enclosure,” Num. Heat Tran. A, vol. 47, pp. 917-934,
June 2005.
[10] Q-.H. Deng, G-.F. Tang, Y. Li, and M.Y. Ha, “Interaction Between
Discrete Heat Sources in Horizontal Natural Convection
Enclosures,” Int. J. Heat Mass. Tran., vol. 45, pp. 5117-5132,
2002.
[11] A. Bazylak, N. Djilali, and D. Sinton, “Natural Convection in an
Enclosure with Distributed Heat Sources,” Num. Heat Tran. A, vol.
49, pp. 655-667, October 2006.
[12] F.P. Incropera, D.P. DeWitt, Introduction to Heat Transfer, 4 th Ed.,
John Wiley & Sons, Inc., New York, NY, 2002.
[13] D. Gerty, D.W. Gerlach, Y.K. Joshi, and A. Glezer, “Development
of a Prototype Thermal Management Solution for 3-D Stacked Chip
Electronics by Intervealed Solid Spreaders and Synthetic Jets”.
THERMINIC 2007, Budapest, Hungary, 17-19 September 2007.
[14] www.3m.com
[15] www.aremco.com
©EDA Publishing/THERMINIC 2009 191
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7-9 October 2009, Leuven, Belgium
Presentation and status of the NANOPACK project
A. Ziaei, S. Demoustier
Thales Research and Technology - France
Campus Polytechnique
1, avenue Augustin Fresnel
91767 Palaiseau Cedex, France
Abstract – NANOPACK – Nano Packaging Technology for
Interconnect and Heat Dissipation – is a European large-scale
integrating project aiming at the development of new
technologies and materials for low thermal resistance interfaces
and electrical interconnects, by exploring the capabilities
offered by nanotechnologies such as carbon nanotubes,
nanoparticles and nano-structured surfaces, and by using
different enhancing contact formation mechanisms, compatible
with high volume manufacturing technologies. Several key
research areas relative to thermal management, interconnect
and packaging are addressed in the project by European
industrial and academic partners: thermal interface materials,
assembly, reliability and characterisation, supported by
modeling and simulations. After an overview of NANOPACK, a
status of the project progress is presenteed in these different
fields.
I. INTRODUCTION
Thermal management of chip based electronic devices is
becoming one of the largest bottlenecks to increased
performance and integration density. Size scaling of
transistors and increase of the clock rate according to
Moore’s law and the semiconductor industry association
(SIA) roadmap led to an explosion in power-density for logic
circuits, communication devices, and memory. Although the
energy per operation is still decreasing, cramming more and
more transistors to the same area increases the density of
dissipated power to an unacceptable level that threatens the
current fast rate of progress of the industry. On the path from
the source in the drain region of individual transistors to the
heatsink – be it an air or a liquid cooler – the heat flux
crosses a multitude of interfaces some of them separated by
bulk amounts of matter.
To reduce the thermal resistance from junction to ambient,
new generations of low thermal resistance interfaces and low
electrical resistance interconnects are needed. Efforts are
focused in NANOPACK on the development of thermal
interface materials (TIM), enhancing surface mechanisms
and assembly technologies to reach total thermal interface
resistance as low as a few Kmm²/W. Such low targeted
values raise the question of their measurements with enough
accuracy and repeatability. That’s why high-end specific
characterisation systems are also implemented in the
framework of NANOPACK.
As more nanoparticles are used to improve the
performance of filled materials by increasing heat transfer
between solid surfaces and fluids, these nano-fluids will also
be confronted with effects related to phonon quantization
and will need experimental investigation as well as
theoretical frameworks. To allow a continued development
of the semiconductor industry, as stated in the SIA roadmap,
an improved understanding of phononics in nanoparticle
filled fluids or composites is needed. Nano-scale modeling
and characterisation techniques are developed in the project
to tackle these issues.
II. NANOPACK OVERVIEW
NANOPACK is a large-scale Integrating Project
performed within the Information and Communication
Technologies (ICT) theme of the 7 th European Framework
Program, targeting the development of next-generation
nanoelectronics components and electronics integration.
The NANOPACK consortium, placed under the lead of
Thales Research and Technology, consists of 4 major
industrial partners, 4 innovative SMEs, and 6 academic
groups in total representing 8 European countries and
providing all the necessary competences in all key areas
dedicated to thermal management, interconnect and
packaging: thermal interface materials (TIM), thermal
interface assembly, reliability, characterisation and modeling
supported by world class computers. The total cost of the
project is 11 M€ for a total funding of 7.4 M€.
Fig. 1. NANOPACK Technology Base
The overall objective of the NANOPACK project is to
develop new thermal interface technologies for low thermal
resistance by employing nano-modified surfaces and
materials along with methods to characterize and simulate
them with respect to thermal, electrical and reliability-related
properties. Three parallel approaches will be pursued to
improve thermal and electrical performance: enhancement of
bulk conductivity of filled systems, reduction of bondline
©EDA Publishing/THERMINIC 2009 192
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thickness, and optimization of nanoscale thermal and
electrical contact surfaces (see Fig. 1). To tackle the overall
project purpose, four major technical objectives are targeted:
• To develop new interface technologies for low thermal
and electrical resistance and discover new high-density
integration technologies;
• To develop new characterisation methods and tools for
thin and highly conductive interface layers;
• To understand heat transfer on a micro/ nano scale thanks
to simulative and nano-analytical methods;
• To build optimal demonstrators with respect to thermal,
electrical and reliability-related properties to create
impact in several industries.
III. PROJECT STATUS AND PROGRESS
In order to successfully achieve the project goals and
enable the development of leading thermal management and
interconnect technologies at the horizon of 2010, the project
has been organized into 6 main technical work packages
which address the following research issues: materials and
process development, thermal, electrical and mechanical
characterizations, nano- to macro-scale modeling and
simulations. Several demonstrators will be designed to
validate the adequacy of the technologies with applications
such as microprocessors, automotive and aerospace high
power electronics and high power radio-frequency switches.
7-9 October 2009, Leuven, Belgium
B. Process Development and Optimization
These activities aim at establishing new manufacture and
integration process which enables more efficient heat
removal in modern integrated circuits and microsystems.
Several parallel routes are studied. A surface modification
technique based on micromachined hierarchical nested
channels (HNC) has proven its efficiency to reduce the final
BLT by > 20% for the majority of TIMs on 1-250cm2
interfaces. Au-nanosponge surface enhancement technique is
also under evaluation to decrease interfacial contact
resistance. Properties of randomly distribubted and aligned
Carbon Nanotubes (CNT) are currently studied. A specific
process has been establish to manufacture a metal-polymer
composite with thermal conductivty as high as 20 W/mK.
Finally, fine pitch CNT bumps reported with isotropic
adhesives are serious candidates as future flip chip
interconnect technology (Fig. 3).
Fig. 2. NANOPACK Work Packages
A. Materials Development
Thermal grease, thermal conductive adhesive, thermal
conductive phase change materials and electrically
conductive adhesive (ECA) are currently developped in the
project. The fabrication methodology is based on the
synthesis of nano-structured materials such as nanoparticles,
nanotubes, nanofibrils and on the optimisation of dispersing
technologies to generate minimum thermal barriers between
nano-fillers and matrix to achieve a maximum thermal
conductivity. More than 6 W/mK as thermal conductivity
has been reached by bimodal thermal grease, with spherical
metallic micro spheres and graphitsed Carbon Nano Fibers
(CNF) in Silicone matrix. Bimodal ECA with 9.5 W/mK as
thermal conductivity has been fabricated by incorporating
silver flakes and micro silver spheres in bi-epoxy matrix.
Reliability tests are under progress.
Fig. 3: CNT bumps transferred by patterned Isotropic Conductive Adhesive
films
C. Fabrication of Test Structures and Characterisation
This work is focused on the characterization of the
interface materials developed in the project along with their
process dependence in thermal, electrical and thermomechanical
properties. It requires to manufacture test
structures to facilitate the in-situ measurement of thin layers
of very high thermal conductivity materials. Additional test
structures are also realised in order to investigate the
electrical properties of microscale particle stacks for
electrical interconnects in power electronics die attach.
Failure of interfaces and crack propagation are studied
thanks to advanced in-situ thermo-mechanical experiments.
Thermal resistance values smaller than 10 mK/W are
expected to be measured with an accuracy of 3 - 5 % thanks
to original designs of several TIM testers in steady state.
Spatially resoluted measurements of electrical conductivity
with 5 μΩ resolution are also on stakes. The 3-omega
method is also adapted in the project to retrieve local
information on the subcontinuum (spatial dispersion) heat
conduction as nanostructured materials offer a promising
way to increase the heat transfer between TIMs and their
substrates.
E. Modeling and Simulations
State-of-the-art simulation techniques are developed to
better understand heat transfer at the nano and micro scales
in thin films and dense particle systems. Analytic techniques,
FDTD methods and molecular dynamics simulations are
used to explore phonon properties in nano scale systems. In
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7-9 October 2009, Leuven, Belgium
addition to more scientific studies, traditional tools such as
finite element analysis for mechanical structures are
incorporated for design of demonstrator devices and failure
analysis.
F. Demonstrators
With better cooling as developed in the NANOPACK
project, electronic components can be packed more densely
and be operated at higher power levels. This strongly
increases the energy efficiency of the systems by reducing
the need for chiller systems and limiting the waste of
materials associated with lower density systems. The
objective of this work is to exploit the newly enabled
technologies by demonstrating several devices owning
unprecedented thermal and electrical capabilities, in the
fields of microprocessors, automotive and aerospace high
power electronics and high power radio-frequency switches.
IV. LIST OF PARTNERS
The NANOPACK consortium consists of 4 major
industrial partners, 4 innovative SMEs, and 6 academic
groups in total representing 8 European countries:
Thales Research & Technology, France
Budapest University of Technology and Economics, Hungary
Robert Bosch GmbH, Germany
Institut d’Electronique de Microtechnologies et de
Nanotechnologie, France
Chalmers University of Technology, Sweden
Electrovac AG, Austria
Foab Elektronik AG, Sweden
Fraunhofer Insititut IZM, Germany
IBM Zurich Research Laboratory, Switzerland
Catalan Institute of Nanotechnology, Spain
MicReD Ltd. Hungary
Berliner Nanotest und Design GmbH, Germany
Thales Avionics, France
VTT Micro and Nanoelectronics, Finland
ACKNOWLEDGMENT
This work is supported by the European Commission 7 th
Framework Programme (FP7), under the grant agreement
n°216176 (NANOPACK).
©EDA Publishing/THERMINIC 2009 194
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Electro-Thermal Modeling of Nano-Scale Devices
D. Vasileska 1 , K. Raleva 2 and S. M. Goodnick 1
1 Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706, USA
2 Faculty of Electrical Engineering and Information Technology, University Sts. Cyril and Methodius, Skopje, Republic of
Macedonia
Abstract-In this paper we present simulation results obtained with
our electro-thermal device simulator when modeling different
technology generations of FD-SOI devices. In particular, we stress
out the importance of the temperature boundary conditions for
digital and analog circuits and the use of the full model which
takes into account both temperature and thickness dependence
(which is particularly important for thin silicon films) of the
thermal conductivity.
Key-words: electro-thermal modeling, FDSOI devices,
particle-based device simulations
I. INTRODUCTION
The scaling of semiconductor devices into the nanometer
regime and the problems associated with further
miniaturization of device technologies has resulted into
investigation of devices with alternative materials and
alternative device designs such as fully-depleted (FD), dualgate
(DG), tri-gate silicon-on-insulator (SOI) and other device
designs. The problem with SOI devices is that they exhibit selfheating
effects. These self-heating effects arise from the fact
that the underlying SiO 2 layer has about 100 times smaller
thermal conductivity than bulk Si (1.4 W/m/K). Also, the
thickness of the silicon film in nanoscale devices is much
smaller than the phonon mean free path which is on the order
of 300 nm in bulk silicon. Therefore, boundary scattering
becomes dominant scattering mechanism, thus reducing the
thermal conductivity value to a fraction of its bulk value. For
example, the bulk thermal conductivity in silicon is 148
W/m/K and the thermal conductivity of a silicon film of
thickness of 10 nm is 13 W/m/K (a factor of 10 smaller than
the bulk value). Also, in thin silicon films the thermal
conductivity has smaller temperature dependence because
boundary scattering is temperature independent scattering
process.
II. THE ROLE OF THE TEMPERATURE BOUNDARY
CONDITIONS
In analog devices neighboring devices are typically on and if
the gate contacts are also biased then there is no heat flow
through the gate contact and the side boundaries. In these cases
it is appropriate to use Neumann boundary conditions on the
side (artificial) boundaries and Neumann boundary conditions
on the gate electrode. Simulation results for the current
degradation for different technology of FD SOI devices,
summarized in Table 1, are presented in Figure 1.
In the case of digital circuits, the devices are rarely on and
the use of Dirichlet boundary conditions at the gate and the side
boundaries are the appropriate boundary conditions. This
corresponds to the best-case scenario of heat removal from the
device active region. Simulation results for the current
degradation for different technology devices when Dirichlet
boundary conditions are applied to the gate and the side
boundaries, are shown in Figure 2.
Table 1. Parameters for various simulated device technology nodes (constant
field scaling) [1].
L
(nm)
tox
(nm)
t Si
(nm)
t box
(nm)
N ch
(cm -3 )
V GS=V DS
(V)
I D
(mA/um)
25 2 10 50 1×10 18 1.2 1.82
45 2 18 60 1×10 18 1.2 1.41
60 2 24 80 1×10 18 1.2 1.14
80 2 32 100 1×10 17 1.5 1.78
90 2 36 120 1×10 17 1.5 1.67
100 2 40 140 1×10 17 1.5 1.57
120 3 48 160 1×10 17 1.8 1.37
140 3 56 180 1×10 17 1.8 1.23
180 3 72 200 1×10 17 1.8 1.03
L- Gate Length; tox- Gate Oxide Thickness;
t Si- Active Si Layer Thickness;
t box- BOX Thickness;
N ch- Channel Doping Concentration;
I D- Isothermal current value (300K).
Degradation (%)
100
75
50
25
300K
400K
600K
Neumann
0
50 100 150
Gate Length (nm)
Figure 1. Current degradation vs. technology generation ranging from 25 nm to
180 nm channel length FD SOI devices (Table 1). Isothermal boundary
condition of 300K is set on the bottom of the BOX. Parameter is the
temperature on the gate electrode. Neumann boundary conditions are applied at
the vertical sides.
Degradation (%)
100
80
60
40
20
300K
Neumann
0
50 100 150
Gate Length (nm)
Figure 2. Current degradation for the case of Dirichlet boundary conditions at
the artificial boundaries. In one case Dirichlet boundary conditions are applied
at the gate electrode with T Gate=300 K and in the second case Neumann
boundary conditions are applied at the gate electrode.
©EDA Publishing/THERMINIC 2009 195
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III. TEMPERATURE AND THICKNESS DEPENDENT THERMAL
CONDUCTIVITY MODEL
In order to perform more realistic estimates of the current
degradation using temperature and thickness dependent thermal
conductivity model we follow the work of Sondheimer [2], that
takes into account phonon boundary scattering (by assuming it
to be purely diffusive). Namely, the thermal conductivity of a
semiconductor film of a thickness a, under the assumption that
the z-axis is perpendicular to the plane of the film, the surfaces
of the film being at z=0 and z=a, is given by:
π /2
⎧
3 ⎛ a ⎞ ⎛ a−2z
⎞⎫
κ() z = κ0() T sinθ 1−exp − cosh
dθ
(1)
∫ ⎨ ⎜ ⎟ ⎜ ⎟⎬
2()cos λT
θ 2()cos λT
θ
0 ⎩ ⎝ ⎠ ⎝ ⎠⎭
where λ(T) is the mean free path expressed as
λ( T) = λ0
(300/ T)
nm where room temperature mean free
path of bulk phonons is taken to be λ
0
= 290 nm.
Selberherr [3,4] has parametrized the temperature
dependence of the bulk thermal conductivity in the temperature
range between 250K and 1000K. In our case we find that the
appropriate expression is:
135
κ
0( T ) = W/m/K
(2)
2
a + bT + cT
where a=0.03, b=1.56×10 -3 , and c=1.65×10 -6 . Eqs. (1) and (2)
give almost perfect fit to the experimental and the theoretical
data reported in an Asheghi paper [5] (see Figure 3).
In Table 2 we compare electro-thermal simulation results
for various models for two different device gate lengths (25 nm
and 180 nm). Dirichlet boundary conditions are assumed on the
gate and back contact (300K), and the other boundaries are
treated as Neumann boundary conditions (no heat flow).
Thermal conductivity (W/m/K)
80
60
40
experimental data
full lines: BTE predictions
dashed lines: empirical model
thin lines: Sondheimer
100nm
50nm
30nm
20
20nm
300 400 500 600
Temperature (K)
Figure 3. Silicon film thickness dependence of the average thermal
conductivity at T=300 K vs. active silicon layer thickness. Experimental data
are taken from the work of Asheghi and co-workers [5].
In Fig. 4, we show the temperature maps in the active
region of the 25 nm and 180 nm channel length device with the
full anisotropic and temperature dependent thermal
conductivity model. Compared to earlier results [6], we find
that the anisotropic and temperature dependent thermal
conductivity model leads to higher lattice temperature profiles
7-9 October 2009, Leuven, Belgium
at the drain end of the channel and in the channel itself for
larger device structures even though the current degradations
are very similar. This makes the heat removal process from the
drain contact more difficult.
Table 2. Absolute values of the currents for: (1) bulk thermal conductivity
model, (2) temperature-dependent bulk thermal conductivity model, (3)
anisotropic thickness dependent thermal conductivity model, and (4)
anisotropic thickness and temperature dependent thermal conductivity model.
25nm FD SOI (V GS=V DS=1.2V) 180nm FD SOI (V
Thermal
GS=V DS=1.8V)
Current (isothermal):1.824mA/um Current (isothermal):1.032mA/um
conductivity
Current
Current
Current
Current
model
(mA/um) Decrease (%) (mA/um) Decrease (%)
142.3 W/m/K 1.714 6.0 0.922 10.7
κ bulk=κ bulk(T) 1.712 6.1 0.915 11.3
anisotropic 1.698 6.9 0.887 14.0
13 W/m/K 1.702 6.7 0.875 15.2
2
4
6
8
10
383K
528K
25 50 75
500
450
400
520
20
500
480
40
450K
539K 460
60
440
420
0 180 360 540
Figure 4. Lattice temperature for a 25 nm channel length device (top)
and a 180 nm gate-length device (bottom).
ACKNOWLEDGMENT
This work was supported in part by the Arizona Institute
for NanoElectronics (AINE).
REFERENCES
[1] ITRS for FD SOI devices: http://public.itrs.net/ .
[2] E. H. Sondheimer, “The Mean Free Path of Electrons in Metals”,
Advances in Physics, Vol. 1, no. 1, Jan. 1952, reprinted in Advances in
Physics, Vol. 50, pp. 499-537, 2001.
[3] V. Palankovski and S. Selberherr, „Micro materials modeling in
MINIMOS-NT“, Journal Microsystem Technologies, Vol. 7, pp. 183-
187 November, 2001.
[4] Silvaco Manual (www.silvaco.com).
[5] W. Liu and M. Asheghi, “Thermal condition in ultrathin pure and doped
single-crystal silicon layers at high temperatures”, J. Appl. Phys., Vol. 98,
123523-1 (2005).
[6] K. Raleva, D. Vasileska, S. M. Goodnick and M. Nedjalkov, “Modeling
Thermal Effects in Nanodevices”, IEEE Transactions on Electron
Devices, vol. 55, issue 6, pp. 1306-1316, June 2008.
Biography of Dragica Vasileska:
Dragica Vasileska (B.S.E.E. 1985, M.S.E.E. 1992, Ph.D. 1995). From 1995
until 1997 she held a Faculty Research Associate position at ASU. In 1997 she
joined the faculty of Electrical Engineering at ASU. Her research interests
include semiconductor device physics and device modeling. Dr. Vasileska has
published more than 120 journal publications.
©EDA Publishing/THERMINIC 2009 196
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Effects of Quantum Corrections and Isotope
Scattering on Silicon Thermal Properties
Javier V. Goicochea
IBM Research GmbH, Zurich Research Laboratory, 8803 Rüschlikon, Switzerland
Marcela Madrid
Pittsburgh Supercomputing Center, Pittsburgh, PA 15213, USA
Cristina Amon
Department of Mechanical and Industrial Engineering, University of Toronto, Toronto, ON, M5S 1A4, Canada
Abstract- A quantum correction procedure is proposed to
correct silicon thermal properties estimated with molecular
dynamics (MD). The procedure considers the energy
quantization per mode basis and the anharmonic nature of the
potential energy function (including the thermal expansion of
the crystal) and is applied to reported thermal properties of
silicon estimated with MD in ref. [11], such as temperature,
specific heat and thermal conductivity. The procedure
facilitates the use of these properties as input to faster
numerical methods, such as those based on the Boltzmann
transport equation under the single relaxation time
approximation. In addition, the effect of isotope scattering is
included in reported values of phonon-phonon relaxation times.
The effects of the correction procedure and the scattering with
isotopes are analyzed in terms of the change of phonon specific
heat, mean free path and thermal conductivity. We have found
that the application of quantum corrections yields a significant
reduction in the contribution of high-frequency modes to the
overall thermal conductivity. This contribution is further
reduced by the inclusion of isotope scattering. At 220 K, the
total contribution of optical modes reduces from 12.3 % (before
quantum corrections) to 5.8 %; and to 2 % when the isotope
scattering is also considered. The quantum corrections and the
inclusion of isotope scattering are found to bring the estimated
thermal conductivity into close agreement with experimental
values. The relative contributions of the acoustic and optical
modes after quantum corrections agrees very well with recently
reported ab initio results.
I. INTRODUCTION
Several alternatives have been proposed to link MD with
other continuum or sub-continuum models [1, 2]. Most
approaches divide the macroscopic domain in regions where
different numerical methods are employed. The different
levels of interaction have been typically described using MD
and finite element (FE) methods [1, 2]. In some cases,
quantum-mechanics models are concurrently used to
estimate unknown parameters required by MD. The link
between these methods is achieved by defining a special
interaction region (also called hand-shake region), where the
FE-mesh overlaps with the atoms defined in MD. Usually, a
special Hamiltonian is used to describe such interaction [2,
3]. Problems like crack propagation, dynamic of fractures,
nano-indentation and dislocation generation have been
addressed by these methods. Conversely, neither of these is
suitable for describing the sub-continuum heat transport in
semiconductors. The common simplification of the
interatomic potential and the assumption of long wave
behavior (both required for solving the FE method), changes
the scattering mechanisms of interacting heat carriers and
affects the description of the heat transport in
semiconductors. In addition, the assumption of long wave
behavior neglects the existence of optical modes, which are
important in describing sub-continuum heat transfer under
self-heating conditions [4-9].
For semiconductor materials, the sub-continuum heat
transport has been studied by means of the Boltzmann
transport equation (BTE) for phonons. Phonons are
quantized lattice vibrations, subject to different scattering
mechanisms that affect how the heat is transported in the
crystalline structure [10]. The complexity of the scattering
mechanisms has led to the development of phenomenological
models whose thermal predictions depend on thermal
properties difficult to estimate or measure in advance, such
as phonon relaxation times and dispersion relations. To
avoid this, MD simulations and the normal mode
decomposition have been recently used to estimate all
thermal properties of silicon required as input to the BTE,
including phonon relaxation times, dispersion relations,
group velocities and specific heat, at 300 and 1000 K [11].
However to use these quantities, quantum corrections (QCs)
are necessary since both methods interpret the physics of
phonons differently.
The main idea of QCs is to map the results obtained
classically (using MD) onto their quantum analogs at the
same energy level. In a quantum system, the phonon
occupation number is a function of the temperature and
frequency, and the energy is quantized in units of h ω . In a
classical, the modes are equally excited regardless of the
temperature, have an energy expectation value of about and
are continuous functions of the instantaneous position and
momentum of the particles in the system [12]. These
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differences affect the values of the properties estimated
using MD. At temperatures below the Debye’s temperature,
quantum effects are particularly important due to the
mode specific heat and thermal conductivity. We include the
relaxation time associated with isotope scattering to our
previously reported values for phonon-phonon scattering and
freezing of high frequency modes, while at high analyze their effect over the mode thermal conductivity.
temperatures ( T > θ D ) the predictions of both systems are Lastly, in section 5 a summary of results and conclusions is
expected to converge [17]. The Debye’s temperature for given.
silicon has been estimated to be 645 K [18].
Unfortunately, the common procedure for applying the
QCs (see Eqs. 1-3) has several limitations. These limitations
can potentially impact the thermal predictions obtained with
MD. First, the anharmonic nature of the potential energy
function and the thermal expansion of the crystal are
typically neglected. Second, there is an inconsistency when
the MD results are compared directly with the experimental
data after QCs. The inconsistency lies on the difference
between the number of isotopes (atoms of the same element
with different atomic mass) included in the MD simulation
and the corresponding number in naturally occurring
semiconductors. While natural silicon ( nat Si) has three stable
isotopes ( 28 Si, 29 Si and 30 Si, in a proportion of 92.23%,
4.67% and 3.1%, respectively), most MD simulations
include only one. To compare the MD results with
experimental data for nat Si, the isotope scattering should be
included in the analysis. Third, the standard QCs procedure
for thermal conductivity implicitly modifies individual mode
contributions by a constant factor (i.e. given by cv / 3k
B N ).
The constant factor is applied regardless of the quantization
of the energy as a function of frequency. The quantization of
the energy can severely impact the contribution of phonon
modes to the overall thermal conductivity. Lastly, although
the intention to apply QCs is to compare the MD results with
experimental values, the procedure relies only on the
analytic estimation of the specific heat and does not include
a solid connection with measurable properties. Other
quantum correction procedures have been proposed [19], but
have not been fully evaluated and cannot be applied to
correct all thermal properties needed to solve the BTE.
These limitations can potentially impact the applicability of
the thermal predictions obtained from MD.
In this work, a QC procedure is proposed and applied to
correct the temperature, specific heat and thermal
conductivity. The procedure considers the quantization of
the energy per mode and addresses the limitations previously
proposed QC methods. In addition, we analyze the effects of
QCs and isotope scattering over the frequency-dependent
specific heat and mode thermal conductivity. The new QC
procedure is applied to the thermal properties reported in
[11].
The manuscript is structured as follows: In section 2, we
review the standard procedure used to apply QCs to MD
results. We review the scattering of phonons with isotopes
and the expressions commonly used to calculate its
associated relaxation time as a function of frequency. In
section 3, we describe the equations and methodology
followed to apply the new QC procedure. In section 4, we
analyze the effects of the new QC over the temperature,
II.
LITERATURE REVIEW
A. Standard Quantum Corrections
The standard procedure to correct the temperature consists
on equating the total energy of the classical system (LHS)
with the corresponding in a quantum system (RHS) [14-16],
such that
3 N −1
k T = ∑ h ω n + 1/ 2
(1)
( ) [ ]
B
MD
m
m
m
where, h / 2 represents the zero-point energy,
ω m
−
[ exp( / k ) −1] 1
nm = hω m BT
is the phonon occupation
number, T MD and T are the temperature of the molecular
dynamics simulation and the QC temperature. Note that the
occupation number is a function of phonon frequency ( ω )
and temperature. In the equation the summation is taken over
the m normal modes of the system. The QC temperature is
determined by replacing the phonon occupation number
expression in Eq. 1.
The correction for the thermal conductivity is obtained
assuming that the quantum heat flux is equal to that of a
classical system [12, 14], as
dT dTMD
q = −k
real = −k
MD
(2)
dx dx
Hence, to obtain the corrected thermal conductivity ( k ),
the value of the MD thermal conductivity ( k MD ) is
multiplied by the correction factor dT MD / dT , which can be
calculated from Eq. 1,
dTMD
k = k MD
(3)
dT
In Eq. 3, the factor dT MD / dT affects the overall value of
thermal conductivity regardless of the contribution of each
mode and is given by c / k N .
B. Isotope Scattering
v 3
B
For temperatures below 350 K, a significant increase in
thermal conductivity has been reported as the concentration
of impurities is reduced [22], such is the case of isotopically
enriched 28 Si. Capinski et al. [22] reported an increase of the
thermal conductivity of isotopically pure Si (i.e. 99.7 % of
28 Si) over a temperature range of 100 - 375 K. At room
temperature the increase in the thermal conductivity was
reported to be 60 % for the isotope enriched silicon samples
[22, 23]. However, as shown in Fig. 1, recent experimental
evidence has revealed that such increase in the thermal
conductivity of isotope enriched silicon might be lower than
previously measured. At room temperature only an increase
m
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7-9 October 2009, Leuven, Belgium
of 7 to 10 % has been found [24-26] .
found using the experimental specific heat for nat Si [30]. Due
to the lack of experimental specific heat data for single
It is well known that the fluctuation in the mass silicon isotopes, the quantum corrected temperature is also
distribution throughout a crystal produces thermal resistance obtained using the analytical expression for specific heat
[27-29]. Klemens [29] and Carruthers [28] have suggested (both results are presented in Table I), given by [31]
two similar expressions for the relaxation times associated to cv, a ( T ) =
isotope scattering,
∑ cv,
a ( T,
ωm
)
(7a)
m
−1
4
−1
A 4
τ imp = Aω and τ imp = ω
(4)
⎪⎧
⎪⎫
3
2 exp( hωm
/ kBT
)
v
c ( )
g
v,
a T = ∑ ⎨kB
( h ωm
/ kBT
)
⎬ (7b)
2
m
⎪⎩
[ exp( hωm
/ kBT
) −1]
⎪ ⎭
where, v g is the phonon group velocity and A is a fitted
constant.
where cv, a
( T,
ωm
) is the mode contribution to the specific
Thermal conductivity (W/m-K)
400
350
300
250
200
150
Δk e
= 16.8 %
100
200 210 220 230 240 250 260 270 280 290 300
Temperature (K)
nat Si - Ho et al. 1974
nat Si - Capinski et al. 1997
nat Si - Kremer et al. 2004
28 Si - Capinski et al. 1997
28 Si - Ruf et al. 2000
28 Si - Gusev et al. 2002
28 Si - Kremer et al. 2004 (Sample NN)
Fig. 1 - Experimental values of thermal conductivity of natural and isotopeenriched
silicon. Δ ke
represents the reduction of the thermal conductivity
due to isotope scattering measured in [25].
III. METHODOLOGY
To obtain the quantum corrected temperature, we modify
the approach described in [14] to include the quantization of
the energy per mode basis and the change of the dispersion
relations. In [14], the thermal conductivity correction factor
is written as,
dT c T
MD v,
e(
)
= (5)
dT 3( N −1)
kB
/ V
where, dT MD / dT is now defined as the ratio between the
experimental ( c v , e ) and the classical specific heats, N is the
number of atoms in the simulation, k B is the Boltzmann
constant. The relation between the molecular dynamics and
corrected temperatures can be found integrating Eq. 5 with
respect to temperature,
V T
*
TMD ( T ) = cv, e(
T ) dT + T
3( N −1)
k ∫
(6)
0
B
In this expression the integration constant * T is of the
order of the Debye temperature [14]. The zero-point energy
term is implicitly included since we are using the
experimental specific heat. The corrected temperature (T ) is
heat. In Eq. 7b, the summation is taken over all phonon
modes in [100] and is computed using the dispersion relation
previously determined using MD [11] at different
temperatures, which include the effects of anharmonicity (i.e.
thermal expansion and change of the dispersion relations).
In addition, due to the difference between the experimental
[12] and analytical dispersion relations at room temperature,
it is expected that the experimental Debye temperature ( θ D )
will be different from the one calculated using pair
potentials, such as, Stillinger-Weber, Tersoff, EDIP, etc.
Therefore, the integration constant in Eq. (6) is adjusted to
include this difference, such that
⎛
max
⎞
* θ ⎜
ω
D
a,
k
T =
⎟
∑
(8)
⎜ max
6 ⎟
k = 1,6 ⎝ ω e , k ⎠
max max
where, ω a,k and ω e,k are the maximum frequencies of the
analytical and experimental dispersion relations for each
branch. Based on our previous results obtained using the
Stillinger-Weber potential [11], we found that the integration
constant is T * =790.94 K. Eq. 8 would converge to the
experimental Debye temperature if both dispersion relations
(experimental and analytical) are equal.
To obtain the correction for the thermal conductivity and
specific heat, Eq. 3 is adjusted to include the quantization of
the energy of each mode at T . In addition, the analytic
specific heat is obtained using the dispersion relations
determined using MD at the studied temperatures. The
thermal conductivity is corrected considering that the
specific heat depends on: i) the temperature, ii) the frequency
(ω ) and iii) the ratio between the total experimental and
analytical specific heats ( c T ) / c ( ) ), as
k(
T)
c
⎧
( T)
⎪4π
⎨
( T)
⎪ 3
⎩
v , e ( v,
a T
= v , e
∑ ∫
c
v,
a
In the equation, v g and p
⎡ωm,max
⎤⎫
1 ⎛
⎞
⎢ ⎜
vg
⎟ ⎥⎪ a
r ⎬
( ) ⎢ ⎜
v
2
c , ( T,
ω)
τ ω dω
3
2
2π
v ⎟ ⎥
⎪ ⎭
b,
p ⎢⎣
ωm,min
⎝
p ⎠ ⎥⎦
… (9)
v are the phonon group and phase
velocities and τ r is the phonon relaxation time. The
expression between curly brackets corresponds to the
Tiwari’s thermal conductivity expression [32]. For
simplicity, we assume that the thermal properties of the
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7-9 October 2009, Leuven, Belgium
silicon crystal are isotropic and equal to those for the [100] 1.2
direction. The thermal conductivity obtained with Eq. 9 is
1.1
further corrected ( k'
→ k /( π / 3)
) to account for the real
1
volume of the first Brillouin zone.
To include the isotope scattering, we find the value of the
coefficient A of Eq. 4 that produces a reduction in the
thermal conductivity equal to the one observed
experimentally due to the presence of isotopes. As shown in
Fig. 1, we compute the decrease of thermal conductivity at
the quantum corrected temperature from [25], avoiding in
this way mixing thermal conductivity values from different
measuring techniques and equipments. The final expression
of the phonon relaxation time, including phonon-phonon and
impurity scattering, is written using the Matthiessen’s rule,
−1 −1
−1
as: τ τ + τ .
r
= ph−
ph imp
c v
/ k B
0.9
0.8
0.7
0.6
0.5
0.4
TA
LA
Before QCs
After QCs
0.3
0 2 4 6
Frequency (rad/s)
8 10 12
x 10 13
Fig. 2 - Mode contribution to the specific heat before and after quantum
corrections at 220 K. Arrows indicate the frequency range of each mode.
LO
TO
IV.
RESULTS
Quantum corrections. Table I shows the value of the
quantum corrected temperature using the experimental
specific heat for nat Si [30] and using the analytical expression
for the specific heat (Eq. 7b), with T * = 790.94 K. Both
estimates provide similar results. At T MD = 300 K, the
corrected temperature is roughly 220 K, while at 1000 K the
temperature quantum corrections are negligible.
TABLE I
Quantum corrected temperature (Eq. 6)
T MD (K) T (K)
Experimental
Analytical
300 218.5 220.6
1000 1011.3 1006.5
Quantum corrections also affect the behavior of the
contribution of each mode to the specific heat with
frequency. Fig. 2 shows the contribution of each mode as a
function frequency at T MD = 300 K. As expected, before
QCs the mode contribution obtained MD is independent of
the frequency, however, when the quantization of the energy
is considered and QCs are applied, the contribution of each
mode decreases as their frequency increases. The quantum
corrected mode contribution starts at almost the same value
of the corresponding for the classical anharmonic system
( c v / k B = 1), however, the difference becomes larger at
higher frequencies. This is also expected for real systems
where c v / k B →1
as ω → 0 and c v / k B < 1 as ω > 0 . In the
figure, the small shift in the specific heat value observed at
zero-frequency is produced due to the difference between the
experimental and analytic specific heats ( cv , e( T ) / cv,
a(
T ) ).
Fig. 3 shows the contribution for each mode to the thermal
conductivity as a function of the frequency in the [100]
direction. Eq. 9 has been arranged such that,
ωm,max
k
k ω dω
(10)
= ∑∫
m
ω
m,min
m
( )
It is observed that the contribution of each mode is
substantially affected by the correction of the specific heat
and decreases as the frequency of the modes increases. This
is evident for the LO mode, whose contribution near the
Brillouin zone before QCs is comparable to that of the
acoustic modes, but reduces significantly after QCs are
applied. Before quantum corrections, the contribution of the
TA and LA modes to the total thermal conductivity is
approximately 33.9% and 55.9%, respectively [11]. As
shown in Table II, when the proposed QCs are applied, the
quantization of the energy changes both the relative
contribution of each mode and overall value of the thermal
conductivity. This is not the case when the standard
procedure is applied. The standard procedure only modifies
the overall value of thermal conductivity by a factor equal to
c v, a(
T ) / 3( N − 1)
kB
. However, the relative contribution of
the different modes remains the same.
k m
(ω) (W/m-K*s/rad)
Before QCs
4
After QCs
3.5
3
LA
2.5
2
1.5
TA
LO
1
0.5
TO
0
0 2 4 6 8 10 12
4.5 x 10-12 Frequency (rad/s)
x 10 13
Fig. 3 - Mode contribution to thermal conductivity before and after QCs.
As noted in Fig. 3, the specific heat of high-frequency
modes is substantially affected. This translates in a reduction
of the thermal conductivity values for the LA, LO and TO
modes, while the value for TA mode remains almost the
same. The contribution of the acoustic modes increases to
©EDA Publishing/THERMINIC 2009 200
ISBN: 978-2-35500-010-2

From
7-9 October 2009, Leuven, Belgium
TABLE II
Overall thermal conductivity and relative mode contribution before and after QCs at T = 220 K
Factor
Factor
value
MD n/a n/a
+Standard QCs
+Proposed QCs
c
v,
a
( T )
3( N −1)
k
c
c
v , e
v,
a
( T )
( T )
B
0.645
1.037
k
TA
(W/m-K)
128.615
(33.87%)
82.932
(33.87%)
125.303
(38.62%)
k
LA
(W/m-K)
212.151
(55.87%)
136.797
(55.87%)
180.660
(55.67%)
k
LO
(W/m-K)
35.800
(9.43%)
23.084
(9.43%)
17.310
(5.33%)
Total 94.29 % 5.71 %
k
k ' = k *(3/ π )
TO
(W/m-K) (W/m-K)
3.092
(0.82%)
362.549
1.994
(0.82%)
1.218
(0.38%)
233.773
309.866
94.29 % (i.e. an increase of 4.54 % from the values before
QCs), while the contribution of the optical modes becomes
5.71 %. The contribution of the LO and TO modes reduces
from 9.43 % and 0.82 % before QCs to 5.33 % and 0.38 %
after QCs, respectively, and the TA mode increases from 33.87
to 38.62 %. These results are in excellent agreement with
recent ab initio predictions [33], in which acoustic modes
provide 95% of the contribution to the thermal conductivity
and that the contribution of LA is higher than that from the TA
mode.
Isotope scattering. Based on the experimental data for nat Si
and 28 Si [25] at the corrected temperature, the reduction in the
thermal conductivity is estimated to be 16.80 % (measured
relatively to the nat Si thermal conductivity). Table III shows the
MD thermal conductivity before and after QCs including the
isotropic scattering term. Before QCs are applied, the deviation
of the MD-predicted thermal conductivity with respect to the
experimental value is 44.48 % for 28 Si. When QCs and the
isotope scattering are applied this difference reduces to 23.48
and 13.94 % respectively.
TABLE III
Thermal conductivity before and after isotopic scattering at T = 220 K
From
k
k
k
−1*100
−1*100
(W/m-K) ke( 28 nat
Si)
ke(
Si)
MD 362.5 44.48 %
+QC 309.9 23.48 %
+ISO 265.3 13.94 %
k ( 28 e Si) = 250.934 W/m-K [25], ke ( Si)
= 232.844 W/m-K [21], k e
:
experimental thermal conductivity.
The inclusion of the isotope scattering term modifies all
properties that depend on the phonon relation times. Although,
both isotope scattering expressions (Eq. 4) lead to the same
value of thermal conductivity, the relative contributions of the
modes change. The contribution of the optical modes
decreases, while the on from the acoustical modes increases.
The acoustical modes contribute 97.6 % when the velocity term
is neglected and 98.5 % when is included. Additionally, the
contribution of optical modes becomes almost negligible (less
that 2.4 %).
Fig. 4 shows the mode thermal conductivity as a function of
frequency. In terms of frequency, the isotope scattering lowers
significantly the contribution of optical modes. For both
scattering terms, the contribution of the LO mode reduces
more than half, while the one from TO becomes negligible
(less than 0.01 %). At the same time, the mode thermal
conductivity of the TA does not experience a significant
change, while the LA changes as the frequency increases.
k m
(ω) (W/m-K*s/rad)
Before isotope scattering
4 Isotope scattering: A*ω 4 3 x 10-13 LO
Isotope scattering: A/v *ω 4 2.5
3.5
g
2
3
1.5
1
TO
2.5
LA
0.5
2
0.95 1 1.05 1.1
x 10 14
1.5
1
TA
LO
0.5
TO
0
0 2 4 6 8 10 12
4.5 x 10-12 Frequency (rad/s)
x 10 13
Fig. 4 - Contribution to the thermal conductivity of the TA, LA, LO and TO
modes before (solid thick line) and after isotope scattering.
V. HIGH TEMPERATURE IMPLICATIONS
T ≥ θD
At high temperatures (
), both the quantization of
the energy and the presence of isotopes are expected to have
a minor effect on the reduction of the thermal conductivity.
Note that the contribution to the thermal conductivity from
the high frequency modes as the temperature of the system
is increased would progressively become similar to the one
estimated with MD (before QCs).
VI. SUMMARY AND CONCLUSIONS
In this work a new quantum correction procedure was
proposed to correct silicon thermal properties obtained from
molecular dynamics. The procedure considers the energy
quantization per mode basis and the anharmonic nature of
the potential energy function, and involves the use of
experimental or analytical specific heat values. In addition,
the effect of isotope scattering was analyzed in terms of the
change of the mode thermal conductivity.
In the standard quantum correction procedure, the specific
©EDA Publishing/THERMINIC 2009 201
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7-9 October 2009, Leuven, Belgium
heat is corrected by a factor defined as the ratio of the
quantum and classic energies ( c v, a(
T ) / 3( N − 1)
kB
) while the
quantization of the energy leads to changes on the
contribution of each mode to the specific heat with
frequency. These are more severe as the frequency of the
modes increases. The changes in the specific heat modify the
individual contribution of the modes to the overall thermal
conductivity of the crystal. After the new quantum correction
procedure is applied, the relative contribution of acoustic
modes to the overall thermal conductivity becomes 94.29 %
(being k LA > kTA
, see Tables II-IV). This result compares
very well with recent ab initio calculations [33], which
indicate that acoustic modes contribute about 95 % to the
total thermal conductivity and that the contribution of LA
modes is higher than that from TA modes. In addition, it is
found that the proposed QC alternative improves the thermal
conductivity prediction when compared with experimental
results for nat Si and 28 Si. Despite the variability of the
reported thermal conductivity for isotopically enriched 28 Si,
our conservative assumption of 16.80 % reduction in the
thermal conductivity, leads to a reasonable agreement with
experimental results for nat Si.
Lastly, when isotope scattering is included, the
contribution to the thermal conductivity of the LO and TO
modes is further reduced, especially when the group velocity
is considered. Most of the contributions to the thermal
conductivity still come from the LA and TA modes. At high
temperatures, when all modes are thermally excited and the
system behaves classically, the effects of the energy
quantization and the isotope scattering are negligible.
ACKNOWLEDGMENT
The authors gratefully acknowledge the funding of the
National Science Foundation grant CTS-0103082, the
Pennsylvania Infrastructure Technology Alliance (PITA) and
NANOPACK.
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©EDA Publishing/THERMINIC 2009 202
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7-9 October 2009, Leuven, Belgium
Directional Thermal Conductivity of a Thin Si Suspended
Membrane with Stretched Ge Quantum Dots
Jean-Numa Gillet, ∗ Bahram Djafari-Rouhani, Yan Pennec
Université de Lille 1, Institut d'Electronique de Microélectronique et de Nanotechnologie (IEMN, CNRS UMR 8520),
Département de Physique, Av. Poincaré, BP 60069, 59652 Villeneuve d'Ascq cedex, France (www.iemn.univ-lille1.fr);
Members of the European Consortium NANOPACK
Abstract-We model a nanomaterial showing a hybrid
thermal behavior between dissipative and insulating
regimes. The nanomaterial is made up of a thin Si
suspended membrane covered by self-assembled Ge
quantum dots (QDs) with facets. A membrane plane is
constituted from the orthogonal [100] and [001]
directions (x and z, respectively). The QDs are stretched
in [001] forming nanoscale phonon waveguides. When
hot and cold junctions are connected to the membrane
following [001], the throughput thermal conductivity λ
shows a significant exaltation with respect to the in-plane
orthogonal direction [001] where QD constriction is
defined. This property can be used for the design of
nanoscale dissipaters to remove heat in only one main
direction. Indeed, low leakage heat currents are
obtained in other directions so that they cannot affect
thermal budget in other parts of a device to cool as a
silicon chip. In our theoretical model, a deflection angle
β is taken in a membrane plane from the axis x. The
anisotropic thermal conductivity is analyzed as a
function of β. In an example molecular-scale device, λ
can be exalted by 4 to 5 folds, or from 0.7 to 2.9 W/m/K,
when β is increased from 0° (x) to 90° (z), respectively.
Therefore, the QD-waveguide nanomaterial presents a
different thermal insulating behavior in the direction
[100] and can as well be used for the design of both
dissipative and thermoelectric devices. The transition
between both contra effects is obtained for the in-plane
close-packed directions .
Keywords: Heat dissipation, Thermoelectrics, Nanoscale
devices, Quantum dots, Silicon, Germanium
I. INTRODUCTION
The design of nanostructured semiconducting
devices with optimized thermal properties and indirect
electronic band gap (as those using the Si/Ge IV-IV
∗ Corresponding author’s email: jean-numa.gillet@univ-lille1.fr
couple) is currently one of the major challenges for onchip
cooling in nanoscale silicon-based architectures [1].
These thermal nanodevices should enable continuation of
the historical integration pace given by the Moore's law
in CMOS microelectronics.
With the fast and spectacular development of
nanotechnology, self-assembly became a major
technology for bottom-up fabrication of threedimensional
(3D) nanostructured devices for various
applications in drug design, biotechnologies, electronics
and photonics, for instance [2-5]. Epitaxial self-assembly
has been used to design germanium quantum-dot (QD)
arrays in silicon [6,7]. The Ge QDs stand on or are
sandwiched between diamond-cubic (dc) Si thin layers.
In the classical Stranski-Krastanov growth mode, a thin
wetting Ge layer is grown by epitaxy in the vertical
direction with respect to a Si {010} substrate as
investigated by experimentalists to fabricate twodimensional
(2D) arrays of self-assembled (SA) Ge
islands forming QDs with facets on Si. 3D ordering of a
SA Ge-QD array in a Si matrix can be obtained,
thereafter, by propagation of the stress field from a
bottom layer to the superposed layers. To obtain sharper
Ge QDs with lower size dispersion, more sophisticated
technologies as e-beam and focus ion beam can be used.
3D QD Ge/Si nanocomposites were used for quantum
applications (as single-electron or single-photon devices,
e.g.) and for solar-energy conversion.
Gillet et al. recently presented theoretical studies of
3D SA Ge-QD supercrystals in Si for the design of
crystalline thermoelectric (TE) devices that can be
CMOS-compatible [8,9]. These Si/Ge supercrystals can
present an extreme reduction of the thermal conductivity
λ that can be lower than only 0.04 W/m/K (i.e. less than
twice the value of air) for different size parameters and
Ge concentrations [9,10]. The aim of modeling this 3D
Si/Ge supercrystal was to obtain λ as tiny as possible
since the energy-conversion efficiency of a TE material is
©EDA Publishing/THERMINIC 2009 203
ISBN: 978-2-35500-010-2

an increasing function of its TE figure of merit ZT.
Indeed, the non-dimensional ZT is given by ZT = S 2 σ T /
λ, where S, σ and T denote the Seebeck coefficient,
electrical conductivity and absolute temperature,
respectively [11,12]. Therefore, ZT is inversely
proportional to λ but directly proportional to the power
factor S 2 σ. Discovery of a material with ZT higher than 3
would result in a TE yield that is higher than 42 % of the
Carnot efficiency for hot and cold junctions at 800 K and
300 K, respectively [9,12]. Achievement of such a dream
would have an enormous impact for energy conversion
and renewable energies.
In this theoretical study, we investigate a novel type
of thermal membranous nanomaterials that is made up of
a thin dc Si membrane covered by stretched SA Ge QDs
with facets. The QDs are stretched in the [001] direction
with respect to the dc symmetry to form phonon
waveguides. The length L of the QD waveguides in the
stretching direction [001] is defined as larger than the
average phonon mean free path (MFP) in Si given by Λ 0
∼ 100 nm. In contrast, the QDs are constricted in the
orthogonal in-plane direction [100] with a bottom basis
B 0 that is several folds smaller than Λ 0 .
The anisotropic thermal conductivity λ of the QD
device is obtained in a membrane plane as a function of
the deflection angle β taken with respect to the axis x
parallel to the QD constriction direction [100]. The
throughput λ, when hot and cold junction are connected
to both sides of the membrane, is computed with 3D
lattice dynamics for β = 0° to β = 90°. The latter value is
related to the axis z parallel to the QD stretching direction
[001]. The discrete supercell to be encoded to obtain the
phonon dispersion curves is taken as a molecular slab of
the nanomaterial. Since L > Λ 0 , the slab has an out-ofequilibrium
width given by the Si lattice parameter a =
0.5431 nm in the direction z. To respect the dc
symmetry, four molecular planes with the same Miller
indices (001) have to be used to define the supercell slab.
The dispersion curves, computed by lattice dynamics
[13-15], show flat behaviors in the direction x owing to
QD constriction. Consequently, low phonon group
velocities are obtained in this direction leading to a small
throughput λ. In contrast, the slopes of the dispersion
curves are usually higher in the direction z so that the
stretched QDs form nanoscale phonon waveguides with
axes parallel to z. Indeed, the QD average length L is
large in z with L > Λ 0 . As a result, the throughput λ is
much larger in the direction z with respect to that x.
When hot and cold junctions are connected to the
membrane following z, the QD-waveguide nanomaterial
can be used for the design of efficient unidirectional
thermal interface devices for heat sinking. Indeed, the
leakage heat currents, which might affect thermal budget
7-9 October 2009, Leuven, Belgium
of other parts of a device to cool, are small owing to the
much smaller throughput λ in the in-plane orthogonal
direction x. The proposed membranous material presents
a hybrid behavior between thermal dissipation and
insulation. The operation regime depends on the heatflux
direction determined by the hot and cold junctions
with a connection angle β with respect to x.
Consequently, the same nanomaterial can be applied to
the design of heat sinkers and dissipaters as well as TE
generators and coolers.
In the following sections, using an example
molecular-scale QD-waveguide nanomaterial, we show
exaltation of the throughput λ by a significant factor of 4
to 5 folds (i.e. from 0.7 to 2.9 W/m/K) when the
connection angle β is increased from 0° to 90°,
respectively. The thermal transition between the
insulating and dissipative regimes is obtained for β = 45°
that is related to the in-plane close-packed direction
of the Si membrane.
II.
MODEL
To keep a membrane-like geometry, which is
responsible of directional effects on the thermal
conductivity, we set the length L of the stretched Ge QDs
in the in-plane direction z, or [001], as being of the order
or larger than the average MFP Λ 0 ∼ 100 nm of the
phonons in bulk dc Si, as depicted in Fig. 1(a). The QD
bottom basis B 0 in the in-plane x direction, or [100], is
defined as being several folds lower than Λ 0 . Therefore,
the QDs are stretched in the z direction with respect to the
orthogonal direction x so that they form phonon
waveguides. In the continuous-medium representation of
Fig. 1(b), the top basis of the QDs is denoted by B 1 while
d x is the length of a nanomaterial supercell in the QDconstriction
direction x. In the non-repetitive direction y,
or [010], the height of the dc Si membrane is h while that
of the Ge QDs is H.
The throughput thermal conductivity λ of the
suspended nanomaterial is computed from the dispersioncurve
diagram in a range from 0 to ∼ 20 THz using 3D
lattice dynamics and an incoherent approach of the
phonon scattering relaxation times. A discrete model is
derived from a supercell slab of the continuous-medium
representation sketched in Fig. 1(b). As shown in Fig. 2
where the red and blue dots denote the locations of Si and
Ge atoms, respectively, we encode a discrete supercellslab
model at the molecular scale for lattice-dynamics
calculations. Since L ≥ Λ 0 ≥ B 0 , the width in z of the
supercell slab, which is parallel to the crystallographic
plane with the Miller indices (001), can be taken as equal
to the Si lattice parameter a = 0.5431 nm. Since the dc
©EDA Publishing/THERMINIC 2009 204
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7-9 October 2009, Leuven, Belgium
crystals form a subset of the face-centered cubic (fcc)
group with a basis 2, four molecular planes with the
coordinates z = 0, z = a/4, z = a/2 and z = 3a/4 (before
binding energy relaxation) have to be utilized to define
the supercell slab as sketched in Fig. 2(a). The slab
section at z = 0 is displayed in Fig. 2(b). Since the space
domain is quantized with an interatomic lattice constant
a, the lengths d x = n x a, h = n y a, B 0 = μ a, B 1 = m x a, and
H = m y a are obtained from the integer size parameters n x ,
n y , μ, m x , and m y , respectively In the four planes with the
same Miller indices (001), the two QD facets are
assumed to follow close-packed directions of the
fcc crystals. As a result, they show a 45° deflection angle
with respect to the height axis y in Figs. 2(a) and 2(b).
From the precedent, the reduced bottom basis m of a QD
has to respect the equality μ = 2(m y -1) + m x . In this
theoretical study, we analyze an example hybrid
nanomaterial with the integer size parameters n x = 20, n y
= 4, m x = 5 and m y = 4 so that μ = 11. Since phonon
scattering is mainly incoherent for T > 5 K, the basis B 0
of the QDs can be modified and their centers offset (with
respect to the supercell median plane) by a fraction of the
quantity d x /2. Consequently, the overall thermal
conductivity of the altered system in x will remain (in
average) close to that of the periodic system. We also
note that the individual QD lengths in z can be quite
different if the inequality L > Λ 0 holds.
The throughput λ has to be minimized or maximized
for the hybrid thermal nanomaterial to operate in either
insulation or dissipation regimes. Getting one or the
other of these contra effects depends on the in-plane
propagation direction, with a deflection angle β with
respect to the membrane longitudinal axis x, as shown in
Fig. 1(b). For a material with a sufficient number of Ge
QDs, an anisotropic thermal conductivity λ β can be
physically defined as a function of the angle β. This is
the case when (i) the membrane is cleaved to form two
sides in a Miller plane parallel to the direction given by β
and (ii) hot and cold reservoirs are connected to the two
other membrane sides. For instance, the device in Fig.
1(a) is for a membrane with β = 90° since hot and cold
reservoirs are connected through the direction z while the
two lateral sides have to be cleaved with respect to the
(100) Miller plane (orthogonal to the x direction). When
β = 90°, the throughput λ is maximal since the QDs are
stretched in the z direction with L > Λ 0 to form phonon
waveguides. This case is different from that with β = 0°
in the QD-constriction direction x where the throughput λ
is minimal.
The key point to understand the directional effects in
our hybrid nanomaterial is to study the curve of the
anisotropic thermal conductivity λ β vs. β taken from 0° (x
direction) to 90° (z direction).
Si chip @ T h
(a)
(b)
z [001]
y [010]
SA stretched Ge QDs
L av Si thin membrane
y
z [001]
B 1
B 0
dc-Si
Si
dc-Ge
β
d x
x [100]
Si chip @ T c
Continuous supercell
Fig. 1 (colors). Hybrid insulating/dissipative nanomaterial:
(a) Cross section in (y, z) if the membrane is connected between hot
and cold reservoirs in the [001] direction (z) where heat dissipation
is maximal (W av being the average length of the QDs in z); (b)
Continuous-medium scheme of a nanomaterial supercell where β is
the average angle of the heat flux in a membrane plane with respect
to the [100] direction (x) showing constriction of the QDs. The
inequalities B 1 ≤ B 0 < Λ 0 have to hold in (b).
If we use polar coordinates (k, φ) taken from the origin
point of the 2D reciprocal space related to a direct plane
(x, z) of the 3D nanomaterial space, this curve is obtained
from:
λ =
β
π / 2
∫
0
+
[cos( β −φ)]
R(
φ)
dφ
+
π / 2
∫
0
2
sin[2( β −φ)]
P(
φ)
dφ.
π / 2
∫
0
[sin( β −φ)]
A(
φ)
dφ
In Eq. (1), the one-dimensional (1D) integration kernels
R(φ), A(φ) and P(φ), with the same metric unit [W/m/K
per radian], depends on the only independent variable φ.
They are obtained in a 2D reciprocal plane by prior
integrations over the radial coordinate k from 0 to the
location K(φ) on the boundary of the first 2D rectangular
Brillouin zone (BZ) for the azimuthal angle φ, as depicted
in Fig. 3(a). R(φ) and A(φ) are related to the square
amplitudes of the radial [ u m ( k,
φ)
] and azimuthal
[ v m ( k,
φ)
] phonon group velocities in the first 2D BZ,
respectively. The cross-term P(φ) in Eq. (1) is a
functional of the product u m ( k,
φ)
× v m ( k,
φ)
.
2
(1)
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7-9 October 2009, Leuven, Belgium
(a)
y [010]
x [100]
(b)
y [010]
Si
x [100]
z = 0 z = a/4
Ge
Si
z = a/2 z = 3a/4
B 0 = ma
Ge
B 1 = m x a
d x = n x a
H= m y a
h= n y a
Planes (001)
Plane (001)
With z = 0
1
A(
φ)
=
2
π h
1
P(
φ)
=
π h
N m
K ( φ)
(0)
2
∂nm
∑ ∫
[ vm(
)] τ m(
k)
ωm(
k)
∂
m= 1 0
( k)
k dk , (3)
T
N m
K ( φ)
(0)
∂nm
[ um(
k)
vm(
k)]
τ m(
k)
ωm(
k)
∂
m= 1 0
2 ∑ ∫
( k)
dk.
T
In Eqs. (2)-(4), k denotes the 2-tuple k = (k, φ), is the
reduced Planck constant, N m is the finite number of
eigenvalues (at k = 0) or 3 folds the number of atoms in a
nanomaterial supercell, ω m (k) are the quantized angular
frequencies from the dispersion curves, which are
computed by lattice dynamics in a reciprocal direction
(0)
given by φ in the harmonic case, n m ( k)
is the
equilibrium Bose-Einstein distribution of the phonons for
a system temperature T, and the membrane height is
given by h = n y a as in the precedent. The radial [Eqs. (2)
and (4)] and azimuthal [Eqs. (3) and (4)] group velocity
components are obtained in polar coordinates by partial
derivation of ω m (k) as u m = ∂ ω m(k)
/ ∂k
and v m =
( 1/ k )[ ∂ωm(
k)/
∂φ]
, respectively. The phonon relaxation
times τ m (k ) in Eqs. (2)-(4), derived from the relaxationtime
approximation of the Boltzmann transport equation,
are computed in an incoherent approach with the
Mathiessen rule using an addition of (non normalized)
scattering probabilities:
(4)
−1
( u)
−1
( s)
−1
[ τ m(
k)]
= [ τ m ( k)]
+ [ τ m ( k)]
. (5)
Fig. 2 (colors). Discrete-medium cross sections of a supercell slab:
In the four planes with z = 0, z = a/4, z = a/2 and z = 3a/4 used to
define a supercell slab for lattice-dynamics calculations, the red and
blue dots denote Si and Ge atoms, respectively (a). All planes of the
slab have the same Miller indices (001). In the plane (001) with z = 0
(b), the reduced parameters of an example molecular-scale device are
defined as n x = 20, n y = 4, m x = 5, m y = 4, and μ = 11 for Ge QDs with
45° facets.
As noted in Eqs. (2), (3) and (5), for R(φ), A(φ) and P(φ),
respectively, the 1D kernels in Eq. (1) also depends on
the scattering relaxation times τ m ( k,
φ)
and heat
capacities of the phonon eigenmodes given by the integer
indices m:
( u)
In Eq. (5), the umklapp relaxation time τ m ( k)
is
computed from a semi-analytical model presented in
Refs. [8,16]. Other incoherent scattering mechanisms are
( s)
denoted by the relaxation time τ m ( k)
. To compute the
latter, only incoherent scattering processes are considered
( s)
at the interfaces. From this hypothesis, τ m ( k)
can be
derived from the interface scattering cross sections as
1/ τ
( s)
m
( k)
= u ( k)/[
h + ( B / D ) H ]
m
with B = ( B0
+ B1)/
2.
x
(6)
Indeed, a membranous material without punctual defects
and dislocations is analyzed in this study.
1
R(
φ)
=
2
π h
N m
K ( φ )
(0)
2
∂nm
∑ ∫
[ um(
)] τ m(
k)
ωm(
k)
∂
m= 1 0
( k)
k dk , (2)
T
©EDA Publishing/THERMINIC 2009 206
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III.
RESULTS
A. Anisotropic dispersion curves
The definitions in the 2D reciprocal space of the
independent variables k and φ to obtain the throughput λ
are explained in Fig. 3(a). The 2D BZ is elongated by a
20-fold factor in the reciprocal direction k z with respect to
that k x . Indeed, the reduced length of the supercell slab in
x is given by n x = 20. The dispersion-curve diagrams for
φ = 0° (direction k x with k z = 0) and φ = 90° (direction k z
with k x = 0) are displayed in Figs. 3(b) and 3(c),
respectively.
(a)
(b)
φ = 0 o
K z =π/a
k
k = (0,0)
K(φ)
φ
K x =π/d x =π/(n x a)
7-9 October 2009, Leuven, Belgium
Different colors (blue, red, green, magenta and black
from the lowest to the highest frequencies) represent
different frequency ranges for the dispersion curves.
As shown in Fig. 3(b), the dispersion curves for φ =
0° are very flat leading to low radial group velocities
u m (k, 0) in the direction k x . In contrast, for φ = 90°, the
radial group velocities u m (k, π / 2) are usually much
higher than those obtained for φ = 0°. Indeed, as depicted
in Fig. 3(c), the slopes of the dispersion curves for φ =
90° are usually much larger than those for φ = 0° [Fig.
3(b)]. As a consequence, we can already expect from the
evolution of the dispersion curves a significant exaltation
of the throughput thermal conductivity λ in the direction
z (β = 90°) with respect to that x (β = 0°), as discussed in
the following.
B. Anisotropic thermal conductivity
For the example nanodevice presented in Figs. 1 and
2, a low λ β varying from only 0.7 to 1.0 W/m/K is
computed when β is increased from 0° to 24.4°,
respectively, as shown in Fig. 4. Since 1 W/m/K
corresponds (approximately) to the extreme low limit of
the thermal conductivity of bulk amorphous Si [17,18],
the hybrid nanomaterial can have a insulating behavior
when β ≤ 25°. Second, when β is increased from 26.6 to
90°, the material operation regime becomes more
dissipative since λ β grows, with a sigmoid curve, from
1.1 to 2.9 W/m/K, respectively.
(c)
φ = 90 o
Fig. 3 (colors). Phonon band diagrams with the definition of the polar
reciprocal coordinates k and φ (a) and dispersion curves obtained by
lattice dynamics for φ = 0° (b) and φ = 90° (c).
Fig. 4. Computed λ β vs. β curve with a sigmoid shape:
The hybrid nanomaterial is that in Figs. 1 and 2 at room
temperature T = 300 K. The circles, interpolated by the dotted line,
are values for fcc crystallographic directions with integer Miller
indices.
©EDA Publishing/THERMINIC 2009 207
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The regime transition at λ β = 1.7 W/m/K between the
thermal insulating and dissipative behaviors is obtained
when β = 45°. This value is related to the close-packed
directions in a membrane plane (for the fcc group). A
significant 4.1 exaltation factor of λ β is found out when β
is increased from 0° (x direction) to 90° (z direction).
IV.
CONCLUSION
A suspended thermal nanomaterial made up of a Si
membrane with stretched SA Ge QDs forming phonon
waveguides is proposed. A hybrid behavior, which can
be either insulating or dissipative is shown for thermal
transport in our nanomaterial. As a consequence, a wide
range of applications can be possibly covered by the
membranous nanomaterial from thermoelectrics to heat
sinking. Phonon wave-guiding is analyzed as a function
of an angle β in a membrane plane. This deflection angle
is defined from the in-plane direction [100], showing a
significant QD constriction, to that [001] of the QD
stretching. As observed from the dispersion curves
computed by lattice dynamics, the throughput thermal
conductivity λ is significantly increased in the direction
[001] with respect to that [100]. Numerical results show
that (i) the suspended nanomaterial has a thermalinsulating
behavior for moderate β-values while (ii) heat
dissipation is much more significant when β is increased
up to 90°. A significant exaltation factor of 4 to 5 folds is
obtained for the throughput λ between these operation
regimes for an example molecular-scale device.
7-9 October 2009, Leuven, Belgium
[8] J.-N. Gillet, Y. Chalopin, and S. Volz, ASME J. Heat
Transfer 131, 043206 (2009).
[9] J.-N. Gillet, and S. Volz, J. Electron. Mater., in press.
[10] J.-N. Gillet, Outstanding Scientific Paper Award, in Proc.
28 th International Conference on Thermoelectrics (ITC
2009), H. Bottner, Ed., Freiburg, Germany, 26-30 July
2009.
[11] W. Kim, J. Zide, A. Gossard, D. Klenov, S. Stemmer, A.
Shakouri, and A. Majumdar, Phys. Rev. Lett. 96, 045901
(2006).
[12] T. M. Tritt, H. Bottner, and L. Chen, MRS Bulletin 33,
366-368 (2008).
[13] M. T. Dove, Introduction to Lattice Dynamics,
Cambridge Topics in Mineral Physics and Chemistry, No
4 (Cambridge Univ. Press, Cambridge, UK, 1993).
[14] Z. Jian, Z. Kaiming, and X. Xide, Phys. Rev. B 41,
12915-12918 (1990).
[15] Y. Chalopin, J.-N. Gillet, and S. Volz, Phys. Rev. B 77,
233309 (2008).
[16] C. J. Glassbrenner, and G. A. Slack, Phys. Rev. 134,
A1058-A1069 (1964).
[17] D. G. Cahill, S. K. Watson, and R. O. Pohl, Phys. Rev. B
46, 6131-6140 (1992).
[18] C. Chiritescu, D. G. Cahill, N. Nguyen, D. Johnson, A.
Bodapati, P. Keblinski, and P. Zschack, Science 315, 351-
353 (2007).
ACKNOWLEDGMENT
The authors thank the European Consortium NANOPACK
(www.nanopack.org) for its financial contribution.
REFERENCES
[1] R. Venkatasubramanian, Ed., Nanoscale Heat Transport -
From Fundamentals to Devices, (Mater. Res. Soc. Symp.
Proc. Volume 1172E, Warrendale, PA, 2009).
[2] P. W. K. Rothemund, Nature (London) 440, 297-302
(2006).
[3] V. Maurice, G. Despert, S. Zanna, M.-P. Bacos, and P.
Marcus, Nat. Mater. 3, 687-691 (2004).
[4] A. Condon, Nat. Rev. Genet. 7, 565-575 (2006).
[5] C. R. Martin, and P. Kohli, Nat. Rev. Drug Discov. 2, 29-
37 (2002).
[6] A. I. Yakimov, A. V. Dvurechenskii, and A. I. Nikiforov,
J. Nanoelectron. Optoelectron. 1, 119-175 (2006).
[7] S. Kiravittaya, H. Heidemeyer, and O. G. Schmidt, Appl.
Phys. Lett. 86, 263113 (2005).
©EDA Publishing/THERMINIC 2009 208
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7-9 October 2009, Leuven, Belgium
Thermal Transient Measurements: the State of the Art
Vladimir Székely
BUTE, Hungary
Text unavailable at the time of printing.
©EDA Publishing/THERMINIC 2009 209
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Characterization of Metal Micro-Textured
Thermal Interface Materials
Roger Kempers 1,2 , Anthony Robinson 2 & Alan Lyons 1,2,3
1 Alcatel-Lucent
Blanchardstown Industrial Park
Dublin 15, Ireland
2 Department of Mechanical &
Manufacturing Engineering
Trinity College Dublin,
Dublin 2, Ireland
3 Department of Chemistry
City University of New York,
College of Staten Island
New York, USA
Abstract- To address performance limitations of conventional
thermal interface materials (TIMs), a metal micro-textured
thermal interface material (MMT-TIM) has been developed
that consists of a thin metal foil with raised micro-scale features
that plastically deform under an applied pressure thereby
creating a continuous, thermally conductive, path between the
mating surfaces. Here, the influence of various geometrical
parameters on the mechanical and thermal performance of
hollow conical MMT-TIMs is investigated experimentally. The
results demonstrate the influence of feature size, shape, array
density and foil thickness. The results also serve to highlight
the underlying challenge of characterizing the thermal contact
resistance of MMT-TIMs. Future efforts for this project are
discussed including the validation of a numerical thermalmechanical
model and development of a relationship between
electrical and thermal contact resistance for MMT-TIMs that
would allow estimation of the thermal contact resistance using a
straightforward electrical measurement.
I. INTRODUCTION
The mitigation of thermal contact resistance is essential to
the performance of conduction-based electronic thermal
management solutions. Typically the most feasible strategy
to reduce thermal contact resistance is to insert a thermal
interface material (TIM) of higher thermal conductivity
between the mating surfaces to conform to the contacting
surface asperities and displace any micro and macroscopic
air voids, thereby providing a path of improved heat
conduction.
To work effectively, TIMs must physically conform to the
mating surfaces under reasonable assembly pressures and
exhibit low contact resistance with adequate bulk thermal
conductivity. The bond-line thickness values are kept to a
minimum to help reduce bulk thermal conductivity, however
the thickness must be sufficiently large to enable the TIM to
comply to surface irregularities and non-planarities. For
assembly of microprocessors, where surfaces are relatively
smooth and flat, TIMs are thin. However for other
demanding applications, such as the assembly of high
powered wireless amplifiers where surfaces can be rough
and undulating, relatively thick TIMs are required to ensure
good contact across the entire surface. Many different TIMs
are commercially available that attempt to meet these
requirements in different ways. These include a range of
adhesives, greases, elastomeric pads and various phasechange
materials [1].
The main weakness of many commercially available TIMs
is their relatively poor thermal performance. Often the TIM
consists of a low-conductivity organic phase, such as
silicone grease, interspersed with higher conductivity metal
(e.g. silver, copper) or ceramic particles (e.g. aluminium
oxide, zinc oxide or boron nitride) to boost the overall
effective thermal conductivity of the material. The end
result is a material whose effective thermal conductivity is
limited by multiple point-to-point contacts between adjacent
particles. Despite using extremely high conductivity filler
materials, such as silver (k ≈ 420 W/m·K), the effective
thermal conductivity of the best commercially available
TIMs is on the order of 5 to 10 W/m·K, which is
considerably lower than the thermal conductivities of typical
mating components. In addition, dispensing and flow of the
particle-matrix composite results in voids being trapped
within the bond.
Indeed in many high thermal energy dissipating systems,
the TIMs can account for up to 50% of the available thermal
budget of the package [2]. With the inevitable
implementation of high performance liquid cooling
strategies, this percentage will become even greater. If the
thermal management of an electronic device is inadequate,
unacceptable temperature levels may be reached which can
adversely affect device performance, reliability and lifespan
[2]. These thermal issues have spawned a global effort
towards the development of novel TIMs with complex
formulation and very high performance [3-5].
To address these issues, a novel TIM has been developed
called metal micro-textured thermal interface materials
(MMT-TIMs) [6]. These materials consist of an array of
small-scaled raised metal features on a thin metallic
substrate. When this structure is compressed between two
mating surfaces, the features plastically deform and conform
to the contacting bodies as illustrated in Fig 1. This
approach reverses the conventional TIM paradigm by
creating two interpenetrating continuous phases – one of
high-conductivity plastically deformable metal features and
a second of an optional organic compound which flows
around these features. The constraint on thermal
©EDA Publishing/THERMINIC 2009 210
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F
F
A
B
Fig. 1: Metal micro-textured thermal interface material concept
conductivity imposed by multiple point-to-point contacts in
conventional TIMs is eliminated. In addition, the possibility
of void formation is significantly reduced since these microtextured
contact points are fixed in an array. Air voids,
which may become entrapped in the organic phase, will not
affect metal contact density. The result is an array of
conformable, yet continuous solid metal features of high
effective thermal conductivity that are in intimate contact
with the mating surfaces due to the plastic deformation of
raised features. Furthermore, by employing pure metals
such as copper, silver or aluminium, the features of the
MMT-TIM are both good thermal conductors and relatively
compliant.
A preliminary investigation characterized the performance
of an array of hollow silver cones (measuring approximately
2 mm tall by 1 mm diameter, on 2mm pitch) which exhibited
promising results with effective thermal conductivities up to
5 W/m·K. Furthermore, these MMT-TIMs demonstrated
significant compliance (up to 85% strain) with a relatively
constant application pressure. More importantly, the
effective thermal conductivity remained relatively constant
over a large deformation range [6]. Kempers et al. [6] have
also developed a numerical model that characterizes the
mechanical and thermal response of a given MMT-TIM
geometry during its compressive deformation.
The present study investigates the performance of several
different MMT-TIM feature geometries and presents some
experimental results that demonstrate the significance of
certain geometrical factors on both the mechanical and
thermal response of the MMT-TIM. Ultimately, this will
lead to a design tool that can be used to develop optimum
MMT-TIM geometries for a given set of criteria.
A
B
7-9 October 2009, Leuven, Belgium
contribute to a low overall uncertainty and a robust error
analysis provides uncertainties for all measured and
calculated quantities. Details regarding the design and
uncertainty analysis of this apparatus are provided in [7].
The temperatures at the meter-bar contact surfaces, T a and
T b , and the heat flux, Q, for each meter-bar were obtained by
performing least squares regression of the axial temperature
distribution to a straight line and computing the resulting y-
intercept and slope at the contact surfaces. As a result, the
uncertainty of T a , T b and Q depend on both the thermal and
spatial uncertainties of each thermistor. Details regarding
the uncertainty propagation through the least squares
regression are presented in [7].
The heat transfer rate through each meter-bar is then
computed by
Q m k A
mb mb
(1)
where m mb is the temperature gradient through each meterbar,
k mb is the thermal conductivity of each meter-bar, and A
is the cross-sectional area of the meter-bar.
The apparent thermal resistance of the TIM is then
calculated as
mb
=
R =
( T T )
a −
Q
(2)
where Q is the mean heat transfer rate through the meterbars.
The effective thermal conductivity of the TIM can then
be calculated using
QL L
keff = =
A( Ta
− Tb
) AR
(3)
where L is the thickness of the specimen bond line. The
decrease in sample height as they are compressed was
computed by subtracting the bondline thickness from the
initial height. Pressure is computed using the apparent
contact area of the apparatus (1600 mm 2 ).
III. MMT-TIM GEOMETRIES
The prototype MMT-TIMs investigated in the present
study were fabricated by first creating a 3D model of the
desired surface-negative using a conventional CAD package
(in this case ProEngineer). This form or mandrel was then
built in wax directly using a high-resolution wax 3D printer.
Silver was electroplated onto the wax mandrel to a desired
thickness and the wax subsequently removed. The resulting
b
II. EXPERIMENTAL APPARATUS
The design of the experimental apparatus was based upon
a popular implementation of ASTM D5470 where wellcharacterized
meter-bars are used to extrapolate surface
temperatures and measure heat flux through the sample
under test. Measurements of thermal resistance, effective
thermal conductivity, and electrical resistance can be made
simultaneously as functions of pressure and sample
thickness. This apparatus is unique in that it takes advantage
of small, well-calibrated thermistors for precise temperature
measurements (±0.001 K). Careful implementation of
instrumentation to measure thickness and force also
Fig. 2: Cross-section of hollow conical MMT-TIM geometry
©EDA Publishing/THERMINIC 2009 211
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7-9 October 2009, Leuven, Belgium
Fig. 3: Nominal feature geometries and measured dimensions of MMT-TIMs
MMT-TIM structure consists of an array of hollow metal
features and can be described as a textured metal foil. This
methodology allows for the creation of a wide range of
relatively detailed geometries. Furthermore, these geometries
potentially lend themselves to low-cost, high-volume
manufacturing techniques such as micro-stamping or
embossing, making this an attractive option for a costreduced
TIM.
Clearly, the scope of potential MMT-TIM geometries
is very large; however, for the present study, arrays of hollow
conical structures were investigated. An illustration of the
cross-section of a single cone indicating nominal geometrical
parameters is shown in Fig. 2. Here the important parameters
of the hollow conical structure can be described by the
overall feature height, base diameter, plating or foil thickness,
and pitch.
A description of the specimens tested for the present
study is presented in Fig. 3. Here, the sample name and
approximate nominal geometries are shown. Due to
resolution limitations of the wax 3D printer, this “idealized”
geometry is rarely realized as indicated by the accompanying
SEM image of the subsequently plated structures. The
dimensions listed correspond to the measured dimensions of
the final structures, corresponding to Fig. 2. Here,
approximate values of diameter and pitch were measured
using the SEM image and found to correspond well to the
designed geometry. Initial feature height was measured using
the experimental apparatus outlined previously. Foil
thickness was relatively difficult to control due to the plating
process with which the metal was deposited. However,
having once obtained the outer dimensions, the approximate
thickness was estimated by measuring the mass of the
sample. The volume of each unit-cell could then be obtained
by using the density of silver in conjunction with the
representative 3D CAD model. For the present study, feature
“B” in Fig. 3 served as the base-line case for which to make
comparisons to other geometries.
©EDA Publishing/THERMINIC 2009 212
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IV.
RESULTS & DISCUSSION
7-9 October 2009, Leuven, Belgium
7
A. Effect of Feature Height & Feature Size
The effect of feature height for two metal thicknesses was
compared between the nominal case of feature “B” and for a
conical structure of similar diameter and approximately twice
the height, designated as feature “A” in Fig. 3. The pressure
required to deform these structures is plotted as a function of
strain in Fig. 4. Here, all features exhibit a similar trend: the
pressure increases somewhat linearly until approximately
20% strain. Next there is a region of moderate plateau until
the structures begin to densify and the pressure rises steeply
between 70 and 80% strain. Overall, the thicker metal foil
requires a correspondingly larger pressure to deform to a
given strain for both feature heights. The trends and
magnitudes for the taller structure (feature “A”) correspond
well to that of a similar geometry investigated in [6]. The
taller feature (A) offers greater compliance than “B” as the
pressure required to achieve a certain stain (in the 20-70%
strain range) is approximately 20-25% lower.
The effect of overall feature size was also compared
between the nominal case of feature “B” and for a conical
structure half the diameter and approximately half the height,
designated as feature “F” from Fig. 3. From a mechanical
standpoint, the trend in compressive pressure for both
thicknesses of the half-sized MMT-TIM is extremely steep,
requiring significantly more force to be deformed to a given
strain than sample “B”. This can be attributed to two
reasons: First, ratio of pitch to diameter for both features is
the same, resulting in the MMT-TIM array of sample “F”
having four times as many features as sample “B”. Secondly,
while the outer dimensions of sample “F” are approximately
50% of “B”, the metal plating thickness remains the same,
thereby resulting in an overall stiffer structure.
From a thermal standpoint, the variation of effective
thermal conductivity with pressure for these MMT-TIMs is
plotted in Fig. 5. At low pressures, the effective thermal
conductivity of these structures is relatively low; indicating
the role of contact thermal resistance is dominant in this
3
keff (W/mK)
6
5
4
3
2
1
0
B1
B3
A1
A3
F1
F3
0 0.5 1 1.5 2 2.5 3
Pressure (MPa)
Fig. 5: Variation of effective thermal conductivity with pressure for
MMT-TIMs of different heights, diameters and metal thicknesses.
region. However, as the pressure is increased and the
structures undergo deformation, the effective thermal
conductivity of these structures increases significantly,
reaching a maximum of approximately 5.5 W/mK at a
pressure of 3 MPa for MMT-TIM “F1”. Generally speaking
the thicker metal-plated MMT-TIMs exhibited only a slightly
higher effective thermal conductivity at pressures in certain
regions of this curve, whereas for the most part, the thinner
MMT-TIMs demonstrated similar thermal performance for a
given pressure.
B. Effect of Pitch
The effect of feature pitch alone can be established by
comparing samples “B” and “D” from Fig. 3. A plot of their
respective stress-strain curves is shown in Fig. 6. Similar to
the result of sample “F” in Fig. 4, due to the four-fold
increase in the number of features being compressed, the
amount of pressure required to deform sample “D” to a given
strain increases dramatically over the baseline case.
From a thermal standpoint, the effective thermal
3
2.5
2.5
Pressure (MPa)
2
1.5
1
0.5
0
B1
B3
A1
A3
F1
F3
0 20 40 60 80 100
Strain (%)
Fig. 4: Variation of compressive pressure with strain for MMT-TIMs of
different heights, outer dimensions and metal thicknesses
Pressure (MPa)
2
1.5
1
0.5
0
B3 (p=2 mm)
D1 (p=1 mm)
0 20 40 60 80 100
Strain (%)
Fig. 6: Variation of compressive pressure with strain for MMT-TIMs of
different pitches.
©EDA Publishing/THERMINIC 2009 213
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7-9 October 2009, Leuven, Belgium
keff (W/mK)
8
7
6
5
4
3
2
1
0
B3 (p=2 mm) - k_eff
D1 (p=1 mm) - k_eff
D1 (p=1 mm) - RA
B3 (p=2 mm) - RA
0 0.5 1 1.5 2 2.5 3
Pressure (MPa)
0.001
0.0009
0.0008
0.0007
0.0006
0.0005
0.0004
0.0003
0.0002
0.0001
conductivity and specific thermal resistance are plotted as a
function of pressure in Fig. 7. Here, while the higher featuredensity
sample “D1” exhibits higher effective thermal
conductivity at all pressures, its overall thermal resistance it
actually higher in the upper pressure range. This is due to the
inability to compress the sample to as thin a bondline as
sample “B3” as indicated in Fig. 6.
C. Effect of Feature Shape
A direct comparison was made between the baseline case
of the circular-based hollow cone (sample “B”) and a squarebased
hollow pyramid of similar outer dimensions and
thickness (sample “C”). The variation of pressure as a
function strain is presented in Fig 8. Clearly, the squarebased
pyramid requires less force to deform to a given strain.
It is hypothesized this is due to stress concentrations that
exist where the sides of the pyramid meet as opposed to the
somewhat stiffer axisymmetric buckling that would occur in
the circular hollow cone as predicted by early model results
[6].
From a thermal standpoint, the pyramid structure exhibits a
Pressure (MPa)
Fig. 7: Variation of effective thermal conductivity and specific thermal
resistance with pressure for MMT-TIMs of two different pitches
3
2.5
2
1.5
1
0.5
0
0 20 40 60 80 100
Strain (%)
0
B3 (cone)
C1 (pyramid)
Fig. 8: Variation of compressive pressure with strain for two conical
and pyramidal MMT-TIM geometries of similar dimensions
RA (m 2 K/W)
keff (W/mK)
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
B3 (cone) - k_eff
C1 (pyramid) - k_eff
B3 (cone) - RA
C1 (pyramid) - RA
0 0.5 1 1.5 2 2.5 3
Pressure (MPa)
0.001
0.0009
0.0008
0.0007
0.0006
0.0005
0.0004
0.0003
0.0002
0.0001
Fig. 9: Variation of effective thermal conductivity with pressure for
conical and pyramidal MMT-TIMs
somewhat lower effective thermal conductivity over the
range of applied pressure, as illustrated in Fig 9. In terms of
specific thermal resistance, however, at low pressures, the
pyramidal MMT-TIM has a lower thermal resistance. At
higher pressures, the conical shaped MMT-TIM represents
the optimum geometry.
D. Thermal Contact Resistance of MMT-TIMs
These results serve also to highlight the main challenge in
characterizing the thermal performance of MMT-TIMs:
specifically distinguishing the bulk thermal resistance of the
MMT-TIM from the contact thermal resistance with the
meter bars of the test apparatus. Typically, for conventional,
homogeneous TIMs, the contact resistance can be
characterized experimentally by measuring several
thicknesses of TIM, plotting the thermal resistance as a
function of thickness and extrapolating contact resistance as
the y-intercept where the thickness is zero [8]. For MMT-
TIMs however, this method cannot be used due to the nonuniform
behaviour of the bulk TIM.
The specific thermal resistance of each TIM is plotted as a
function of pressure at 50% strain in Fig. 10. Overall, there is
a decreasing trend in thermal resistance, which demonstrates
that, generally, stiffer structures offer a lower overall thermal
resistance. This is indicative of the important role thermal
contact resistance plays in the thermal performance of these
TIMs. However, compliance is also required of thermal
interface materials to avoid exerting excessive stresses on the
mating parts. Thus a trade-off between thermal resistance
and compressive pressure exists. To this point, sample “D2”
exhibits over a 3 fold increase in compliance (i.e. reduction in
pressure required to achieve 50% strain) while exhibiting a
relatively small increase in thermal resistance (~0.00005
m2k/W)
The thermal contact resistance and electrical contact
resistance are qualitatively similar as both of these
phenomena depend on the ratio of actual, intimate contact
area to the apparent contact area [9, 10]. However, whereas
thermally the bulk resistances are on similar orders of
magnitude as the contact resistances, electrically the
0
RA (m 2 K/W)
©EDA Publishing/THERMINIC 2009 214
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RA (m 2 K/W)
0.0008
0.0007
0.0006
0.0005
0.0004
0.0003
0.0002
0.0001
0
C2
A3
C1
B3
D2
A1
B1
0 0.5 1 1.5 2 2.5 3
Pressure @ 50% Strain (MPa)
D1
F3
7-9 October 2009, Leuven, Belgium
measurements will be required. Future work will also involve
validating the simultaneous thermal-mechanical numerical
model developed by Kempers et al. [6] with this data.
Additionally, characterization the thermal contact resistance
of these MMT-TIMs as they deform is essential to
understating their performance and for the design of optimum
MMT-TIMs for a given application. Present work revolves
around understanding the relationship between electrical and
thermal contact resistance for these deformable metal
structures in order to develop a simple electrical
measurement to estimate the thermal contact resistance of
MMT-TIMs.
ACKNOWLEDGMENTS
This work was supported by IDA Ireland. Special thanks
to Paul Ahern of Alcatel-Lucent for the SEM imaging.
Fig. 9: Variation of specific thermal resistance with pressure at 50%
strain for each MMT-TIM
resistances of the bulk MMT-TIM are extremely small
compared to the resistance at the contact surfaces. For these
MMT-TIMs, it has been proposed that a relatively
straightforward electrical resistance measurement be
employed to characterize the thermal contact resistance [6,7].
Work is presently being carried out in order to characterize
the relationship between thermal and electrical contact
resistance of deformable metal structures for this purpose.
V. CONCLUSIONS & FUTURE OUTLOOK
Several different hollow conical MMT-TIM structures
were characterized experimentally. The results explore the
effect of various geometrical parameters such as metal
thickness, feature height, size, density and shape on both the
mechanical and thermal response of the MMT-TIM. Overall,
these parameters can exhibit a definite influence both the
thermal and mechanical response of the TIM.
Generally speaking, MMT-TIMs with thicker metal
plating (foil thickness) exhibit a stiffer mechanical response
and a slightly higher effective thermal conductivity.
Additionally, stiffer structures and MMT-TIMs with high
density feature arrays can exhibit higher effective thermal
conductivities but also higher thermal resistances due to
lower compressibility in the structure.
The best overall TIM performance was achieved
through a trade-off between effective thermal conductivity
and mechanical compliance. This was achieved with sample
“D2” where a dense array of conical features formed an
interface of multiple, redundant, thermal contacts. Due to the
thin metal plating, the features plastically deform relatively
easily providing good compliance and a large interfacial
contact area. Thicker metal plating does further reduce
thermal resistance of the MMT-TIM, but only at the price of
significantly higher assembly pressures.
The present work represents an initial exploration into
the effects of various MMT-TIM geometries on the
mechanical and thermal properties. Although some
performance trends were demonstrated, the tested structures
are far from optimal. Additional experimental structures and
REFERENCES
[1] Liu, J., Michel, B., Rencz, M., Tantolin, C, Sarno, C., Miessner, R.,
Schuett, K-V., Tang, X., Demoustier, S. & Ziaei, A., “Recent Progress
of Thermal Interface Material Research—An Overview”, Proceedings of
the 14 th Workshop on Thermal Issues in ICs and Systems
(THERMINIC), Rome, Italy, September 24-26, 2008
[2] Smith B., Brunschwiler, T., & Michel, B. “Comparison of transient and
static test methods for chip-to-sink thermal interface characterization”.
Microelectron. J., doi:10.1016/j.mejo.2008.06.079 (2008).
[3] Linderman, R., Brunschwiler, T., Smith B., and Michel, B. “High
performance thermal interface technology overview”. Proceedings of the
13 th Workshop on Thermal Issues in ICs and Systems (THERMINIC),
pp. 129-134 (2007).
[4] Ziaei, A. & Demoustier, S., “NANOPACK – Nano Packaging
Technology for Interconnect and Heat Dissipation”. Proceedings of the
14 th Workshop on Thermal Issues in ICs and Systems (THERMINIC),
Rome, Italy, September 24-26, 2008.
[5] Liu, J., Michel, B., Rencz, M., Tantolin, C., Sarno, C., Miessner, R.,
Schuett, K. V., Tang, X., Demoustier, S. & Ziaei, A. “Recent Progress
of Thermal Interface Material Research – An Overview”. Proceedings of
the 14 th Workshop on Thermal Issues in ICs and Systems
(THERMINIC), Rome, Italy, September 24-26, 2008.
[6] Kempers, R., Frizzell, R., Lyons, A. & Robinson, A.J., “Development of
a Metal Micro-Textured Thermal Interface Material”, ASME
InterPACK Conference, IPACK2009-89366, San Francisco, July 8-12,
2009
[7] Kempers, R., Kolodner, P., Lyons, A. & Robinson, A.J. “A High-
Precision Apparatus for the Characterization of Thermal Interface
Materials” Accepted to Review of Scientific Instruments, (2009).
[8] Teertstra, P. “Thermal Conductivity and Contact Resistance
Measurements for Adhesives”. Proceedings of ASME InterPACK 2007,
Vancouver, BC, July 8-12, 2007.
[9] Madhusudana, C.V., Thermal Contact Conductance, Springer-Verlag,
New York, (1996).
[10] Braunovic, M., Konchits, V.V. &Myshkin, N.K., Electrical Contacts:
Fundamentsl, Aplications and Technology, CRC Press, (2007).
©EDA Publishing/THERMINIC 2009 215
ISBN: 978-2-35500-010-2

7-9 October 2009, Leuven, Belgium
Carbon Nanotube Enhanced Thermally Conductive
Phase Change Material For Heat Dissipation
Xinhe Tang, Ernst Hammel and Werner Reiter
Electrovac AG
Aufeldgasse 37-39
3400 Klosterneuburg, Austria
Tel: 0043-2243-450405, Fax: 0043-2243-450315, tan@electrovac.com , www.electrovac.com
ABSTRACT
Carbon nanotube enhanced thermally conductive phase
change material for heat dissipation has been studied in the
present paper. It was indicated that the thermal resistance was
greatly reduced by incorporating multi-walled carbon
nanotubes into the organic matrix. The uniform distribution of
carbon nanotubes has been realized by optimizing the
dispersion parameters like temperature, shear strength, rolling
speed and gap of rollers. New phase change materials have
been developed and the thermal performance has been
evaluated. The further work relating to physical and
mechanical properties and application in heat dissipation is
being undertaken.
Key words: carbon nanotubes, nanofiller enhanced phase
change material, thermal performance, thermal resistance
I. INTRODUCTION
An organic phase change material (PCM) shows thermal
storage capacity due to its latent heat of transformation, but its
application in thermal management is limited owing to its low
thermal conductivity. It is expected that embedding a thermally
conductive nanofiller in the PCM matrix can either increase the
thermal conductivity of the composite or decrease the thermal
resistance, and therefore reduce the junction temperature of the
components.
Carbon nanotubes (CNTs) possess high thermal conductivity
in the axis direction. An individual multi-walled carbon
nanotube (MWCNT) can be as high as 3000 W/mK in thermal
conductivity [1]. The CNTs with their outstanding conductivity
have a great potential to be employed in PCM for heat
dissipation. It is believed that the high inherent thermal
conductivity of CNTs significantly enhances the thermal
conductivity of the PCM. It was indicated that the thermal
grease made from carbon nanofibers (CNF) showed low
thermal resistance in the previous work [2-3]. It has been
reported that CNT arrays lead to a minimum thermal
resistance of 19.8 Kmm 2 /W, while the combination of the CNT
arrays with phase change material results in much lower
resistance of 5.2 Kmm 2 /W [4]. The dispersion and the
formation of a network of CNTs in the matrix, the loading
grade of the fillers, the manufacture process and even the
properties of the matrix itself exert an important influence on
the thermal performance of the PCM.
The objective of this work is to develop nanofiller enhanced
phase change material by finding out desirable compositions
where CNTs and matrix may well be incorporated, and by
optimizing dispersing parameters to generate minimum thermal
barriers between nanofillers and matrix and to realize a
maximum thermal conductivity of the phase change material.
In the present work following activities have been involved in
developing CNTs enhanced PCM:
• Selection of PCM matrices and filler materials;
• Pre-treatment of carbon nanotubes;
• Optimization of dispersion parameters;
• Optimization of loading grade of CNTs;
• Evaluation of CNTs distribution in PCM;
• Measurment of the thermal resistance of the PCM;
• Comparison of the enhancement over the matrix;
II. EXPERIMENTAL
1. Selection of carbon nanofibers as filler
It has been reported that the thermal grease made from heattreated
carbon nanofibers showed lower thermal resistance than
any other non-treated CNF and CNT[2]. A multi-walled carbon
nanotube was treated at high temperature and used as the filler
to enhance the thermal performance. Fig. 1 shows the SEM
morphology of this filler material. As many nanoparticles, the
carbon nanotubes are also strongly agglomerated, which shows
the difficulty to be well dispersed into the organic matrix.
Fig. 1: SEM morphology of multi-walled carbon nanotube
2. Selection of organic phase change material
The following properties have been taken into account to
select organic PCM:
©EDA Publishing/THERMINIC 2009 216
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• Low thermal resistance;
• Good wetting with carbon nanotubes;
• High latent heat of fusion;
7-9 October 2009, Leuven, Belgium
Table 1 gives a list of organic PCM and their melting range.
The thermal resistance of these PCMs is measured and given in
this table too. Polyethylene glycol (PEG) with different
molecular weight is also used as the matrix material and PEG-
1000, PEG-1500 and PEG-2000 show much lower thermal
resistance by themselves than lauric acid and tetradecanol
which are typical PCMs. The melting range of PEG increases
with increase of molecular weight. PEG-2000 shows a melting
range from 45°C to 50°C.
Table 1: Selection of organic PCM and thermal resistance
3. Preparation of CNT reinforced phase change material
Following processes were involved in making CNT
reinforced phase change material (CNT-PCM):
• Melting the organic PCM;
• Pre-mixing CNT with PCM;
• Dispersing CNT into PCM;
• Studying Rth change with dispersing time;
In order to generate minimum thermal barriers between
nanofillers and PCM, the dispersion parameters have to be
optimized. The PCM matrix was melted and then was mixed
with CNTs using dual asymmetric centrifuge (DAC) followed
by dispersion procecess. The dispersion of CNTs into PCM
matrix was completed using three rolling mill. The parameters
such as shear strength, temperature, gap of rollers and rolling
speed were optimized. Nanofiller reinforced phase change
material has been prepared by selecting a desirable organic
PCM and embedding CNTs into the matrix under optimized
dispersing condition.
4. Measurement of thermal resistance of PCM
Fig. 2 shows a schematic set-up for evaluating thermal
resistance of CNT-PCM. It is comprised of a heater, a cooler
and two Cu-bodies with diameters of 40mm. The top-body is
soldered to the heater, while as the bottom-body is connected
to cooling water to remove the heat. Pressure is applied by a
cylinder.
The CNT-PCM is placed on the surfaces of the well
polished copper body. A pressure 400N is applied to the
system. The temperature difference is recorded after 10 min of
operation. The bondline thickness (BLT) is indicated using
Mitutoyo Gauge ID-C. The thermal resistance R th is measured
Fig. 2: Schematic set-up for R th measurement
by the temperature difference between the two copper bodies
devided by input power.
III.
RESULTS AND DISCUSSIONS
1. Evaluation of CNT dispersion into PCM
CNT dispersion in PCM can be evaluated by observing the
cross-section of CNT-PCM by SEM. The strongly
agglomerated CNTs can be seen if they are not well dispersed
into the PCM. The feed material of CNTs are strongly
agglomerated like peanut shell (see Fig. 1) and it can be well
dispersed into the PCM using the process developed in this
work. Fig. 3 and Fig. 4 show the SEM mophologies of the
cross-section of CNTs in PEG-2000 and in lauric acid
respectively. No more strongly agglomerated carbon
nanotubes can be observed by SEM, which indicates that CNTs
are uniformly dispersed into these PCMs.
Fig. 3: Dispersion of carbon nanotubes in PEG-2000
Fig. 4: Dispersion of carbon nanotubes in lauric acid
2. Dependence of thermal resistance on dispersing time
The influence of dispersing time on thermal resistance of
CNT-PCM has been studied. Fig. 5 shows the Rth-dispersing
©EDA Publishing/THERMINIC 2009 217
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7-9 October 2009, Leuven, Belgium
relation of CNT in PEG-1000. It can be seen that the thermal
resistance decreases gradually with increasing dispersing time.
Fig. 6 shows the Rth-mixing time for embedding CNT into
tetradecanol. The R th decreases slowly within the first 20
minutes. Afterward R th drops from 0.03K/W to 0.022K/W in
next 10min, and it decreases further to 0.021K/W after 1h
dispersion. The reduction of R th directly reflects the
distribution of CNTs in the PCM matrix. The longer the
dispersing time is, the more uniform the CNTs distribute,
which was also approved by SEM (see Figs. 3 and 4).
Fig.8: R th comparison of CNT enhanced PCM
Fig. 5: R th Change with dispersing time for CNT-PEG1000
IV. CONCLUSIONS
The present study indicates that the thermal resistance of
organic phase change materials can be greatly reduced by
incorporating multi-walled carbon nanotube into matrix. The
uniform distribution of carbon nanotubes is realized by
optimizing the dispersion parameters like temperature, shear
strength, rolling speed and gap of rollers. Carbon nanotube
enhanced thermally conductive phase change materials have
been developed. The further study including physical and
mechanical properties and application in heat dissipation is
being undertaken.
ACKNOWLEDGMENT
This work was partly financially supported by the 7 th
Framework Program of EU Nanopack (Project No. 216176,
Nano Packaging Technology for Interconnect and Heat
Dissipation).
Fig. 6: R th Change with dispersing time for CNT-Tetradecanol
3. R th comparison of CNT in different PCM
Figs. 7 and 8 give R th comparison before and after
embedding CNT into matrices. Only slight decrease in R th
can be achieved after dispersing CNT into PEG-1000, PEG-
1500 and PEG-2000, while an obvious reduction in R th is
realized by dispersing CNT into PEG-600 (see Fig. 7). From
Fig. 8 it can be seen that lowest R th (0.018K/W) is achieved by
embedding CNT in lauric acid. More than 40% reduction in R th
has been obtained for matrices lauric acid and 1-tetradecanol
respectively. The reduction as high as 50% has even been
realized for undecylenic acid.
Fig.7: Rth comparison (CNT-PEG system)
REFERENCES
[1] P. Kim et al., “Thermal transport measurements of
individual multiwalled nanotubes”, Phys. Rev. Lett.
87, 215502 (2001)
[2] X. Tang, E. Hammel et al, “Study of Carbon
Nanofiber Dispersion for Application of Advanced
Thermal Interface Materials”, Proceedings of 1 st
Vienna International Conference Micro-and Nano-
Technology, 395-400, March 9-11, 2005, Vienna,
Austria
[3] E. Hammel, X. Tang et al, “Performance of Carbon
Nanofiber Based Thermal Grease”, IMAPS Advanced
Technology Workshop on Thermal Management for
High-Performance Computing and Wireless
Application, Palo Alto, CA, USA, Oct.24-26, 2005
[4] Xu et al, “Enhancement of thermal interface materials
with carbon nanotube arrays”, International Journal
of Heat and Mass Transfer , Vol. 49, N o 9-10, (2006),
pp. 1658-1666
BRIEF BIOGRAPHY
The principal author, Dr. Xinhe Tang has joined Electrovac
AG since 2000. He focuses currently his work on the research
and development of new products such as thermal interface
materials and bonded copper/ceramic substrates. He
participates in the EU project “Nanopack” and leads the second
work package “Development of materials”.
©EDA Publishing/THERMINIC 2009 218
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7-9 October 2009, Leuven, Belgium
Method for In-Situ Reliability Testing of TIM
Samples
Andras Vass-Varnai, Zoltan Sarkany, Marta Rencz
Mentor Graphics Hungary Ltd.
MicReD Division
e-mail: @mentor.com
In this paper a possible method demonstrated for in-situ
reliability testing of various TIM materials. The method is based
on thermal transient measurements of a power semiconductor
device in a TO-type package which has a flat, external cooling
surface. By powering the junction of the semiconductor cyclically
the whole assembly is exposed to intense thermal cycles in which
the main heat-flow path leads through the TIM material. May the
quality of the TIM change during the cycles the maximum
junction temperature also changes.
I. INTRODUCTION
With the always growing speed and integration densities of
electronic circuits their thermal management is becoming a key
task in thermal engineering. The increasing power results in
increasing temperature in the chip that first just modifies, later
destroys the operation of the circuit, if the heat is not
appropriately lead out of the chip. The heat transfer to the
outside world can be improved by better heat sinks, higher air
velocities and liquid cooling if the application allows it. But the
heat first has to reach the surface of the package, and the
efficiency of this heat transfer depends on the conductivity of
the package itself, and the interface thermal resistance that is
defined as the sum of the thermal resistance of the interface
material (TIM) plus the contact resistances. The thermal
interface between the outside cooling structures also has to be
improved by TIM materials as their connections are thermally
far from perfect. Based on these facts the lifetime of a device
strongly depends on the long term reliability of the TIM
materials in the cooling assembly.
somewhat less demand for accuracy. As a powerful tool to
observe any changes in the heatflow path the JEDEC JESD51-
1 static electrical test method can be used [5] and enhanced by
mathematical calculations; mapping over the heat-flow path
from the electrically excited junction to the ambient by means
of thermal resistances and thermal capacitances.
II.
MEASUREMENT ARRANGEMENT
In the proposed test arrangement the TIM material is put
between the external cooling surface of a power
semiconductor device and a heat-sink. The semiconductor is
fixed to the surface of the heat-sink by constant force. This
force is maintained by a special fixture, as it can be seen in
Fig 1. The highest temperature elevation and the total
junction-to-ambient thermal resistance of the assembly are
characterized at the device’s operating parameters to get
reference values.
Our goal with this work is to monitor any changes of TIM
performance after repeated reliability tests. Unfortunately due
to many physical problems, the testing of TIM materials is not
a straightforward task [2]. Commonly accepted laboratory test
methods such as transient thermo reflectance measurement [3],
direct thermal diffusivity measurement or the 3 omega method
[4] are versatile and precise characterization tools however
they are not applicable for in-situ measurements. To
characterize the TIM performance in a given electronics
application, e.g. to see the change of the Rth value of a TIM
layer after reliability testing raises new requirements: these
measurements have to be very fast in situ measurements with
Fig 1. : Special fixture to mount the power semiconductor on the cooler
surface by constant force
This type of test is aimed at the evaluation of the durability
of TIM materials for temperature cycling, induced by power
cycles. The temperature of the surface of the cold-plate can
be set and maintained at any temperature between 5 to 100°C.
The measurements are carried out with a thermal transient
tester and its high power accessory. The high power
excitation which results in the temperature rise in the device
is provided by the accessory. After reaching hot thermal
steady state, the high power is switched off and the cooling
©EDA Publishing/THERMINIC 2009 219
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transient is measured by the transient tester. Such test
conditions resemble the normal operation of the device: if the
quality of the TIM gets worse, the same powering results in
higher junction temperatures in each cycle.
May other failures occur in the device under test, the
measurement results unfold them, too. As the resulting
functions of the thermal transient measurements yield us
structural information of the whole cooling assembly,
especially near the junction, beside the changes of TIM
performance even die attach failures can be noticed this way.
III.
EXPERIMENTAL
In order to evaluate the above discussed test method, we
conducted tests on 8 different TIM samples. As a heater
element a PNP type power transistor was used in TO-220
type package. The package was fixed on a cold-plate as stated
before. The powerwstep required for the measurements was
generated using the so-called voltage step method. A
constand 2A current was forced through the open transistor,
while the base-collector voltage was switched in 1 µs
between -1V and -10V. Once the powerstep took place the
base-emitter voltage was used as a temperature sensitive
parameter to measure the temperature response. The power
step was 18.2 W, and the sensitivity of the transistor resulted
in -1.1 mV/°C.
All measuerements lasted for 20 seconds. It took 10
seconds for the junction of the transistor to heat up
completely and it also took 10 seconds to cool down.
The thermal behaviour of 8 different TIM samples were
investigated , however as most of them showed very similar
results, therefore not all resulting graphs are presented in this
paper. The list and composition of the TIM materials used
for this study is summarized in Table 1.
Sample
ID.
Filler
Matrix
TIM-1 CNT diluted epoxy
TIM-2 Al micro-particles silicone
TIM-3 CNT + graphite diluted epoxy
TIM-4 CNT + graphite solvent
TIM-5
graphite + metal
powder
resin
TIM-6 CNT epoxy
TIM-7
silicone grease
TIM-8 CNT epoxy
7-9 October 2009, Leuven, Belgium
In order to evaluate the results three views were used. The
most straightforward way to see the difference between two
measurements is to compare the transient responses. The
transients should run together until the time point where the
main trajectory of the heat leaves the package boundary and
enters the grease layer. The difference between the total
elevations should show the the change of the thermal resistance
of the TIM material unless any other structural element
changes its thermal properties in the heat-flow path.
Fortunately this can be easily verified using the structure
functions.
Generated from the transient results using a mathematical
procedure called the NID method [6], the structure functions
represent the heat-flow path from the place where the power
step takes place (so-called driving point) towards the
environment. Both the thermal resistance of each strucure in
the heat-flow path and the the thermal capacitance of the
corresponding layer in which the heat spreads can be identified
this way. Due to the extremely high repetability of the thermal
transient method [7] while the heat flows in the same structure,
the structure functions are exactly the same. If the structure of
the heat-flow path changes the difference immediately appear
son these functions, showing the exact location (thermal
resistance value) and magnitude (thermal capacitance value) of
the change. Hence with the help of the structure functions it
can be made sure that it is really the TIM material which
changes its thermal resistance in the assembly, or not.
As in the beginning for each TIM material 2500 cycles were
performed and the cooling transient for each cycle was
captured, using the tansient response - and structure functious
only it is impossible to show trends. In order to overcome this
problem, the temperature difference between an early point of
the transient and the highest elevation was plotted after each
measurement:
Table 1. list of thermal interface materials used in this
Study
The surface of the heat-sink was set to 40°C during all
measurements. This allowed the junction temperature to rise
up to app. 120 °C in each cycle, of course this value may
change a bit depending on the TIM.
Figure 2. Tendency of the final temperature of the junction using TIM-1
(raw data above, smoothed data below)
Figure 2. clearly shows how the repeated power cycles
make the thermal resistance of the TIM material lower and
lower until app. after 1500 cycles the material stabilizes.
Along the x axis the number of the samples can be followed,
while the y axis shows the final difference between the
temperature elevation at a very early time of the transient and
the final temperature value. The data is first expressed in bits
©EDA Publishing/THERMINIC 2009 220
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7-9 October 2009, Leuven, Belgium
which can be transferred to voltage and temperature values if
necessary using the following equation:
T=Bits*LSB/K, (1)
Where T is a temperature value counted from a reference
point, LSB is the resolution of the tester, which is 24.4µV in
our case. K is the temperature sensitivity value of transistor.
Using the equation and reference values above, it can be
calculated that the temperature change during all of these
cycles is app. 6.5°C in case of TIM-1. By plotting some
transient curves and comparing them, this value can be
directly read from the transients.
T3Ster Master: Smoothed response
Temperature rise [°C]
70
60
50
40
30
20
TIM_1_3_2500_aver.0001 - Ch. 0
TIM_1_3_2500_aver.0500 - Ch. 0
TIM_1_3_2500_aver.1000 - Ch. 0
TIM_1_3_2500_aver.2500 - Ch. 0
Fig 4. : Zoomed view of Fig 3.
10
0
0.001 0.01 0.1 1
Time [s]
Fig 3. The thermal behavior of TIM 1 material after 1, 500, 1000 and 2500
heating cycles
The results indicate that the heat-flow path after the first
cycle has the highest thermal resistance. After cycle 500 the
TIM material significantly becomes better, no big changes
can be observed anymore.
Fig 4 shows that the temperature difference between cycles
1 and 500 and above is already 4.5 centigrade.
The evaluation of the measured data after each cycle
suggests that the TIM4 sample is reliable on the long run
even though it changed a bit in the initial 500 cycles, it just
became better. This result also verifies the measurement
arrangement; applying this methodology, very small
differences can be revealed in the heat-flow path; moreover
the measurement itself is carried out with extremely high
repeatability, as the temperature transient curves clearly fit
each other up to 0.3 seconds.
In order to see whether the change is really caused by the
TIM material’s property changes the structure functions can
reveal the truth. Fig 5. shows that the structure functions
generated by the transients in Fig 3 run together up to above 3
K/W, which is over the junction-to-case thermal resistance
value of the transistor used for this study. As it is proven that
the structure of the heater transistor has remained
unchainged, the temperature drop is obviously caused by the
property change of the TIM layer.
Fig 5. Cumulative structure functions of TIM 1 material
Most of the materials (e.g. silicone grease) showed similar
behaviour, i.e. their thermal resistance decreased after the
cycles. During the first 500 cycles the matrix rearranges
itself, which results in probably lower contact resistance.
After the first app. 500 cycles the change becomes less
significant, the assembly is close to stabilization.
Some materials don’t change at all, or the change is close to
the noise level.
61,20
61,00
60,80
60,60
60,40
60,20
60,00
59,80
59,60
59,40
59,20
0 500 1000 1500 2000 2500
Fig 6. Tendency of the final temperature of the junction using TIM-4
©EDA Publishing/THERMINIC 2009 221
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7-9 October 2009, Leuven, Belgium
Fig 6. gives the tendency of TIM 4 material during 2500
cycles. Although some clear increase can be observed in the
temperature up to 1000 cycles followed by a slight diminish,
the maximum change during all 2500 measurements is less
than 0.4 °C. Practically after finishing the test the junction
temperature remains unchanged, the TIM 4 material is
reliable. To make sure that the pattern on Fig 6 is not a
summary of two effects, i.e. the change of the structure of the
heater transistor plus the change of the TIM, it is worth to
check both the transients and the structure functions.
T3Ster Master: Smoothed response
61,60
61,40
61,20
61,00
60,80
60,60
60,40
1 195 389 583 777 971 1165 1359 1553 1747 1941 2135 2329
Temperature rise [°C]
60
50
40
30
20
10
0
TIM4_repeat2500.0001 - Ch. 0
TIM4_repeat2500.0500 - Ch. 0
TIM4_repeat2500.1000 - Ch. 0
TIM4_repeat2500.1500 - Ch. 0
TIM4_repeat2500.2000 - Ch. 0
TIM4_repeat2500.2500 - Ch. 0
0.001 0.01 0.1 1
Time [s]
Fig 7. Transient results of TIM 4 sample after 1, 500, 1000 , 1500, 2000 and
2500 cycles
T3Ster Master: cumulative structure function(s)
Cth [Ws/K]
100
10
1
0.1
0.01
TIM4_repeat2500.0001 - Ch. 0
TIM4_repeat2500.0500 - Ch. 0
TIM4_repeat2500.1000 - Ch. 0
TIM4_repeat2500.1500 - Ch. 0
TIM4_repeat2500.2000 - Ch. 0
TIM4_repeat2500.2500 - Ch. 0
0.001
1.5 2 2.5 3 3.5
Rth [K/W]
Fig 8. Structure function view of the transient responses shown in Fig 7.
Very similarly to the TIM 1 material both functions are
exactly the same on a large time and thermal resistance range.
They indicate that during the measurement the structure of
the transistor has not changed at all, the effect is
characteristic to the TIM 4 material.
Beside decreasing and stabile trends some materials also
showed some small degradation, at least in terms of thermal
resistance. Materials TIM 3 and TIM 6 are good examples of
this behavior. The slight degradation of TIM 3 during the
cycles can be observed in Fig 9.
Fig 9. . Tendency of the final temperature of the junction using TIM-3
The corresponding structure functions are not shown in the
present paper, however they are in very good correlation with
the results in Fig 9 and they diverge above the junction-tocase
thermal resistance of the transistor.
The behavior of the other materials also follow the
tendencies shown before, for this reason their graphs are not
included, only the trends are listed in Table 2. Beside the
trend (direction of the junction temperature change) and the
cycle number of the stabilization, the maximum temperature
change is also listed.
Sample
ID
Trend in
Rth
Max.
Temp. Diff.
[°C]
TIM-1 decreasing 6,5
TIM-2 decreasing 0,86
TIM-3 increasing 1,1
TIM-4
increasing
up to app.
1000 then
slightly
decreasing
Stabilization
app. 1500,
but still
diminishing
app. 2000,
but still
diminishing
app. 2000,
but still
increasing
stabile, on
the whole
range within
the noise
level
TIM-7 decreasing 1,47 app. 250
TIM-8 decreasing 2,47 1000
Table 2. Resulting trends and maximum temperature changes for TIM
materials listed in Table 1
Even though the temperature change is not large during
2500 cycles, the small changes can be measured very well.
The resolution of the measurements is 0.02 °C in this
measurement range, which is adequate for this purpose.
0,4
TIM-5 decreasing 1,2 app. 1500
TIM-6
decreasing
up to 150,
then
linearly
increasing
0,78 no
©EDA Publishing/THERMINIC 2009 222
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IV.
SUMMARY AND CONCLUSIONS
7-9 October 2009, Leuven, Belgium
The methodology discussed in this paper is aimed at the insitu
reliability testing of TIM materials with a special
emphasize put on the thermal properties. The temperature
change of a probe was selected as an output signal which is in
correspondence with the thermal resistance of the TIM
material. This special power cycling test resembles the real
application and makes it possible to track the TIM property
changes “online”, without changing the thermal system.
[4] D.G. Cahill. Rev. Sci. Instrum. 62 2 (1990), p. 802
[5] www.jedec.org/download/jedec/jesd51-5.pdf
[6] V. Székely, Identification of RC Networks by Deconvolution:
Chances and Limits, IEEE Transactions on Circuits and Systems-I.
Theory and Applications, CAS-45 (3):244-258, 1998
[7] Rencz M., Székely V.,: Measuring partial thermal resistances in a
heat flow path, IEEE Transactions on CPT, Vol 25,No 4, Dec.
2002, pp 547-553
The tests were conducted on 8 different materials and gave
three types of tendencies as results. Some materials became
significantly better during the power cycles showing no sign
of reliability problems. A small number of materials either
kept their initial characteristics or slightly became worse. As
most of the materials showed some clear change in their
thermal properties, it may be important to track these changes
and have them appeared in some form in their datasheets.
This would enable the users to predict the long-time behavior
of their thermal systems.
The thermal transient methodology combined with the NID
mathematical method is a perfect way for this type of
characterization. The fine temperature resolution enables the
user to generate tendencies, while the structure functions
serve as a great tool to make sure whether the change
originates from the TIM material or not. If the temperature
probe is correctly chosen, the time period of a cycle is very
short, 2500 cycles were measured and recorded in less than
14 hours.
This methodology may also be suitable to evaluate other
type of reliability tests, too. On the long run we plan to
evaluate the effect of temperature cycling and HAST tests for
TIM reliability for similar measurements.
ACKNOWLEDGMENT
The authors would like to express their acknowledgements
to Electrovac A.G. for providing the TIM samples for
testing. This work was supported by the NANOPACK FW7
No. 216176/2007 IP Project of the EU.
REFERENCES
[1] A. Vass-Várnai, M. Rencz: “Testing interface thermal resistance”,
In: Proceedings of eTherm'08 - The 1st International Symposium on
Thermal Design and Thermophysical Property for Electronics.
Tsukuba, Japan. 2008. pp. 73-76.
[2] Lasance, C.J.M.; Murray, C.T.; Saums, D.L.; Rencz, M.
“Challenges in thermal interface material testing”, Semiconductor
Thermal Measurement and Management Symposium, 2006 IEEE
Twenty-Second Annual IEEE Volume , Issue , 14-16 March 2006
Page(s):42-49, Digital Object Identifier
10.1109/STHERM.2006.1625204
[3] Burzo, M.G.; Komarov, P.L.; Raad, P.E, Optimized thermoreflectance
system for measuring the thermal properties of thinfilms
and their interfaces, Semiconductor Thermal Measurement
and Management Symposium, 2006 IEEE Twenty-Second Annual
IEEE Volume , Issue , 14-16 March 2006 Page(s):87 – 94,DOI:
10.1109/STHERM.2006.1625211
©EDA Publishing/THERMINIC 2009 223
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7-9 October 2009, Leuven, Belgium
Progress in Thermal Characterisation Methods and
Thermal Interface Technology within
the “Nanopack” Project
B. Wunderle 1,2 , M. Abo Ras 1,3 , M. Klein 1 , R. Mrossko 1 , G. Engelmann 1 , D. May 1 ,
O. Wittler 1 , R. Schacht 1,4 , L. Dietrich 1 , H. Oppermann 1 , B. Michel 1
1 Fraunhofer Institute Reliability and Microintegration, Gustav-Meyer-Allee 25, 13355 Berlin, Germany
Email: bernhard.wunderle@izm.fraunhofer.de
2 Technische Universität Chemnitz, 09107 Chemnitz, Germany
3 Berliner Nanotest und Design GmbH, 12489 Berlin, Germany
4 University of Applied Sciences Lausitz, 01968 Senftenberg, Germany
As the demand for new thermal technologies and
materials has been increasing over the years to provide
thermal solutions to the next generation of power
electronics, microprocessors and high-power optical
systems also thermal characterisation methods have to
keep up with the pace of this development with respect to
resolution and accuracy. Within the EU-funded project
“Nanopack” we have developed both bulk and interface
technologies to reduce thermal resistance using Ag-based
materials and low-T and low-p processes to render them
eligible for the electronics industry. New processes to
generate nano-enhanced surface structures as well as
thermo-compression bonding are examined within this
paper. Along with these processes especially designed test
stands are described which are able to extract the effects
achieved by the technological advances.
I. INTRODUCTION
Thermal interface material resistance represents one of the
major bottlenecks in advanced thermal packaging solutions.
Over the last couple of years this trend has become more and
more apparent as well as the need for new developments in
advanced thermal technology [1-3].
Part of the thermal resistance is governed by the thermal
conductivity of the material, another is determined by the
interface resistance [4,5]. So development for advanced
thermal technology has to focus on an understanding of heat
transfer across bulk and interfaces of thermal interface
materials (TIMs), the infuences of processing conditions and
– as a necessary requirement for progress – their accurate
characterisation [4-8].
Whereas the bulk thermal conductivity of greases or
adhesives using filler particles of different materials, size,
shape and modality has been showing some improvement
over the last few years, the interfaces have received much
less attention, although at thin bond line thicknesses (BLT)
they have a major influence on heat transfer [5,6,9]: The
particle density is usually lower at the interface and
boundaries of dissimilar materials reduce the heat transfer
across the interface [5]. This is also due to processing
conditions [10]. In order to overcome these inherent limits,
various technological approaches have been tried [9,10].
We have developed and applied different surface
modification methods to create structures which could
enhance heat transfer across the interface to e.g. a particlefilled
adhesive. Different approaches were tested to create
nano-enhanced surfaces to conform easily to filler particles,
contain excess matrix material or increase surface diffusion
capabilities for bonding. Governing principle was to select
low-cost processes which could be done on wafer level and
do not create additional interfaces. From different
approaches, a so-called “nano-sponge” technology realised
in a thin Au-layer gave the best processing results and is
being characterised thermally and mechanically. The layer
can be applied at low T and put directly onto the die surface
without any second interface. As could be shown, the
resulting structure with an open-porous void size of initially
15 nm can easily be modified in their mechanical properties
by process parameters. It could be shown by nanoindentation
that the material deforms easily, i.e. showing the prerequisite
to conform to filler particles, regaining most of the excellent
thermal conductivity of pure Au exactly where it is needed.
Although the process optimisation is ongoing, first results
can already be shown.
In order to characterise the effect of these surface
modifications, a special test stand has been designed which
allows localised measurement of thermal current and
temperature measurement as close as possible to the
modified surface. Thin film heaters and sensors are realised
on the flat surfaces of two silicon chip surfaces of 2 x 2 cm 2
allowing a maximum possible temperature drop across the
sandwiched TIM under test thus achieving maximum
resolution. For mechanical stability the chips are bumped
©EDA Publishing/THERMINIC 2009 224
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and wire-bonded to a ceramic frame. To prevent chip tilt
capacitive sensors are also integrated to measure the TIM
thickness locally along with the thermal current. The sensors
are covered by a thin CVD-glass which in return acts as
support layer for the surface enhancement structure. Again,
the thermal performance can be measured under conditions
which are as close as possible to the real application.
Another thermal technology developed is a sintering
approach to Ag-powder to provide a highly conductive diebond
layer [6]. We have reached a parameter window within
which thermal conductivities up to 400 W/mK can be
reached at low porosity. The interfaces need a thin plated Ag
or Au layer, therefore providing excellent heat transfer. A
special test stand has been developed to characterise this diebond
layer using processes and materials as well as surfaces
as later in a possible application. Shear tests indicate a very
good adhesion for the developed process. Also here
mechanical characterisation and reliability tests are ongoing,
as thickness and material properties have a great impact on
reliability of power systems and so such considerations have
to be included into the design process right from the
beginning [11,12].
The research and development work presented here has
been carried out in the ongoing EU FP7 Integrated Project
“Nanopack”.
7-9 October 2009, Leuven, Belgium
by a lower filler density near the interface, an abundance of
matrix material with much lower conductivity [5]. Therefore
one may look for process or technology related riffs to
change that. One idea is to enlarge the surface in a way that
is can adjust to the filler particles. This is one aspect of the
nano-sponge technology which is now presented.
Chip
Nanosponge
Filler Particles
Matrix
Substrate
Fig 2: Schematic of an adhesive contact with
nano-sponge surfaces on both sides.
Nano-porous structures, which could be deposited by
electroplating, would combine the advantage of a wafer level
process with the benefit of a large contact area. The nanosponge
can serve as a compliant interface layer for high
thermal conductive adhesives with conductive filler particle.
The conformity between filler particle and contact surface is
reached by local compression of the nano-sponge which
should result in low thermal interface resistance, ideally
locally regaining the conductivity of bulk Au (figure 2).
II. NANO-SPONGE SURFACE ENHANCEMENT
A technology fit to reduce thermal interface resistance has
to feature very low added cost, compatibility with back-end
processes and low-temperature quite apart from enhancing
heat transfer for good reasons.
R th
[K/W]
TIM
10
Gel#1
8
TIM Folie #2
6
4
2
R th,0
0
0.0 0.1 0.2 0.3
d [mm]
Fig. 1. Typical situation: TIMs show diversity in thermal
conductivity (slope) and thermal interface resistance
(intercept) as measured by time honoured method
(e.g. ASTM-standard or [5,13]).
As seen in figure 1, bulk conductivity is only half of the
story. In the relevant region below 100 µm BLT the TIM #1
would be the better choice despite a much lower thermal
bulk conductivity: This interface resistence is in part caused
3 µm
Fig 3: Cross section of a nano-sponge structure .
An enhancement is further given by a possible take in of
superfluous matrix material at the boundary into the pores,
which should at the same time increase the mechanical
interlocking between adhesive and nanoporous surface, thus
increasing reliability. If it was possible to generate such
porous layers in the nano-region, enhanced interdiffusion
capabilities due to such a nano-scale should give rise to new,
interestingly reduced interconnect bonding parameters.
The nano-sponge process can be applied to the reverse
side of a silicon chip. The structure is also open-porous with
pores of about 15 nm diameter. This is their initial size when
observed by focused ion beam (FIB) imaging as seen in
figure 4: Altogether, the unoccupied volume amounts to
80 %vol of the sponge in that case. Interestingly, by
tempering it is possible to coarsen the Au nanosponge which
should be due to surface diffusion of Au-atoms to help
decrease the energetically unfavourable large internal
surface of the sponge. For e.g. 30 min at 300°C Au
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7-9 October 2009, Leuven, Belgium
structures of a size of about 200 nm are generated (see
figure 5).
Pt
Indenter
Sponge
Au
500 nm
300 nm
Fig 4: FIB image of the nano-sponge Au-structure. Note
the initially generated pores of 15 nm diameter. This
sponge has only 1/5 th of the density of Au. This image
is a close-up of figure 3.
Fig. 6: FIB image after nanoindentation.The platinum
layer was deposited after nanoindentation.
This is depicted in figure 7: The stiffness (E-modulus) is
initially at very low values, far from the bulk value of pure
Au (≈ 80 GPa [14]). With increasing indentation depth, the
stiffness increases.
18
15
12
d = 2400 nm
E [GPa]
9
6
d = 1500 nm
300 nm
Fig. 5: SEM image of the nano-sponge after tempering
at 300 °C for 30 min.
So the generation of the nanosponge structure seems a
very handy way to apply an open porous layer onto e.g. a
silicon die with low T proceses. It now needs to be
characterised in its themal and mechanical properties as a
function of structural size.
II A. NANO-SPONGE CHARACTERISATION
Nanoindentation measurements were performed on a
specimen which had a structure as depicted in figure 4. A
Berkovich indenter was used for indentation at room
temperature. The effect of the indentation can be seen in
figure 6 where the indenter has left a characteristic mark in
the sponge layer of approximately 5 µm thickness. Notable
is the fact that the Au layer below has not been indented but
that the sponge has apparently taken up all (plastic)
deformation. That should also be evident from the obtained
values for stiffness E and hardness H. For that purpose,
indents were set at different levels of force which produce
indents of various depths. After unloading the stiffness could
be obtained.
3
0
d = 50 nm
d = 120 nm
0 2000 4000 6000 8000 10000
Force [µN]
Fig 7: E-modulus of the sponge as function of indentation
depth and force.
H [GPa]
0.14
0.12
0.10
0.08
0.06
0.04
0.02
d = 50 nm
d = 120 nm
d = 1500 nm
0 2000 4000 6000 8000 10000
Force [µN]
d = 2400 nm
Fig 8: Hardness of the sponge by nanoindentation as
function of force and depth.
This could be due to an increasing densification of the
sponge as the tip moves downward to compress it, but also
due to the increasingly dominant presence of the solid Aulayer
below (substrate effect). Conspicuous is the large
©EDA Publishing/THERMINIC 2009 226
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scatter in the results, which is due to the largely
inhomogeneous surface structure of the sponge showing
cracks and voids (see figure 3).
F [µN]
300
250
200
150
100
50
0
Bulk Au
Sponge
Au
0 20 40 60
Depth [nm]
20
15
10
5
0
7-9 October 2009, Leuven, Belgium
hardness values found for low indentation depths.
F [µN]
Fig. 9. Force-displacement curve for the smalest force
(right curve). For comparison: Indentation on 300 nm bulk
Au [15] (to the left). Note the different scales.
A different observation is made for the hardness, i.e. a
measure of ductility of the material. The initial state of the
sponge shows a significantly higher value (above the usual
dependence of hardness to increase at low depths [14]), i.e.
the nearly un-deformed structure shows some elastic effect
of the sponge structure. Then, with increasing depth, it
becomes softer only to increase slowly again as indentation
continues. This again should be due to densification of the
sponge. However, even at 50 % deformation the porous layer
is still more than an order of magnitude from a (process
dependent) bulk value for Au-hardness (e.g. 1.3 GPa for
electroplated Au [14]). The convergence to a bulk value has
still to be shown in further measurements.
F [µN]
2500
2000
1500
1000
500
0
F max = 2500µN
On further increasing the force, the curves take on the
familiar shape of a bulk metal indicating large plastic
deformation with its hysteresis (figure 10). However, to
clarify the deformation process at this scale further
investigation is necessary.
The low stiffness and hardness of the sponge renders it
eligible for the purpose of conforming easily to filler
particles of an adhesive, hence decreasing interface
resistance.
II B. SILICON TO SILICON TESTER (SISSY)
The name Sissy-tester is derived from “Si-Si” as two
silicon dies face each other in a steady state measuring
configuration. This tester is required to accurately measure
thermal conductivity and interface resistance using in-situ
monitoring of the major influential quantities. It offers the
unique capability to include the surface modification
technologies specified and developed in the Nanopackproject,
a feature not offered by time-honoured designs
[5,7,13]
AlN- substrate
Wire
bond
T-Sensors
Thin film
heater
F
Si
TIM
Si
CVD Ox
Micro water cooler
Equipotential
surfaces
AlN- substrate
bumps
Fig 11: Schematic cross-section of Sissy-tester
The challenges of Sissy-tester are to produce double side
processed silicon dies and to develop a test system which
enable us accurate mechanical and electrical control. Figure
11 shows a schematic cross-section of the Sissy-tester.
Layout of Chip A bottom and Chip B top
Layout of Chip B bottom
0 500 1000 1500 2000
d [nm]
Fig. 10. Force-displacement curve for larger forces.Now
a more bulk-like curve is obtained
It is instructive to have a look at the force-displacement
curve itself. As depicted in figure 9 for the smallest force
investigated, the curves rise linearly with indentation depth
which is typical for shallow indents and due to the spherical
tip shape. This effect is also visible when compared to bulk
Au [15]. However, the large difference in stiffness becomes
apparent considering the scale. Plastic deformation seems
minimal as the hysteresis is small. This underpins the higher
Wire bond
Capacity sensors
Bump pads
pads
Temperatue sensors
Fig 12: Design and layout of chips.
For the Sissy-tester there are two types of chips designd
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7-9 October 2009, Leuven, Belgium
and produced (chip A and chip B) with two different sizes: A1=64mm² @ big Chip
The big chips is 30 mm x 20 mm and the small one is 20 mm
A2=14mm² @ small chip
x 10mm. Chip A has on the top side thin film heater, 70nm
of TiW layer, which enable power up to 120W and d= 10µm… 100µm
homogeneous temperature distribution. On the bottom side
of chip A five thin film micro temperature sensors and four
60
equipotential surfaces as capacity sensors to measure and
capture distance and tilt in-situ are integrated. Chip B has on
50
the both sides the same configurations, five T-sensors and
four C-sensors. 12 shows the layout of the bottom side of
40
chip A and the bottom and the top side of chip B.
30
Following the main components of the test system will be
20
described:
10
Heater
A 70 nm thin film TiW layer with ρ=5e-7 Ohm*m
electrical resistivity of TiW allows electrical power up to
120W under using a low voltage until 42V. The full area of
the heater structure enables a homogeneous temperature
distribution on the TIM surfaces below.
Temperature sensors
Proper measurements of temperature are very important to
improve the accuracies of the test system. Semiconductor
diodes which are integrated in e.g. flip chip can give proper
temperature measurements but they cannot measure the
interface temperatures. In Sissy-tester thin film micro scale
meander structures of 60nm Au with 30nm TiW adhesion
layer were realised for temperature measurement. The
meander structures have the following technological
parameters: width 20µm, line space 35µm and length
42.5mm for the big chips and 30mm for the small chips, it
yields from that 760 ohm electrical resistance for big
variants and 454 ohm for small variants. The sensivity of
temperature sensors will be than about 10mV/K at
I const =3 mA. T-sensors will be measured separate with using
a four point measurement method.
Capacity sensors
Equipotential surfaces are integrated on the surface to
capture tilt and distance between the dies and between the
lower die and micro cooler to control the homogeneity of a
heat flow through TIM and dies. The equipotenial surfaces
have a defined area 8mm x 8mm for big chips and 3.75mm x
3.75mm for the small one. To determine the distance
between the surfaces the capacity can be measured.
C = ⋅ε
ε 0
r
⋅
A
d
Where C: capacity, ε 0 : permittivity of free space ε r :
relative static permittivity, A: area, d: distance or BLT of
TIM.
The relative static permittivity ε r should be determined
separate for each material. In the worst case ε r will be equal
to 1 (air). To evaluate the measurement range and sensitvity
of the capacity sensors a sample calculation will be estimate
for difference BLT:
C [pF]
big chip
small chip
0
0 20 40 60 80 100
BLT [µm]
Fig. 13: Minimum capacity yvalues vs. BLT for the both
chips with no TIM present.
Figure 13 shows the relationship between capacity and
distance for difference sizes of areas. It can be seen that the
capacity values for a big chip are between 55pF und 5.5pF
and for a small one are between 12pF and 1.2pF at BLT
between 10µm and 100µm, with an increased sensitivity
versus the interesting small BLT values. Such capacitance
values can easily be measured by today’s impedance gauges.
Electrical and mechanical connections
The chips are soldered and wire-bonded to AlN-substrate,
AlN was chosen because of his coefficient of thermal
expansion (CTE). The mean thermal expansion coefficients
obtained in the range 20–300 °C are 4.2e-6 1/K for AlN and
2.8e-6 1/K for silicon. The CTE of silicon and AlN ceramic
is quite close to each other, which minimizes thermomechanical
stresses.
Micro water cooler
AlN-substrate
Si-die
TIM
Si-die
AlN-substrate
Fig. 14: Electrical and mechanical connection of Sissytester
The top of chip A and the bottom of chip B are first
assembled on AlN substrates using AuSn. AuSn solder is
preferably applied using preforms or paste instead of
bumping to maintain some degree of freedom in the process
flow. The bottom of chip A and the top of chip B are wirebonded
after the assembling. To provide mechanical support
and exclude contaminants such as fingerprint residues which
could disrupt circuit operation glob-top encapsulation is
©EDA Publishing/THERMINIC 2009 228
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7-9 October 2009, Leuven, Belgium
applied.
Processing of Sissy Chips
In order to realize the two types of silicon chips which
bear the heater, the sensors for temperature, and the
equipotential surfaces for capacitive measurements, a variety
of functional layers have to be brought on both sides of the
silicon chips. For this purpose double side polished 150 mm
wafers (thickness: 800 µm) have to be processed on both
sides aligned to each other within an accuracy of 6 µm. A
series of thin film processes like PVD, CVD, etching, as well
as reinforcement of layers by electrochemical deposition
(ECD) have been selected to build up the different structured
layers. The metallic thin film layers (TiW, Au, Ni) are
deposited by ion sputtering and, where adequate, used as
plating base before being structured by wet etching. The
inorganic dielectric layers are deposited by CVD. Two
specific combinations of process sequences on both sides of
the wafer correspond to the two types of double side
functional chips. In this context the special challenge is to
combine the process steps in a way that the mutual
interference is minimized. Where necessary the opposite side
of the wafer has to be protected in a suited way from
processing.
In figure 15 a schematic cross-sectional view is given of
the upper of the measurement chip pair. The top side of the
chip bears the heater and the bottom side the temperature
sensors and the equipotential surfaces. The adhesion layers
are made of TiW (blue), the wiring of gold (yellow), and the
passivation layer of an inorganic dielectric (pink).
Additionally the first TiW layer on top has the function of
the heater and the gold thin film on the bottom forms the
sensors. The bond pads are reinforced by ECD. The
soldering pads of the heater on top are made of nickel
(white) and gold, the wire bond pads of gold only.
The bottom chip of the Sissy-tester bears on both sides the
temperature sensors and the equipotential surfaces, but the
soldering pads are formed on the bottom and the wire bond
pads on the top side of the chip as the mounting of the chip
on the ceramic frame is in this case vice versa.
an Ag suspension and is therefore applicable using standard
bonding equipment. Normally silver layers on chip and
substrate side are deposited to ensure an optimum adhesion
to the TIM.
Fig. 16: Cu test samples (side and top view) used for the
setup of the Ag-sintering process and for the thermal
characterization; the Ag suspension is dispensed on the
Ag metallized pedestal having a size of 2 mm²
Cu test samples were used for the setup of the sintering
process, first results are reported in [6]. The aim was to
optimize the adhesion after bonding and to achieve a
reproducible bonding surface which was needed for the
thermal characterization of the interconnection. During first
sintering experiments the Ag suspension was dispensed on
flat Cu surfaces and cut after drying to achieve a contact area
of 1 mm². The disadvantage of this method was on the one
hand the positioning of the contact area on the Cu and on the
other hand the influence by the cutting itself. To get rid of
both issues new Cu samples were designed and
manufactured. Now the contact area is clearly defined by a
pedestal. The size of this pedestal is 2 mm² and the contact
area was previously metalised with a layer of 1-2 µm Ag
(see Figure 16).
200 µm
Fig. 15: Schematic cross-sectional view of the upper
measurement chip, top: heater and soldering pads, bottom:
temperature sensors, equipotential surfaces, and wire bond
pads.
III A. MONO-METAL SILVER INTERCONNECT
Using Ag-sintering as TIM has two advantages: One is the
excellent thermal conductivity of the material and the other
one its good electrical conductivity. An Ag-sintering layer
can be applied either by dispensing or by stencil printing of
Fig. 17: Light microscopy image of a pedestal after shear
testing; the fracture occured between the TIM and the Cu;
parts of the Ag sintering layer remained at the left side
Different parameters and processes needed to be
optimized during the setup: the dispensing of the suspension,
the drying of it before bonding, the selection of force,
temperature and bond time. Finally, samples were bonded
for thermal analysis applying a force of 30 MPa and a
temperature of 250°C for 120 s. Shear testing was performed
and a shear force of about 40 MPa was measured. The
sintering height after dispensing was ~270 µm and after
©EDA Publishing/THERMINIC 2009 229
ISBN: 978-2-35500-010-2

onding it was compressed down to ~60 µm. As shear mode
a fracture between Ag and the Cu surface was detected (see
figure 17).
III B. HI-LAMBDA TESTER
A first description of the set-up has been given in [6]. The
idea of this test system is to measure the thermal
conductivity of very highly conductive metal-based TIMs
with the help of a steady state technique, using copper bars
as thermal resistors for their large thermal conductivity and
hence good resolution at manageable size. Solders as well as
sintered mono-metal layers could be tested with this method,
that the thermal conductivity is measured under processing
conditions as later in the real application.
7-9 October 2009, Leuven, Belgium
NTC-Resistors as temperature sensors which allow to reach
an accuracy of 0.05 K for the six calibrated temperature
sensors. From that we expect an exceptionally good
resolution of the thermal conductivity in the measurement.
The measurements were done under vacuum to minimize the
convection.
From the comparison between experiments and simulation
it could be find that the accuracy of the results strongly
depends of the dimension of the bonding area. Therefore we
measured the contact area of all tested samples. Figure 19
shows the target-performance comparison of one tested
sample.
Table 1: Correlation Experiment vs Simulation
Sensor # Exp [°C] Sim [°C] ∆T [°C]
T1 97,44 97,41 0,02
T2 93,95 93,85 0,11
T3 90,20 90,26 0,06
T4 32,30 32,25 0,04
T5 28,63 28,67 0,04
T6 25,05 25,10 0,05
λ [W/mK] 403 ± 15
Table 1 shows the compare between experiments and
simulations for one test thermal conductivity of the used Cu
is 390 W/mK, a value measured by the laser flash method.
The heat flow can be measured by knowledge of the
geometry and thermal conductivity of the Cu test sample.
Fig 18: Design of hi-lambda tester.
The Cu bars are 30 mm long
Figure 18 shows the improved design of hi-lambda tester.
Temperatures are measured in six positions. To evaluate the
thermal conductivity of the TIM we compare the measured
temperatures with the equivalent FE-Model.
Fig 19: Microscopy image of contact area. Due to
artefacts during processing of the paste the area is
slightly smaller that the maximum possible value.
Therefore we have to guarantee an exact temperature
measurement. This can be achieved by using calibrated
T [°C]
98
97
96
95
94
93
92
91
90
89
32
31
30
29
28
27
26
25
24
T1
T2
T3
T4
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Position [mm]
T5
Exp
Sim
Fig. 20: Correlation Experiment vs Simulation
Two samples with different BLT of sinter Ag were
measured and simulated. As one can see in table 1 and figure
20, the results of simulation and experiment agree very well
to yield results for the thermal conductivity of sintered silver
between 395 W/mK and 410 W/mK. This value comes very
T6
©EDA Publishing/THERMINIC 2009 230
ISBN: 978-2-35500-010-2

close already to the literature value of a theoretically
possible 420 W/mK for pure silver.
To estimate the accuracy of the method, we have
calculated its sensitivity first. This can then be compared to
the mean accuracy of the temperature measurement δT fitted
for the three sensor values along the Cu-bar.
The sensitivity of the method is expected to depend on the
BLT of the TIM. The simulated curves are given in
figure 21 for different TIM-conductivities and BLTs.
Naturally the sensitivity is higher for the larger BLT and
yields the value of S = 0.0046 mK 2 /W. With δT = 0.045 K
we obtain a resolution of around δλ = ± 10 K for the thicker
BLT.
7-9 October 2009, Leuven, Belgium
introduced by the technological modifications. The accuracy
obtainable at low bond-line thicknesses and highly
conductive interface materials is evaluated and commented
on. More results will follow and be presented soon in
another paper, encompassing also reliability aspects of the
new technologies.
ACKNOWLEDGMENTS
The authors appreciate the support of the EU FP 7
Integrated Project “Nanopack”. Further thanks go to the
authors’ Fraunhofer colleagues A. Gollhardt, S. Huber,
M. Koch, K.-F. Becker, T. Braun and M. von Suchodolez.
∆T [K]
0.12
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
BLT = 28 µm
BLT = 71 µm
390 395 400 405 410 415 420
λ Ag
[W/mK]
Fig 21: Sensitivity of measurements for two different BLT
For the thinner BLT we obtain δλ = ± 20 W/mK. This
means that preferably thick BLTs should be used during
characterisation. However, large BLTs of Ag powder are
difficult to realise technologically.
CONCLUSIONS & OUTLOOK
In this paper we have stressed the need for advanced
thermal interface technology and presented two approaches
to process and characterize theses structures. A so-called
“nano-sponge” technology has been introduced with
interesting structural, mechanical and thermal features to
enhance heat transfer across the interface. Nanoindentation
has been used to verify the increased deformability of the
sponge to possibly allow enhanced contact to filler particles.
A second technology using Ag-powder on Ag surface
metallisation has been presented and tested successfully
thermally and mechanically.
It has also been pointed out that usually a variety of
characterisation methods is made necessary as each new
interface technology has to be thermally measured as
processed in the real device. In this vein two test stands have
been designed and developed to measure the effect
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Microsystem Technologies, Vol 15, No 6, pp 799.813,
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[12] B. Wunderle, K.-F. Becker, R. Sinning, O. Wittler, R.
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©EDA Publishing/THERMINIC 2009 232
ISBN: 978-2-35500-010-2

7-9 October 7-9 October 2009, 2009, Leuven, Leuven, Belgium Belgium
Temperature as as a a First-Class Citizen Citizen in in Chip Chip Design Design
Abo Ras M. 224
Amon Cristina 197
Antón Raúl 180
Aranyosi Attila 23
Atienza David 50
Abstract- Abstract- With With new technology new technology trends, trends, arising arising through through a a
confluence confluence Avenas of factors of Y. factors such as such Moore's as Moore's law scaling law scaling and 17 3D and 3D
integration, integration,
Baelmans the role the of role
M. thermal of thermal design design is inexorably 157,
is inexorably
163, shifting 174
shifting from from
package-centric package-centric issues issues towards towards on-chip on-chip optimizations. optimizations. This talk This talk
Bándy E. 61
overviews overviews the roots the of roots this of change, this change, the circuit the circuit effects effects of elevated of elevated
temperatures, temperatures, Bazaz and Shafaat on-chip and on-chip A. optimizations optimizations for effective for effective thermal 40 thermal
management. management.
Beyne E. 56
Bezama Pepe 150
Bieniek
Text unavailable Text unavailable T.
at the at time the of time printing. of printing. 84
Blansaer Eddy 113
Brizar Guy 113
Brunschwiler Thomas 150
Burzo Mihai G. 36, 130
Caviglia Daniele D. 66
Chen C. C. 8
Chen Y. C. 8
Cheng E. 45
Cheng Y. T. 8
Colgan Evan 150
Cupak M. 45
De Wolf I. 56
Delesie T. 174
Demoustier S. 192
Deweerdt R. 113
Dia H. 87
Dietrich L. 224
Djafari-Rouhani Bahram 203
Donose R. 163
Dorkel J-M. 87
Duflos F. 113
Engelmann G. 224
Fiorini P. 95
Földváry Á. 61
Garibbo Alessandro 66
Garimella Suresh V. 101
Gillet Jean-Numa 203
Gillon Renaud 113
Glezer Ari 186
Goicochea Javier V. 197
Gonzalez M. 113
Author Index
Sachin Sachin S. Sapatnekar S. Sapatnekar
University University of Minnesota, of Minnesota,
USA USA Goodnick S. M. 195
Grabiec P. 84
Guédon S. 17
Hammel Ernst 216
Hantos Gusztáv 121
Harirchian Tannaz 101
Hasan M. M. 40
Hauck Torsten 124
Hidalgo Pablo 186
Hodes Marc 75
Hong Yuping 13
Hsiao Hsu-Liang 8
Hutchison M. 168
Janczyk G. 84
Janicki M. 80, 136
Janssen J.H.J. 31
Joshi Yogendra 186
Kaiser S. 17
Kashmiri Mahdi 140
Kempers Roger 210
Kharitonov I.A. 70
Khodabandeh Rahmatollah 180
Kim Kyoung Joon 75
Klein M. 224
Klieber Robert 117
Kollár Ernő 121
Komarov Pavel L. 36, 130
Kota Krishna 186
Kozynko P.A. 70
Kulesza Z. 80, 136
Lee Chia-Yu 8
Leonov V. 95
Lerch Renee 117
Li Yuening 13
Lyons Alan 210
Madrid Marcela 197
Makinwa Kofi 140
Maltz William 23
Marchal P. 45
Marcu Marius 144
Marechal Y. 17
Martínez-Galván Eduardo 180
Martins O. 17
©EDA ©EDA Publishing/THERMINIC Publishing/THERMINIC 2009 2009 233 1 1
ISBN: ISBN: 978-2-35500-010-2
978-2-35500-010-2

7-9 October 7-9 October 2009, 2009, Leuven, Leuven, Belgium Belgium
Temperature as as a First-Class a Citizen Citizen in Chip in Chip Design Design
May D. 91, 224 Van der Plas G. 45
Michel B. 91, 150, 224 Van Hoof C. 95
Mrossko R. 224 Van Oevelen T. 157
Sachin Sachin S. Sapatnekar S. Sapatnekar
Napieralski A. 80, 136 University University of Minnesota, of van Minnesota, Vroonhoven Caspar 140
Nikolić D. 168 USA USA Vanderstraeten D. 113
Oppermann H. 224 Vandevelde B. 45, 56, 113
Oprins H. 45, 56 Vasileska D. 195
Palm Björn 180 Vass-Varnai Andras 219
Paoli Andrea 66 Veendrick H.J.M. 31
Abstract- With new technology trends, arising through a
Paredes confluence Stephan of factors such as Moore's law 150 scaling and 3D Vullers R. J. M. 95
Peltier integration, N. the role of thermal design is inexorably 17 shifting from Wittler O. 224
package-centric issues towards on-chip optimizations. This talk
Pennec overviews Yan the roots of this change, the circuit 203 effects of elevated Wu Mount-Learn 8
Persoons temperatures, T. and on-chip optimizations 163, for 174 effective thermal Wunderle B. 91, 224
management.
Petrosjanc K.O. 70 Ziaei A. 192
Plesz B. 61
Raad Peter E. 36, 130
Text unavailable Text unavailable at the time at the of time printing. of printing.
Raghupathy Arun P. 23
Raleva K. 195
Ramos Juan Carlos 180
Reiter Werner 216
Rencz Marta 219
Robinson A.J. 168
Robinson Anthony 210
Rogiers F. 157
Rothuizen Hugo 150
Rudnyi Evgenii 124
Ryabov N.I. 70
Sabry N. 2
Saenen T. 163, 174
Sapatnekar Sachin S. 1
Sapin P.T. 168
Sarkany Zoltan 219
Sauveplane J.B. 87
Schacht R. 91, 224
Seminara Lucia 66
Shakoor Rana I. 40
Shi Jian 13
Singh C. 8
Srinivasan A. 45
Székely Vladimir 209
Szermer 80, 136
Szynka J. 84
Tang Xinhe 216
Teulings Wim 124
Torfs T. 95
Torregiani C. 56
Tounsi P. 87
Valle Maurizio 66
Abstract- With new technology trends, arising through a
confluence of factors such as Moore's law scaling and 3D
integration, the role of thermal design is inexorably shifting from
package-centric issues towards on-chip optimizations. This talk
overviews the roots of this change, the circuit effects of elevated
temperatures, and on-chip optimizations for effective thermal
management.
©EDA ©EDA Publishing/THERMINIC Publishing/THERMINIC 2009 2009 234 1 1
ISBN: ISBN: 978-2-35500-010-2
978-2-35500-010-2