Online proceedings - EDA Publishing Association

7-9 October 2009, Leuven, Belgium
Spatial and temporal temperature variations in CMOS
designs
J.H.J.Janssen
NXP Semiconductors
Gerstweg 2, 6534AE Nijmegen The Netherlands
H.J.M.Veendrick
NXP Semiconductors
HTC-32, 5656AE Eindhoven The Netherlands
Abstract
Due to the rapid growth in the number of transistors per
chip, the power consumption of the average nMOS ASIC
reached the level of one Watt, which is, in order of magnitude,
about the maximum power consumption allowed for a cheap
plastic package without thermal enhancements like drop-in
heat spreader, fused leads or exposed pads. The internal chip
temperature is the result of the combination of the chip power,
the package, a possible heatsink, the application board and the
airflow conditions. This requires a reasonably accurate model
that includes the thermal properties of the chip, the bonds, the
package and the system.
I. INTRODUCTION
The average power consumption of integrated circuits has
been steadily increasing since they have been introduced
about five decades ago. Until the early eighties, nMOS
technology was the most dominant VLSI technology. Logic
gates, then, were built from an nMOS transistor pull-down
circuit representing the logic function in combination with a
single nMOS load transistor, keeping the output high, when
the pull-down circuit was off. This logic had a major
disadvantage in that every logic gate whose output was zero,
meaning that the pull-down circuit was on, consumed static
power as long as this logic zero state was maintained. On the
average this means that half the number of logic gates was
continuously consuming static power, which was about an
order of magnitude more than the switching power. Due to
the rapid growth in the number of transistors per chip, the
power consumption of the average nMOS ASIC reached the
level of one Watt, which is, in order of magnitude, about the
maximum power consumption allowed for a cheap plastic
package without thermal enhancements like drop-in heat
spreader, fused leads or exposed pads. This forced the drive
from nMOS to CMOS technology and circuits in the early
80ies. Due to the absence of simultaneous conduction of the
nMOS and pMOS transistors in a CMOS logic gate, these
did not show any static power consumption. Therefore, an
average CMOS chip, at that time, consumed about a factor
of ten to twenty less than its nMOS counterpart. However,
today, about 25 years later, the average CMOS chip has
reached this package-limited power level of one Watt again,
but with no alternative technology solution. As a result, a
“less power” attitude is a must at all hierarchy levels of
design. Even when that is the case, the average power
consumption of an integrated circuit is still expected to
continuously increase.
Variability is another point of concern. Spatial variations
are variations due to the fact that identical devices have a
different physical position and environment. This variations
may cause a different behaviour of identical transistors due
to a variation in the channel doping level, a different
orientation, a temperature gradient across the chip, a
different metal coverage or other proximity effects, such as
mechanical stress (e.g., STI stress), the position of a well in
the vicinity of a transistor (well-proximity effect), and/or
pattern shape deviations as a result of imperfect lithographic
imaging and pattern density variations.
Time-based variations include signal integrity effects,
such as cross talk, supply noise, ground bounce, and iR-drop,
but also temperature variations over time, due to variations
in workload.
From the above we see that the temperature contributes to
both spatial and time-based variations. This combined with
the increasing power consumption leads to the idea that the
momentary temperature gradient across the chip can vary a
lot with the workload. This may cause circuits in certain
regions on the chip to slow down at a different rate then
others, which will certainly make the performance of a
digital circuit less predictable, and the timing closure more
complex.
In addition to this, steep and large temperature gradients
(hot spots) may also cause physical stress or may cause the
local temperature to exceed the maximum specified
temperature.
To really visualise the overall impact of the power
distribution across a chip, we first need to make the
transition from power distribution to temperature distribution
and then discuss the influence of the temperature on the
speed of the circuit. Temperature distributions are simulated
©EDA Publishing/THERMINIC 2009 31
ISBN: 978-2-35500-010-2