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7-9 October 2009, Leuven, Belgium typical operating conditions. The concept and the numerical model will be validated by experiments that are currently underway. ACKNOWLEDGMENT The authors wish to acknowledge DARPA Microsystems Technology Office for funding the work through the 3D MINT program and Irvine Sensors Corporation. REFERENCES [1] D. Pinjala, M.K. Iyer, C.S. Guan, and I.J. Rasiah, “Thermal characterization of vias using compact models,” Proc. EPTC 2000, pp. 144-147, 5-7 Dec 2000. [2] T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle, H. Oppermann, and H. Reichl, “Forced Convective Interlayer Cooling in Vertically Integrated Packages,” Proc. ITHERM 2008, pp. 1114-1125, Orlando, Florida, 28-31 May 2008. [3] A. Bar-Cohen, K. Geisler, and E. Rahim, “Pool and Flow Boiling in Narrow Gaps – Application to 3D Chip Stacks,” Proc. Fifth European Thermal-Sciences Conference, Eindhoven, The Netherlands, 18-22 May 2008. [4] D.E. Wroblewski, Y. Joshi, “Liquid Immersion Cooling of a Substrate-Mounted Protrusion in a Three-Dimensional Enclosure: The effects of Geomotry and Boundary Conditions,” J. Heat Tran., vol. 116, pp. 112-119, February 1994. [5] Y. Joshi, M.D. Kelleher, M. Powell, and E.I. Torres, “Natural Convection Heat Transfer from an Array of Rectangular Protrusions in an Enclosure Filled with Dielectric Liquid,” J. Electron. Packaging, vol. 116, pp. 138-147, June 1994. [6] T.J. Heindel, S. Ramadhyani, and F.P. Incropera, “Conjugate Natural Convection from an Array of Discrete Heat Sources: Part 1 – Two- and Three-Dimensional Model Validation,” Int. J. Heat and Fluid Flow, vol. 16, pp. 501-510, 1995. [7] T.J. Heindel, S. Ramadhyani, and F.P. Incropera, “Conjugate Natural Convection from an Array of Discrete Heat Sources: Part 2 – A Numerical Parametric Study,” Int. J. Heat and Fluid Flow, vol. 16, pp. 511-518, 1995. [8] S.K.W. Tou, C.P. Tso, and X. Zhang, “3-D Numerical Analysis of Natural Conevctive Liquid Cooling of a 3x3 Heater Array in Rectangular Enclosures,” Int. J. Heat Mass Tran., vol. 42, pp. 3231- 3244, 1999. [9] Y.L. He, W.W. Yang, and W.Q. Tao, “Three-Dimensional Numerical Study of Natural Convective Heat Transfer of a Liquid in a Cubic Enclosure,” Num. Heat Tran. A, vol. 47, pp. 917-934, June 2005. [10] Q-.H. Deng, G-.F. Tang, Y. Li, and M.Y. Ha, “Interaction Between Discrete Heat Sources in Horizontal Natural Convection Enclosures,” Int. J. Heat Mass. Tran., vol. 45, pp. 5117-5132, 2002. [11] A. Bazylak, N. Djilali, and D. Sinton, “Natural Convection in an Enclosure with Distributed Heat Sources,” Num. Heat Tran. A, vol. 49, pp. 655-667, October 2006. [12] F.P. Incropera, D.P. DeWitt, Introduction to Heat Transfer, 4 th Ed., John Wiley & Sons, Inc., New York, NY, 2002. [13] D. Gerty, D.W. Gerlach, Y.K. Joshi, and A. Glezer, “Development of a Prototype Thermal Management Solution for 3-D Stacked Chip Electronics by Intervealed Solid Spreaders and Synthetic Jets”. THERMINIC 2007, Budapest, Hungary, 17-19 September 2007. [14] www.3m.com [15] www.aremco.com ©EDA Publishing/THERMINIC 2009 191 ISBN: 978-2-35500-010-2
7-9 October 2009, Leuven, Belgium Presentation and status of the NANOPACK project A. Ziaei, S. Demoustier Thales Research and Technology - France Campus Polytechnique 1, avenue Augustin Fresnel 91767 Palaiseau Cedex, France Abstract – NANOPACK – Nano Packaging Technology for Interconnect and Heat Dissipation – is a European large-scale integrating project aiming at the development of new technologies and materials for low thermal resistance interfaces and electrical interconnects, by exploring the capabilities offered by nanotechnologies such as carbon nanotubes, nanoparticles and nano-structured surfaces, and by using different enhancing contact formation mechanisms, compatible with high volume manufacturing technologies. Several key research areas relative to thermal management, interconnect and packaging are addressed in the project by European industrial and academic partners: thermal interface materials, assembly, reliability and characterisation, supported by modeling and simulations. After an overview of NANOPACK, a status of the project progress is presenteed in these different fields. I. INTRODUCTION Thermal management of chip based electronic devices is becoming one of the largest bottlenecks to increased performance and integration density. Size scaling of transistors and increase of the clock rate according to Moore’s law and the semiconductor industry association (SIA) roadmap led to an explosion in power-density for logic circuits, communication devices, and memory. Although the energy per operation is still decreasing, cramming more and more transistors to the same area increases the density of dissipated power to an unacceptable level that threatens the current fast rate of progress of the industry. On the path from the source in the drain region of individual transistors to the heatsink – be it an air or a liquid cooler – the heat flux crosses a multitude of interfaces some of them separated by bulk amounts of matter. To reduce the thermal resistance from junction to ambient, new generations of low thermal resistance interfaces and low electrical resistance interconnects are needed. Efforts are focused in NANOPACK on the development of thermal interface materials (TIM), enhancing surface mechanisms and assembly technologies to reach total thermal interface resistance as low as a few Kmm²/W. Such low targeted values raise the question of their measurements with enough accuracy and repeatability. That’s why high-end specific characterisation systems are also implemented in the framework of NANOPACK. As more nanoparticles are used to improve the performance of filled materials by increasing heat transfer between solid surfaces and fluids, these nano-fluids will also be confronted with effects related to phonon quantization and will need experimental investigation as well as theoretical frameworks. To allow a continued development of the semiconductor industry, as stated in the SIA roadmap, an improved understanding of phononics in nanoparticle filled fluids or composites is needed. Nano-scale modeling and characterisation techniques are developed in the project to tackle these issues. II. NANOPACK OVERVIEW NANOPACK is a large-scale Integrating Project performed within the Information and Communication Technologies (ICT) theme of the 7 th European Framework Program, targeting the development of next-generation nanoelectronics components and electronics integration. The NANOPACK consortium, placed under the lead of Thales Research and Technology, consists of 4 major industrial partners, 4 innovative SMEs, and 6 academic groups in total representing 8 European countries and providing all the necessary competences in all key areas dedicated to thermal management, interconnect and packaging: thermal interface materials (TIM), thermal interface assembly, reliability, characterisation and modeling supported by world class computers. The total cost of the project is 11 M€ for a total funding of 7.4 M€. Fig. 1. NANOPACK Technology Base The overall objective of the NANOPACK project is to develop new thermal interface technologies for low thermal resistance by employing nano-modified surfaces and materials along with methods to characterize and simulate them with respect to thermal, electrical and reliability-related properties. Three parallel approaches will be pursued to improve thermal and electrical performance: enhancement of bulk conductivity of filled systems, reduction of bondline ©EDA Publishing/THERMINIC 2009 192 ISBN: 978-2-35500-010-2
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