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interaction. ETh SimCoupler converts data transferred between simulators (Overheat and Eldo) and launches them, when appropriate. The program runs under GNU/Linux operating system. ETh Model Generator – converter for changing layout data format from IC Station into Overheat input file format. ETh Model Generator is developed as additional component to layout editor IC Station. The flow chart of electro-thermal simulation is shown in fig. 1. Simulation begins with thermal model generation (arrow #1 in fig. 1) made by ETh Model Generator. It requires layout to be fully developed in IC Station and corresponding electrical netlist to be successfully simulated in Eldo. On the second stage ETh SimCoupler is launched to manage iteration simulation and transfer data between Overheat and Eldo. ETh SimCoupler runs Eldo and reveals information about powers from this simulation (arrow #2 in fig. 1); writes these information into Overheat input file (arrow #3 in fig. 1); runs thermal simulation through Overheat and reveals temperature information (arrow #4 in fig. 1); forms new Eldo input file using gained temperatures (arrow #5 in fig. 1). Simulation is looped this way (stages from 2 to 5 in fig. 1) until values of dissipated powers of elements on two consequential iterations differ less then P parameter. III. APPLICATION EXAMPLE The effectiveness of developed electro-thermal subsystem fig. 1 is demonstrated in the example of power voltage regulator IC K142EN9 (see fig. 1). Input voltage is 40 V, output voltage 27 V, output current 270 mA, total power about 11 W. The IC chip layout with sizes 2 mm X 2 mm (see fig. 4) was covered in Overheat by the 513x513 grid for numerical quasi-3d solution of heat transfer equation (1). IBM PC compatible computer (RAM – 512 Mb, CPU frequency – 1.8 GHz) with GNU/Linux version 2.4.18 operating system was used. Simulation finished in 3 iterations and took 14 seconds. Power accuracy parameter P was set to 10 mW. In fig. 4 isothermal lines on the IC chip surface are shown. IV. IR THERMOGRAPHY OF IC CHIP IR camera A40 of FLIR Systems with 18 μm macrolens was used to measure IC chip thermal map and temperatures of elements. Camera thermal sensitivity is 80 mK when 7-9 October 2009, Leuven, Belgium temperature is 25 ºC, resolution is 320x240 pixels, tolerance +/- 2 ºC. IC chip thermal map is shown in fig. 5. Comparing simulated and measured thermal maps shown in fig. 4 and 5, one can see sufficient accuracy. The differences in temperatures of IC elements are 2-5 ºC (see Table 1). TABLE 1 SIMULATED AND MEASURED TEMPERATURES COMPARISON Dot Temperature Difference Measured Simulated A 355.2 K 353.5 K 1.7 K B 353.0 K 353.0 K 0.0 K C 347.2 K 350.4 K 3.2 K D 343.4 K 339.5 K 3.9 K E 341.1 K 339.9 K 1.2 K V. CONCLUSIONS Fully automated electro-thermal simulation subsystem is introduced into Mentor Graphics IC Station Design System. Efficiency of new electro-thermal subsystem were demonstrated by the examples of different types of power analogue and mixed A/D ICs produced by different semiconductor technologies [8]. REFERENCES [1] S. Wünshe, C. Clauß, P. Schwarz, F. Winkler, „Electro-Thermal Circuit Simulation Using Simulator Coupling”, IEEE Trans. on VLSI Systems, 1997, Vol. 5, № 3, pp. 277-282 [2] V. Székely, A. Poppe, A. Páhi, A. Csendes, G. Hajas, M. Rencz. Electro-Thermal and Logi-Thermal Simulation of VLSI Designs. IEEE Transactions on VLSI Systems, 1997, vol. 5,№¹ 3, pp. 258–269. [3] V. Sabry, A. Bontemps, R. Vahrmann, „Realistic and efficient simulation of electrothermal effects in VLSI circuits”, IEEE Trans. VLSI Systems, 1997, Vol. 5, № 3, pp. 283-289 [4] V. Székely, A. Páhi, A. Poppe, M. Rencz, A. Csendes. SISSSI – a tool for dynamic electro-thermal simulation of analog VLSI cells. Proc. of European Design and Test Conference, 1997, p. 617. [5] G. Horvath, A. Poppe. The Sissy electro-thermal simulation system based on modern software technologies. Proc. of the 11th THERMINIC Workshop, Sept. 2005, Belgirate, Italy, pp. 51-54. [6] K.O. Petrosjanc, I.A.Kharitonov, N.I. Ryabov, P.P. Maltcev. Software System for Semiconductor Devices, Monolithic and Hybrid ICs Thermal Analysis. Proc. of EURO-DAC’95 European Design Automation Conf., Sept. 1995, Brighton, UK, pp. 360-365. [7] K.O. Petrosjanc, N.I. Ryabov. Algorithms and Software Tools for Electro-Thermal Design of Semiconductor Devices and ICs. Proc. of Intern. Conf. on Parallel Computing in Electrical Engineering (PARELEC’98), Sept. 1998, Biarlystok, Poland, pp. 310-312. [8] Thermal Analysis and Modeling of Electronic Components: Semiconductor Devices, Chips, PCBs and Units // Official Catalogue CeBIT-2007, 2008 “Russian Information Technologies”. Hannover, Germany. ©EDA Publishing/THERMINIC 2009 73 ISBN: 978-2-35500-010-2
7-9 October 2009, Leuven, Belgium Fig. 3. Power voltage regulator IC schematic (K142EN9). C A B 356,0 K 353,0 350,0 347,0 343,9 340,9 D E 337,9 334,9 331,9 Fig. 4. Simulated thermal map of K142EN9 IC. Fig. 5. Thermal distribution on top of K142EN9 IC, measured using IR thermography. ©EDA Publishing/THERMINIC 2009 74 ISBN: 978-2-35500-010-2
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International Workshop on THERMal I
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of 75 o C for fair comparison. Only
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