Online proceedings - EDA Publishing Association

7-9 October 2009, Leuven, Belgium
Presentation and status of the NANOPACK project
A. Ziaei, S. Demoustier
Thales Research and Technology - France
Campus Polytechnique
1, avenue Augustin Fresnel
91767 Palaiseau Cedex, France
Abstract – NANOPACK – Nano Packaging Technology for
Interconnect and Heat Dissipation – is a European large-scale
integrating project aiming at the development of new
technologies and materials for low thermal resistance interfaces
and electrical interconnects, by exploring the capabilities
offered by nanotechnologies such as carbon nanotubes,
nanoparticles and nano-structured surfaces, and by using
different enhancing contact formation mechanisms, compatible
with high volume manufacturing technologies. Several key
research areas relative to thermal management, interconnect
and packaging are addressed in the project by European
industrial and academic partners: thermal interface materials,
assembly, reliability and characterisation, supported by
modeling and simulations. After an overview of NANOPACK, a
status of the project progress is presenteed in these different
fields.
I. INTRODUCTION
Thermal management of chip based electronic devices is
becoming one of the largest bottlenecks to increased
performance and integration density. Size scaling of
transistors and increase of the clock rate according to
Moore’s law and the semiconductor industry association
(SIA) roadmap led to an explosion in power-density for logic
circuits, communication devices, and memory. Although the
energy per operation is still decreasing, cramming more and
more transistors to the same area increases the density of
dissipated power to an unacceptable level that threatens the
current fast rate of progress of the industry. On the path from
the source in the drain region of individual transistors to the
heatsink – be it an air or a liquid cooler – the heat flux
crosses a multitude of interfaces some of them separated by
bulk amounts of matter.
To reduce the thermal resistance from junction to ambient,
new generations of low thermal resistance interfaces and low
electrical resistance interconnects are needed. Efforts are
focused in NANOPACK on the development of thermal
interface materials (TIM), enhancing surface mechanisms
and assembly technologies to reach total thermal interface
resistance as low as a few Kmm²/W. Such low targeted
values raise the question of their measurements with enough
accuracy and repeatability. That’s why high-end specific
characterisation systems are also implemented in the
framework of NANOPACK.
As more nanoparticles are used to improve the
performance of filled materials by increasing heat transfer
between solid surfaces and fluids, these nano-fluids will also
be confronted with effects related to phonon quantization
and will need experimental investigation as well as
theoretical frameworks. To allow a continued development
of the semiconductor industry, as stated in the SIA roadmap,
an improved understanding of phononics in nanoparticle
filled fluids or composites is needed. Nano-scale modeling
and characterisation techniques are developed in the project
to tackle these issues.
II. NANOPACK OVERVIEW
NANOPACK is a large-scale Integrating Project
performed within the Information and Communication
Technologies (ICT) theme of the 7 th European Framework
Program, targeting the development of next-generation
nanoelectronics components and electronics integration.
The NANOPACK consortium, placed under the lead of
Thales Research and Technology, consists of 4 major
industrial partners, 4 innovative SMEs, and 6 academic
groups in total representing 8 European countries and
providing all the necessary competences in all key areas
dedicated to thermal management, interconnect and
packaging: thermal interface materials (TIM), thermal
interface assembly, reliability, characterisation and modeling
supported by world class computers. The total cost of the
project is 11 M€ for a total funding of 7.4 M€.
Fig. 1. NANOPACK Technology Base
The overall objective of the NANOPACK project is to
develop new thermal interface technologies for low thermal
resistance by employing nano-modified surfaces and
materials along with methods to characterize and simulate
them with respect to thermal, electrical and reliability-related
properties. Three parallel approaches will be pursued to
improve thermal and electrical performance: enhancement of
bulk conductivity of filled systems, reduction of bondline
©EDA Publishing/THERMINIC 2009 192
ISBN: 978-2-35500-010-2