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scatter in the results, which is due to the largely inhomogeneous surface structure of the sponge showing cracks and voids (see figure 3). F [µN] 300 250 200 150 100 50 0 Bulk Au Sponge Au 0 20 40 60 Depth [nm] 20 15 10 5 0 7-9 October 2009, Leuven, Belgium hardness values found for low indentation depths. F [µN] Fig. 9. Force-displacement curve for the smalest force (right curve). For comparison: Indentation on 300 nm bulk Au [15] (to the left). Note the different scales. A different observation is made for the hardness, i.e. a measure of ductility of the material. The initial state of the sponge shows a significantly higher value (above the usual dependence of hardness to increase at low depths [14]), i.e. the nearly un-deformed structure shows some elastic effect of the sponge structure. Then, with increasing depth, it becomes softer only to increase slowly again as indentation continues. This again should be due to densification of the sponge. However, even at 50 % deformation the porous layer is still more than an order of magnitude from a (process dependent) bulk value for Au-hardness (e.g. 1.3 GPa for electroplated Au [14]). The convergence to a bulk value has still to be shown in further measurements. F [µN] 2500 2000 1500 1000 500 0 F max = 2500µN On further increasing the force, the curves take on the familiar shape of a bulk metal indicating large plastic deformation with its hysteresis (figure 10). However, to clarify the deformation process at this scale further investigation is necessary. The low stiffness and hardness of the sponge renders it eligible for the purpose of conforming easily to filler particles of an adhesive, hence decreasing interface resistance. II B. SILICON TO SILICON TESTER (SISSY) The name Sissy-tester is derived from “Si-Si” as two silicon dies face each other in a steady state measuring configuration. This tester is required to accurately measure thermal conductivity and interface resistance using in-situ monitoring of the major influential quantities. It offers the unique capability to include the surface modification technologies specified and developed in the Nanopackproject, a feature not offered by time-honoured designs [5,7,13] AlN- substrate Wire bond T-Sensors Thin film heater F Si TIM Si CVD Ox Micro water cooler Equipotential surfaces AlN- substrate bumps Fig 11: Schematic cross-section of Sissy-tester The challenges of Sissy-tester are to produce double side processed silicon dies and to develop a test system which enable us accurate mechanical and electrical control. Figure 11 shows a schematic cross-section of the Sissy-tester. Layout of Chip A bottom and Chip B top Layout of Chip B bottom 0 500 1000 1500 2000 d [nm] Fig. 10. Force-displacement curve for larger forces.Now a more bulk-like curve is obtained It is instructive to have a look at the force-displacement curve itself. As depicted in figure 9 for the smallest force investigated, the curves rise linearly with indentation depth which is typical for shallow indents and due to the spherical tip shape. This effect is also visible when compared to bulk Au [15]. However, the large difference in stiffness becomes apparent considering the scale. Plastic deformation seems minimal as the hysteresis is small. This underpins the higher Wire bond Capacity sensors Bump pads pads Temperatue sensors Fig 12: Design and layout of chips. For the Sissy-tester there are two types of chips designd ©EDA Publishing/THERMINIC 2009 227 ISBN: 978-2-35500-010-2
7-9 October 2009, Leuven, Belgium and produced (chip A and chip B) with two different sizes: A1=64mm² @ big Chip The big chips is 30 mm x 20 mm and the small one is 20 mm A2=14mm² @ small chip x 10mm. Chip A has on the top side thin film heater, 70nm of TiW layer, which enable power up to 120W and d= 10µm… 100µm homogeneous temperature distribution. On the bottom side of chip A five thin film micro temperature sensors and four 60 equipotential surfaces as capacity sensors to measure and capture distance and tilt in-situ are integrated. Chip B has on 50 the both sides the same configurations, five T-sensors and four C-sensors. 12 shows the layout of the bottom side of 40 chip A and the bottom and the top side of chip B. 30 Following the main components of the test system will be 20 described: 10 Heater A 70 nm thin film TiW layer with ρ=5e-7 Ohm*m electrical resistivity of TiW allows electrical power up to 120W under using a low voltage until 42V. The full area of the heater structure enables a homogeneous temperature distribution on the TIM surfaces below. Temperature sensors Proper measurements of temperature are very important to improve the accuracies of the test system. Semiconductor diodes which are integrated in e.g. flip chip can give proper temperature measurements but they cannot measure the interface temperatures. In Sissy-tester thin film micro scale meander structures of 60nm Au with 30nm TiW adhesion layer were realised for temperature measurement. The meander structures have the following technological parameters: width 20µm, line space 35µm and length 42.5mm for the big chips and 30mm for the small chips, it yields from that 760 ohm electrical resistance for big variants and 454 ohm for small variants. The sensivity of temperature sensors will be than about 10mV/K at I const =3 mA. T-sensors will be measured separate with using a four point measurement method. Capacity sensors Equipotential surfaces are integrated on the surface to capture tilt and distance between the dies and between the lower die and micro cooler to control the homogeneity of a heat flow through TIM and dies. The equipotenial surfaces have a defined area 8mm x 8mm for big chips and 3.75mm x 3.75mm for the small one. To determine the distance between the surfaces the capacity can be measured. C = ⋅ε ε 0 r ⋅ A d Where C: capacity, ε 0 : permittivity of free space ε r : relative static permittivity, A: area, d: distance or BLT of TIM. The relative static permittivity ε r should be determined separate for each material. In the worst case ε r will be equal to 1 (air). To evaluate the measurement range and sensitvity of the capacity sensors a sample calculation will be estimate for difference BLT: C [pF] big chip small chip 0 0 20 40 60 80 100 BLT [µm] Fig. 13: Minimum capacity yvalues vs. BLT for the both chips with no TIM present. Figure 13 shows the relationship between capacity and distance for difference sizes of areas. It can be seen that the capacity values for a big chip are between 55pF und 5.5pF and for a small one are between 12pF and 1.2pF at BLT between 10µm and 100µm, with an increased sensitivity versus the interesting small BLT values. Such capacitance values can easily be measured by today’s impedance gauges. Electrical and mechanical connections The chips are soldered and wire-bonded to AlN-substrate, AlN was chosen because of his coefficient of thermal expansion (CTE). The mean thermal expansion coefficients obtained in the range 20–300 °C are 4.2e-6 1/K for AlN and 2.8e-6 1/K for silicon. The CTE of silicon and AlN ceramic is quite close to each other, which minimizes thermomechanical stresses. Micro water cooler AlN-substrate Si-die TIM Si-die AlN-substrate Fig. 14: Electrical and mechanical connection of Sissytester The top of chip A and the bottom of chip B are first assembled on AlN substrates using AuSn. AuSn solder is preferably applied using preforms or paste instead of bumping to maintain some degree of freedom in the process flow. The bottom of chip A and the top of chip B are wirebonded after the assembling. To provide mechanical support and exclude contaminants such as fingerprint residues which could disrupt circuit operation glob-top encapsulation is ©EDA Publishing/THERMINIC 2009 228 ISBN: 978-2-35500-010-2
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International Workshop on THERMal I
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7-9 October 2009, Leuven, Belgium
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Poster session: Introduction* 7-9 O
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x −1 V(x) = , f(y) = x + 1 y + 1
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of 75 o C for fair comparison. Only
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External Nodes (ne) European projec
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G 2 (resp. C 2 , F 2 ) and G 2e (re
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TABLE I MODEL PARTS CHARACTERISTICS
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OASIS files Final 2D layout design_
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III. SUMMARY In this study it was s
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