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due to a large thermal resistance in the part of parallel connection and a small resistance value in the part of serial connection, respectively. Thus, the materials of air and SiOB could be reasonably removed both in the model calculation and the CoventorWare simulation [7] so that more than 80% reduction of required mesh was achieved as well as the requirements of CPU and DRAM operation in this case. Fig. 5 (a) shows the probable paths of thermal flow predicted by the equivalent ETCM after removing the air and SiOB in the thermal conducting system. Since VCSEL and thermal via have comparable thermal conductivity (see Table. 1) and the thickness of the operating VCSEL and the adjacent one can have two-order magnitude larger than that of thermal via, the thermal via would become the main path of the thermal flow as the expectation in this work. Furthermore, the paths of the thermal flow depicted in Fig. 5 (b) extracted from the simplified thermal conducting system constructed in the simulation verify the validation of the equivalent ETCM by showing the possible paths of thermal flows on the principal components. The simulation results can not only obviously present the main paths of thermal flow as the prediction of the equivalent ETCM, but also indicate the hottest point that in the outermost corner of the operating VCSEL where the most far from the possible paths of the thermal flow. It is important to find out the hottest point in a thermal conducting system due to possible unexpected functionality degradation or even device failure due to a great quantity of thermal accumulation will easily happen at the point. In fact, according to the indications of derived equivalent ETCM, the value of the hottest point could always easily happen at the joints of the heating source and source of thermal flow and the hottest temperature should relate with the characteristics of material and geometry of Z 1 and 7-9 October 2009, Leuven, Belgium the conditions of boundary A. For the purpose of furthermore validation of mentioned characteristics of the hottest point, Fig. 6 shows the scheme of the simplified thermal conducting system with single operating VCSEL established by the equivalent ETCM. The model calculation of the temperatures of node points A, B, and C depicted in Fig. 6 are 80.2, 79.2, and 75°C, respectively. The results reveal that the hottest temperature is at node A and the main path of thermal flow is from node B to C as the prediction of the equivalent ETCM and having excellent match with simulation demonstration in Fig.5 (b). Therefore, it is worthy for system-IC designers and engineers to analyze the worsen cases at those joints and study the thermal behaviors of Z 1 and boundary A seriously by means of the network model or equivalent ETCM. Fig. 7 shows the IR microscope detected temperature distribution of SiOB heated by the operated VCSEL. The bottom of SiOB is constrained with a bias temperature A B Fig. 6. The scheme of the simplified thermal conducting system with single operating VCSEL established by the equivalent ETCM. The model calculation of the temperatures of node points A, B, and C are 80.2, 79.2, and 75°C. C (a) (b) Hottest point Fig. 5. (a) The simplified thermal conducting system established by the indication of the equivalent ETCM. The material of air and SiOB were removed in the system to reduce the required meshes as well as the CPU time. (b) The thermal flow on principal components extracted from CoventorWare simulation provides a verification of the equivalent ETCM. Hottest point was also labeled in the simulation result and indicated the point of possible unexpected functionality degradation or even device failure due to a great quantity of thermal accumulation. Fig. 7. The measured temperature distribution of SiOB heated by the operating VCSEL using IR microscope. Only a laser diode is operated by probe B with 8mA input current and 2V bias voltage. ©EDA Publishing/THERMINIC 2009 11 ISBN: 978-2-35500-010-2
of 75 o C for fair comparison. Only a laser diode is operated by probe B with 8mA input current and 2V bias voltage. The measured thermal distributions verified the validation of the simulation and model prediction shown in Fig. 5 and 6. Fig. 8 shows the comparison between the measurement, equivalent ETCM, and CoventorWare simulation results with and without air and SiOB, respectively. Excellent temperature matching within ±2°C indicates the validation and prediction of the equivalent ETCM and the practicality of the simplified structure in which we can have 90% CPU operation time saving due to 80% mesh number reduction. Besides, the slight temperature mismatch could be caused by the thermal impedance mismatch between the interfaces and the phonon vibration in high temperature. Fig. 8. Comparison between the presented model, measurement data, and simulated results with and without air, BCB and SiOB, respectively. Excellent temperature matching within ±2°C indicates the validation and prediction of the equivalent ETCM and the practicality of the simplified structure in which we can have 90% CPU operation time saving due to 80% mesh number reduction. 7-9 October 2009, Leuven, Belgium V. CONCLUSION The paper physically and conceptually presents a general electrothermal network π-model in system level. A associated equivalent electrothermal circuit model can be readily used for device optimization and CAD programming in terms of the demanding geometrical structure and characteristics of materials. The equivalent ETCM can also open a way for structure simplification and system optimization with high accuracy and achieve the goal of CPU time-saving in FEA simulation without complex and contrived mesh studying or scaling. Furthermore, the equivalent ETCM can predict the hottest point in the system to avoid the device failure or break-down. VI. ACKNOWLEDGMENT This work was supported by the 97-EC-17-A-07-S1-001 project at Optical Sciences Center, National Central University. REFERENCES [1] F. Tamigi, N. Nenadović, V. d’Alessandro, L. K. Nanver, N. Rinaldi, and J. W. Slotboom, “Modeling of thermal resistance dependenceon design parameters in silicon-on-glass bipolar transistors,” in Proc. IEEE 24th International Conference on Microelectronics, vol. 1, pp.257-260, Niš, Serbia-Montenegro, May 2004. [2] A. M. Darwish, A. J. Bayba, and H. A. Hung, “Accurate determination of thermal resistance of FETs,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, January 2005. [3] A. H. Ajami, K. Banerjee, M. Pedram, “Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, pp.849-861, June 2005. [4] B. Goplen and S. Sapatnekar, “Thermal Via Placement in 3D ICs,” Proceedings of the 2005 international symposium on Physical design, pp.167-174, April 2005. [5] K. Vanmeensel, A. Laptev, J. Hennicke, J. Vleugels, and O. V. der Biest, “Modeling of the temperature distribution during field assisted sintering,” Acta Materialia, vol. 53, pp.4379-4388, August 2005. [6] A. J. Kemp, G. J. Valentine, J.-M. Hopkins, J. E. Hastie, S. A. Smith, S. Calvez, M. D. Dawson, and D. Burns, “Thermal Management in Vertical-External-Cavity-Surface-Emitting Lasers: Finite-Element Analysis of a Heatspreader Approach,” IEEE Journal of Quantum Electronics, vol. 41, pp.148-155, February 2005. [7] CoventorWare 2008, http://www.coventor.com/, version 2008. ©EDA Publishing/THERMINIC 2009 12 ISBN: 978-2-35500-010-2
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