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A representative device was measured and the temperature contours were presented. A computational tool as well as an embedded diode was used to validate the results. While the results of the numerical simulation validate the experimental results, the diode readings were significantly off. After a brief numerical investigation it was found that indeed the location and construction of the diode sensor were not ideal, and thus the embedded device could not be used in this case to successfully validate the experimental data. REFERENCES [1] W. Claeys, D. Dilhaire, V. Quintard, J.P. Dom, and Y. Danto, “Thermoreflectance Optical Test Probe for the Measurement of Current-Induced Temperature Changes in Microelectronic Components,” Reliability Engineering International, Vol. 9, pp. 303-308, 1993. [2] Z. Bian, J. Christofferson, A. Shakouri, and P. Kozodoy, “High- Power Operation of Electroabsorption Modulators”, Applied Physics Letters - Vol. 83, No.17, pp. 3605-3607, 2003. [3] P. L. Komarov, M. G. Burzo, and P. E. Raad, “A Thermoreflectance Thermography System for Measuring the Transient Surface Temperature Field of Activated Electronic Device,” Proceedings to the 22nd Semiconductor Thermal Measurement, Modeling, and Management Symposium (SEMITHERM), Dallas, Texas, March 14-16, 2006. 7-9 October 2009, Leuven, Belgium [4] M. G. Burzo, P. L. Komarov, and P. E. Raad, “Thermal Transport Properties of Gold-Covered Thin-Film Silicon Dioxide”, IEEE Transactions on Components and Packaging Technologies, Vol. 26(1), pp. 80-88, 2003. [5] G. L. Eesley, “Surface Raman Ellipsometry,” J. of Quantum Electronics, Vol. 17, No. 7, p. 1285, 1981. [6] P. E. Raad, P. L. Komarov, and M. G. Burzo, ”Thermal characterization of embedded electronic features by an integrated system of CCD thermography and self-adaptive numerical modeling,” Microelectronics Journal, Vol. 39, Issue 7, pp. 1008- 1015, 2008. [7] P. Vairac, B. Cretin, B., M. Genix, B. Charlot, S. Dilhaire, S. Gomès, G. Tessier, N. Trannoy, and S. Volz, , “Ultra-local temperature mapping with an intrinsic thermocouple,” 11th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), Belgirate, Lake Maggiore, Italy, 27 - 30 September 2005 [8] P. E. Raad, J. S. Wilson, and D. C. Price, “System and Method for Predicting the Behavior of a Component,” U.S. Patent No. 6,064,810 (2000), Korean Patent No. 0501053 (2005), Japanese Patent No. 3,841,833 (2006). [9] J. S. Wilson and P. E. Raad, “A Transient Self-Adaptive Technique for Modeling Thermal Problems with Large Variations in Physical Scales,” International Journal of Heat and Mass Transfer, Vol. 47, pp. 3707-3720, 2004. ©EDA Publishing/THERMINIC 2009 135 ISBN: 978-2-35500-010-2
7-9 October 2009, Leuven, Belgium Practical Study of Temperature Distribution in a Thermal Test Integrated Circuit M. Janicki, M. Szermer, S. Klab, Z. Kulesza, A. Napieralski Department of Microelectronics and Computer Science, Technical University of Lodz Wolczanska 221/223, 90-924 Lodz, Poland Abstract-This paper presents measurements and simulations of a test integrated circuit. The circuit contains a matrix of heat sources and a set of temperature sensors, what renders possible measurement of circuit temperature in real cooling conditions inside a closed package. The measurements are validated for different patterns of power dissipation and cooling conditions with numerical simulations. Based on the presented results, the influence of circuit topology on temperature distribution and its impact on the possibility of heat source temperature estimation are discussed. I. INTRODUCTION Due to high power densities dissipated in state-of-the-art integrated circuits, there appeared the need for continuous monitoring of circuit temperature. Because of significant temperature gradients occurring in such circuits, it is not enough to use a single temperature sensor and some more sophisticated solutions should be developed for real time temperature monitoring. Such monitoring circuits, integrated together with the monitored ones within a single IC, would not only protect circuits from overheat but also could provide useful feedback for design engineers. The concept of real time circuit temperature monitoring for power circuits is known already from the early nineties. However, recently an entirely new possible application has emerged for such monitoring systems in the field of chip multiprocessor design [1]-[3]. With the advent of multicore architectures, the exploration of the entire design space has become a task of extreme importance from the performance point of view. Knowing the exact temperature distribution within an operating chip, engineers could design much more efficient architectures and multithread algorithms as well as develop new strategies for active voltage and frequency scaling so as to maximize performance while maintaining chip temperature within allowed safety margins. This paper, based on a practical example of a thermal test circuit, examines the influence of power dissipation pattern and circuit cooling conditions on temperature distribution. The following section is devoted to the description of the test circuit. Then, thermal simulation results are analyzed and compared with measurements. Next, important conclusions regarding the possibility of realizing real time temperature monitoring circuit are provided. Fig. 1. Thermal test chip photograph. II. TEST CIRCUIT DESCRIPTION The test circuit was designed entirely in the Department of Microelectronics and Computer Science of the Technical University of Lodz and manufactured in the 0.35 micron high voltage technology by austriamicrosystems ® . The general photograph of the chip is shown in Fig. 1. The die dimensions are 4.83 mm x 4.11 mm. In this paper, the presentation of the circuit is limited only to the description of the components, which are the most important from the temperature profile investigation point of view, that is the heat sources and the temperature sensors. For a more complete description of the design, refer to [4]. Additionally, it should be mentioned that this circuit does not fulfil all the JEDEC requirements for a standard thermal test chip, unlike those described in [5]-[6], because it was developed also for other purposes. A. Heat Sources The 620 μm x 40 μm heat sources, visible in the above photograph, form a 3 x 3 matrix and consist of compound high voltage 50 V NMOS transistors. These sources operate for power supply voltages 20÷50 V and can be individually switched on or off at any of 7 current levels evenly spread up to 21 mA. Owing to this solution, it was possible to attain high flexibility of power dissipation inside the chip. ©EDA Publishing/THERMINIC 2009 136 ISBN: 978-2-35500-010-2
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