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7-9 October 2009, Leuven, Belgium Electro-Thermal Modeling of Nano-Scale Devices D. Vasileska 1 , K. Raleva 2 and S. M. Goodnick 1 1 Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706, USA 2 Faculty of Electrical Engineering and Information Technology, University Sts. Cyril and Methodius, Skopje, Republic of Macedonia Abstract-In this paper we present simulation results obtained with our electro-thermal device simulator when modeling different technology generations of FD-SOI devices. In particular, we stress out the importance of the temperature boundary conditions for digital and analog circuits and the use of the full model which takes into account both temperature and thickness dependence (which is particularly important for thin silicon films) of the thermal conductivity. Key-words: electro-thermal modeling, FDSOI devices, particle-based device simulations I. INTRODUCTION The scaling of semiconductor devices into the nanometer regime and the problems associated with further miniaturization of device technologies has resulted into investigation of devices with alternative materials and alternative device designs such as fully-depleted (FD), dualgate (DG), tri-gate silicon-on-insulator (SOI) and other device designs. The problem with SOI devices is that they exhibit selfheating effects. These self-heating effects arise from the fact that the underlying SiO 2 layer has about 100 times smaller thermal conductivity than bulk Si (1.4 W/m/K). Also, the thickness of the silicon film in nanoscale devices is much smaller than the phonon mean free path which is on the order of 300 nm in bulk silicon. Therefore, boundary scattering becomes dominant scattering mechanism, thus reducing the thermal conductivity value to a fraction of its bulk value. For example, the bulk thermal conductivity in silicon is 148 W/m/K and the thermal conductivity of a silicon film of thickness of 10 nm is 13 W/m/K (a factor of 10 smaller than the bulk value). Also, in thin silicon films the thermal conductivity has smaller temperature dependence because boundary scattering is temperature independent scattering process. II. THE ROLE OF THE TEMPERATURE BOUNDARY CONDITIONS In analog devices neighboring devices are typically on and if the gate contacts are also biased then there is no heat flow through the gate contact and the side boundaries. In these cases it is appropriate to use Neumann boundary conditions on the side (artificial) boundaries and Neumann boundary conditions on the gate electrode. Simulation results for the current degradation for different technology of FD SOI devices, summarized in Table 1, are presented in Figure 1. In the case of digital circuits, the devices are rarely on and the use of Dirichlet boundary conditions at the gate and the side boundaries are the appropriate boundary conditions. This corresponds to the best-case scenario of heat removal from the device active region. Simulation results for the current degradation for different technology devices when Dirichlet boundary conditions are applied to the gate and the side boundaries, are shown in Figure 2. Table 1. Parameters for various simulated device technology nodes (constant field scaling) [1]. L (nm) tox (nm) t Si (nm) t box (nm) N ch (cm -3 ) V GS=V DS (V) I D (mA/um) 25 2 10 50 1×10 18 1.2 1.82 45 2 18 60 1×10 18 1.2 1.41 60 2 24 80 1×10 18 1.2 1.14 80 2 32 100 1×10 17 1.5 1.78 90 2 36 120 1×10 17 1.5 1.67 100 2 40 140 1×10 17 1.5 1.57 120 3 48 160 1×10 17 1.8 1.37 140 3 56 180 1×10 17 1.8 1.23 180 3 72 200 1×10 17 1.8 1.03 L- Gate Length; tox- Gate Oxide Thickness; t Si- Active Si Layer Thickness; t box- BOX Thickness; N ch- Channel Doping Concentration; I D- Isothermal current value (300K). Degradation (%) 100 75 50 25 300K 400K 600K Neumann 0 50 100 150 Gate Length (nm) Figure 1. Current degradation vs. technology generation ranging from 25 nm to 180 nm channel length FD SOI devices (Table 1). Isothermal boundary condition of 300K is set on the bottom of the BOX. Parameter is the temperature on the gate electrode. Neumann boundary conditions are applied at the vertical sides. Degradation (%) 100 80 60 40 20 300K Neumann 0 50 100 150 Gate Length (nm) Figure 2. Current degradation for the case of Dirichlet boundary conditions at the artificial boundaries. In one case Dirichlet boundary conditions are applied at the gate electrode with T Gate=300 K and in the second case Neumann boundary conditions are applied at the gate electrode. ©EDA Publishing/THERMINIC 2009 195 ISBN: 978-2-35500-010-2
III. TEMPERATURE AND THICKNESS DEPENDENT THERMAL CONDUCTIVITY MODEL In order to perform more realistic estimates of the current degradation using temperature and thickness dependent thermal conductivity model we follow the work of Sondheimer [2], that takes into account phonon boundary scattering (by assuming it to be purely diffusive). Namely, the thermal conductivity of a semiconductor film of a thickness a, under the assumption that the z-axis is perpendicular to the plane of the film, the surfaces of the film being at z=0 and z=a, is given by: π /2 ⎧ 3 ⎛ a ⎞ ⎛ a−2z ⎞⎫ κ() z = κ0() T sinθ 1−exp − cosh dθ (1) ∫ ⎨ ⎜ ⎟ ⎜ ⎟⎬ 2()cos λT θ 2()cos λT θ 0 ⎩ ⎝ ⎠ ⎝ ⎠⎭ where λ(T) is the mean free path expressed as λ( T) = λ0 (300/ T) nm where room temperature mean free path of bulk phonons is taken to be λ 0 = 290 nm. Selberherr [3,4] has parametrized the temperature dependence of the bulk thermal conductivity in the temperature range between 250K and 1000K. In our case we find that the appropriate expression is: 135 κ 0( T ) = W/m/K (2) 2 a + bT + cT where a=0.03, b=1.56×10 -3 , and c=1.65×10 -6 . Eqs. (1) and (2) give almost perfect fit to the experimental and the theoretical data reported in an Asheghi paper [5] (see Figure 3). In Table 2 we compare electro-thermal simulation results for various models for two different device gate lengths (25 nm and 180 nm). Dirichlet boundary conditions are assumed on the gate and back contact (300K), and the other boundaries are treated as Neumann boundary conditions (no heat flow). Thermal conductivity (W/m/K) 80 60 40 experimental data full lines: BTE predictions dashed lines: empirical model thin lines: Sondheimer 100nm 50nm 30nm 20 20nm 300 400 500 600 Temperature (K) Figure 3. Silicon film thickness dependence of the average thermal conductivity at T=300 K vs. active silicon layer thickness. Experimental data are taken from the work of Asheghi and co-workers [5]. In Fig. 4, we show the temperature maps in the active region of the 25 nm and 180 nm channel length device with the full anisotropic and temperature dependent thermal conductivity model. Compared to earlier results [6], we find that the anisotropic and temperature dependent thermal conductivity model leads to higher lattice temperature profiles 7-9 October 2009, Leuven, Belgium at the drain end of the channel and in the channel itself for larger device structures even though the current degradations are very similar. This makes the heat removal process from the drain contact more difficult. Table 2. Absolute values of the currents for: (1) bulk thermal conductivity model, (2) temperature-dependent bulk thermal conductivity model, (3) anisotropic thickness dependent thermal conductivity model, and (4) anisotropic thickness and temperature dependent thermal conductivity model. 25nm FD SOI (V GS=V DS=1.2V) 180nm FD SOI (V Thermal GS=V DS=1.8V) Current (isothermal):1.824mA/um Current (isothermal):1.032mA/um conductivity Current Current Current Current model (mA/um) Decrease (%) (mA/um) Decrease (%) 142.3 W/m/K 1.714 6.0 0.922 10.7 κ bulk=κ bulk(T) 1.712 6.1 0.915 11.3 anisotropic 1.698 6.9 0.887 14.0 13 W/m/K 1.702 6.7 0.875 15.2 2 4 6 8 10 383K 528K 25 50 75 500 450 400 520 20 500 480 40 450K 539K 460 60 440 420 0 180 360 540 Figure 4. Lattice temperature for a 25 nm channel length device (top) and a 180 nm gate-length device (bottom). ACKNOWLEDGMENT This work was supported in part by the Arizona Institute for NanoElectronics (AINE). REFERENCES [1] ITRS for FD SOI devices: http://public.itrs.net/ . [2] E. H. Sondheimer, “The Mean Free Path of Electrons in Metals”, Advances in Physics, Vol. 1, no. 1, Jan. 1952, reprinted in Advances in Physics, Vol. 50, pp. 499-537, 2001. [3] V. Palankovski and S. Selberherr, „Micro materials modeling in MINIMOS-NT“, Journal Microsystem Technologies, Vol. 7, pp. 183- 187 November, 2001. [4] Silvaco Manual (www.silvaco.com). [5] W. Liu and M. Asheghi, “Thermal condition in ultrathin pure and doped single-crystal silicon layers at high temperatures”, J. Appl. Phys., Vol. 98, 123523-1 (2005). [6] K. Raleva, D. Vasileska, S. M. Goodnick and M. Nedjalkov, “Modeling Thermal Effects in Nanodevices”, IEEE Transactions on Electron Devices, vol. 55, issue 6, pp. 1306-1316, June 2008. Biography of Dragica Vasileska: Dragica Vasileska (B.S.E.E. 1985, M.S.E.E. 1992, Ph.D. 1995). From 1995 until 1997 she held a Faculty Research Associate position at ASU. In 1997 she joined the faculty of Electrical Engineering at ASU. Her research interests include semiconductor device physics and device modeling. Dr. Vasileska has published more than 120 journal publications. ©EDA Publishing/THERMINIC 2009 196 ISBN: 978-2-35500-010-2
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