Online proceedings - EDA Publishing Association

More documents

Recommendations

Info

Voltage [V] 0.8 0.78 0.76 0.74 0.72 0.7 0.68 0.66 0.64 0.62 Meas. - Observed Meas. - Fitted Simulations 0.6 20 30 40 50 60 70 80 90 100 Temperature [C] Fig. 7. Simulations vs. measurements. Unfortunately, the use of high voltage technology required the placement of additional guard rings between transistors and resistors. This was necessary because inside the chip also high voltage transistors are used as the heat sources. Therefore, the PTAT sensor, as an analog circuit, should be isolated, otherwise other circuits could disturb its operation. The sensor operation was tested on a measurement stand with forced water cooling in the temperature range from 30 °C to 95 °C. The measurements of the manufactured PTAT sensor are compared with the earlier simulations in Fig. 7. As can be seen, the measured output characteristic is almost linear and has a negative slope of –1.74 mV/K, which is almost the same as the simulated one. However, the measurements reveal a small voltage offset of 20 mV. The most probably this offset is caused by the polysilicon resistor, whose resistance could be different than the one in the design, due to technological parameter scattering. Because so far only water cooling was used, the operation of the sensor was investigated only under 100 °C, so the verification of the overheat warning circuit could not be carried out. Currently the measurement stand is being 7-9 October 2009, Leuven, Belgium modified through the introduction of Peltier thermo-electric modules and the dual cold plates. Then, such a verification and further sensor calibration in higher temperatures will be possible. V. CONCLUSIONS The design and the simulations of a PTAT sensor were presented in this paper. The measurements of the manufactured circuit confirmed the proper sensor operation. This sensor, integrated with the overheat protection circuit, can be reused as a stand-alone device. Through the proper dimensioning of MOS transistor channels the triggering temperature of the protection circuit and the hysteresis size can be adjusted. ACKNOWLEDGMENT This work was supported by the Ministry of Science and Higher Education grant No. N515 008 31/0331. REFERENCES [1] V. Szekely, “Thermal Monitoring of Microelectronic Structures”, Microelectron. J., Vol. 25, pp. 157-170, May 1994 [2] W. Wojciak, A. Napieralski, “Thermal monitoring of a single heat source in semiconductor devices – the first approach” Microelectron. J., Vol. 28, No 3, pp. 313-316, March 1997 [3] Chih-Ming Chang, Herming Chiueh, “A CMOS Proportional–To– Absolute Temperature Reference for Monolithic Temperature Sensors”, THERMINIC 2004, Sophia Antipolis, Cote d’Azur, France, 29 September – 1 October 2004 [4] M. Szermer and A. Napieralski, “The PTAT Sensors in CMOS Technology”, 2005 International Semiconductor Conference, 28th Edition, Sinaia, Romania, 3-5 October, 2005, Vol. 1, pp.197-200 [5] W. Wojciak, A. Napieralski, M. Zubert, M. Janicki “Thermal monitoring in integrated power electronics – new concept”, EPE’97, Trondheim, Norway 8–10 September 1997, pp. 2.906-2.910. [6] M. Szermer, Z. Kulesza, M. Janicki, A. Napieralski, “Test ASIC for Real Time Estimation of Chip Temperature”, NSTI Nanotech 2008, Hynes Convention Center, Boston, Massachusetts, USA, 1-5 June 2008, Vol.3, pp. 529-532 [7] M. Szermer, Z. Kulesza, M. Janicki, A. Napieralski, “Design of the Test ASIC for on-line Temperature Monitoring and Thermal Structure Analysis”, 15th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2008, Poznan, Poland, 19-21 June 2008, pp. 317-320 ©EDA Publishing/THERMINIC 2009 83 ISBN: 978-2-35500-010-2
7-9 October 2009, Leuven, Belgium Thermo-Mechanical Reliability Loop In Device Modeling T. Bieniek, G. Janczyk, P. Grabiec, J. Szynka Institute of Electron Technology Al. Lotnikow 32/46 02-668, Warsaw, POLAND Abstract- 3D device integration faces the designers with new thermo-mechanical design and device exploitation problems. Temperature dependent mechanical stress spreading across the device affects its performance. This paper discusses selected performance and reliability issues related device the mechanical stress and temperature influence. Keywords: Thermo-mechanical modeling, device reliability, integrated modeling, stress affection I. INTRODUCTION Evolving demands on device functionality, reliability and performance result in various paths of engineering technology development and handle with Moore’s law. Fundamental constrains of physics are getting closer and more important as devices are continuously downscaled. Therefore to make devices more robust and powerful architecture tricks and 3D integration technologies have to be exploited. Several research projects like e-Cubes [1] or Corona [2] and many other stimulate R&D efforts in such fields as design-flow speed-up accompanied by development of integration technology. The main idea of the e-Cubes project consists in assemble of the particular number of chip-modules into the one heterogeneous MEMS/MOEMS device assembled as a vertical stack of the electrically, thermally and mechanically connected modules. It is a 3D integration technique developed to make device as universal and robust as possible. Another aim is to reach the best device performance by means of applying the technology perfectly fitting customer device requirements. It is close to Corona project ideas to reduce time-to-market by optimizing the product engineering flow from an idea through the design to the final device fabrication. Knowledge based, spread cooperation designers and manufacturers framework should be ready to incorporate customer feedback and active cooperation in field of their idea hardware implementation. The Corona project research area covers innovations in integrated design methodology and production flow. Methodology and tools used for multidomain modeling and simulation are especially important for the product development process and device reliability control. From the economic point of view it is necessary to reduce costs by means of time and redundant design efforts reduction now necessary before the final technological run. II. MODELING AND SIMULATIONS Selected reliability issues like thermo-mechanical behavior of the whole integrated MEMS/MOEMS device and mechanical stress which spreads through the device substrate have been discussed in this paper. 3D device integration techniques relies on multi module stack formed of silicon slices, mechanically assembled by vertical connections [3, 4] that support mechanical integrity of 3D integrated device and provide both: electrical and thermal connections between stacked modules. Semiconductor memories, microprocessors, CMOS image sensors and various heterogeneous systems are the main application for 3D integration technologies incorporating vertical integrating elements supporting electrical, thermal and mechanical connections. Among several solutions developed in frames of eCubes project – though silicon via (TSV) formed from conducting materials like Cu, W, TiN can be applied for 3D heterogeneous integration. Single TSV is inserted as a nail into deep, narrow holes (high aspect ratio) etched through the silicon wafer substrate. Each TSV goes through the whole substrate. The quality of TSV affects the device reliability and performance. As the temperature distribution is dependent on heat dissipation in the device it is affected by TSV thermal parameters. It also introduces additional mechanical stress into the device and affects device reliability and performance. Fundamental parameters of semiconductor device like silicon crystallographic orientation, carrier density, band-gap width and carrier mobility affect the device performance. As the device reliability is dependent on mechanical stress distribution, it should be accurately modeled to predict and control the device performance. All above mentioned fundamental device physical parameters are affected by temperature and depend on mechanical stress distribution, which is yet another parameter to be taken into account for estimation of the device reliability. Fig. 1. Mechanical stress value spreads across the wafer. Affection on transistor parameters and performance varies in dependence of transistor and stress source locations. ©EDA Publishing/THERMINIC 2009 84 ISBN: 978-2-35500-010-2
Page 1 and 2:
International Workshop on THERMal I
Page 3 and 4:
7-9 October 2009, Leuven, Belgium
Page 5 and 6:
Page 7 and 8:
Page 9 and 10:
Poster session: Introduction* 7-9 O
Page 11 and 12:
7-9 October 7-9 October 2009, 2009,
Page 13 and 14:
7-9 October 2009, Leuven, Belgium T
Page 15 and 16:
7-9 October 2009, Leuven, Belgium u
Page 17 and 18:
7-9 October 2009, Leuven, Belgium p
Page 19 and 20:
7-9 October 2009, Leuven, Belgium E
Page 21 and 22:
x −1 V(x) = , f(y) = x + 1 y + 1
Page 23 and 24:
of 75 o C for fair comparison. Only
Page 25 and 26:
II. GCS DESIGN AND FIELD TEST 7-9 O
Page 27 and 28:
7-9 October 2009, Leuven, Belgium a
Page 29 and 30:
External Nodes (ne) European projec
Page 31 and 32:
G 2 (resp. C 2 , F 2 ) and G 2e (re
Page 33 and 34:
TABLE I MODEL PARTS CHARACTERISTICS
Page 35 and 36:
II. DEVELOPMENT OF CTM FOR SFP The
Page 37 and 38:
7-9 October 2009, Leuven, Belgium r
Page 39 and 40:
Page 41 and 42:
7-9 October 2009, Leuven, Belgium I
Page 43 and 44: 7-9 October 2009, Leuven, Belgium u
Page 45 and 46: 7-9 October 2009, Leuven, Belgium s
Page 47 and 48: 7-9 October 2009, Leuven, Belgium N
Page 49 and 50: 7-9 October 2009, Leuven, Belgium s
Page 51 and 52: 7-9 October 2009, Leuven, Belgium D
Page 53 and 54: 7-9 October 2009, Leuven, Belgium b
Page 55 and 56: 7-9 October 2009, Leuven, Belgium C
Page 57 and 58: OASIS files Final 2D layout design_
Page 59 and 60: 7-9 October 2009, Leuven, Belgium B
Page 61 and 62: 7-9 October 2009, Leuven, Belgium E
Page 63 and 64: 7-9 October 2009, Leuven, Belgium 3
Page 65 and 66: 7-9 October 2009, Leuven, Belgium b
Page 67 and 68: 7-9 October 2009, Leuven, Belgium T
Page 69 and 70: 7-9 October 2009, Leuven, Belgium F
Page 73 and 74: Thermal behaviour causes some varia
Page 75 and 76: on devices of long-term storage at
Page 79 and 80: Fig. 3. Standard package simulation
Page 83 and 84: ∂ 2 T ∂ x ∂2 T T 2 ∂ y 2
Page 87 and 88: q h T h 7-9 October 2009, Leuven, B
Page 91 and 92: 7-9 October 2009, Leuven, Belgium P
Page 93: 7-9 October 2009, Leuven, Belgium 0
Page 97 and 98: 7-9 October 2009, Leuven, Belgium c
Page 99 and 100: is used to model the forward polari
Page 101 and 102: 7-9 October 2009, Leuven, Belgium I
Page 103 and 104: 7-9 October 2009, Leuven, Belgium 1
Page 105 and 106: III. SUMMARY In this study it was s
Page 107 and 108: where V is open-circuit voltage, r
Page 109 and 110: V. THERMAL MATCHING IN LOW-DIMENSIO
Page 111 and 112: Fig. 8. Low-power wireless medical
Page 117 and 118: 7-9 October 2009, Leuven, Belgium C
Page 119 and 120: 7-9 October 2009, Leuven, Belgium
Page 123 and 124: 7-9 October 2009, Leuven, Belgium [
Page 125 and 126: 7-9 October 2009, Leuven, Belgium R
Page 127 and 128: III. FINITE ELEMENT MODELLING OF BG
Page 129 and 130: 7-9 October 2009, Leuven, Belgium I
Page 131 and 132: 7-9 October 2009, Leuven, Belgium V
Page 133 and 134: I OLED 7-9 October 2009, Leuven, Be
Page 141 and 142: 7-9 October 2009, Leuven, Belgium P
Page 143 and 144: 7-9 October 2009, Leuven, Belgium r
Page 145 and 146:
Fig. 5 Computed absolute temperatur
Page 147 and 148:
7-9 October 2009, Leuven, Belgium P
Page 149 and 150:
7-9 October 2009, Leuven, Belgium F
Page 151 and 152:
7-9 October 2009, Leuven, Belgium C
Page 153 and 154:
ETF ∫ VCO f vco (T) output 7-9 Oc
Page 155 and 156:
7-9 October 2009, Leuven, Belgium H
Page 157 and 158:
profile describes the temperature v
Page 159 and 160:
In Fig. 9 (a) the same integer work
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
meshes with highest heat removal ra
Page 167 and 168:
[5] P. Lee and S. Garimella, “Hot
Page 169 and 170:
Page 171 and 172:
7-9 October 2009, Leuven, Belgium o
Page 173 and 174:
In contrast to earlier results pres
Page 175 and 176:
7-9 October 2009, Leuven, Belgium (
Page 177 and 178:
7-9 October 2009, Leuven, Belgium 0
Page 179 and 180:
Page 181 and 182:
hosing fittings etc.) were ‘off t
Page 183 and 184:
Page 185 and 186:
©EDA Publishing/THERMINIC 2009 174
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
The spray boiling curves obtained i
Page 195 and 196:
along the measure zone over the hea
Page 197 and 198:
Page 199 and 200:
7-9 October 2009, Leuven, Belgium f
Page 201 and 202:
7-9 October 2009, Leuven, Belgium t
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
III. TEMPERATURE AND THICKNESS DEPE
Page 209 and 210:
7-9 October 2009, Leuven, Belgium d
Page 211 and 212:
7-9 October 2009, Leuven, Belgium s
Page 213 and 214:
7-9 October 2009, Leuven, Belgium h
Page 215 and 216:
an increasing function of its TE fi
Page 217 and 218:
7-9 October 2009, Leuven, Belgium (
Page 219 and 220:
The regime transition at λ β = 1.
Page 221 and 222:
Page 223 and 224:
Page 225 and 226:
7-9 October 2009, Leuven, Belgium k
Page 227 and 228:
Page 229 and 230:
7-9 October 2009, Leuven, Belgium r
Page 231 and 232:
transient is measured by the transi
Page 233 and 234:
Page 235 and 236:
Page 237 and 238:
7-9 October 2009, Leuven, Belgium s
Page 239 and 240:
Page 241 and 242:
onding it was compressed down to ~6
Page 243 and 244:
7-9 October 2009, Leuven, Belgium M
Page 245:
7-9 October 7-9 October 2009, 2009,
show all

Online proceedings - EDA Publishing Association

Create successful ePaper yourself

Delete template?

Save as template?