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7-9 October 2009, Leuven, Belgium Fig. 7. Temperature evolution at the junction in liquid-cooling based systems using finite-element simulation and the proposed model for straight liquid cooling channels All in all, these experiments outline the potential benefits of the proposed HW/SW thermal emulation framework to explore the design space of complex thermal management policies in 2D/3D MPSoCs, compared to exiting methods based on SW cycle-accurate simulators or finite-elements simulation, which suffer from very important speed limits for long simulations, necessary to achieve representative transient thermal analysis of real systems. VI. CONCLUSIONS 2D and emerging 3D MPSoC architectures have been proposed as a promising solution to exploit the available area in forthcoming computing systems. In this paper I have presented a new HW/SW FPGA-based emulation framework that enables the rapid analysis of run-time thermal behavior in 2D/3D MPSoCs with active liquid cooling. The experimental results have shown that the proposed framework obtains detailed transient thermal exploration with a speed-up of more than 1000× with respect to cycle-accurate MPSoC simulators, even more when active (liquid) cooling effects are considered in the overall thermal system analysis. Furthermore, almost no loss in thermal estimation accuracy (less than 3%) is experienced with respect to classical (and very time-consuming) finite-element simulations. Overall, this HW/SW thermal emulation approach is a promising mechanism to perform long-time transient behavior characterization in 2D and 3D MPSoC stacks. ACKNOWLEDGMENT The author would like to thank Ayse K. Coskun and Prof. Tajana Simunic Rosing from UCSD, Prof. Luca Benini at Bologna University, and the group of Advanced Packaging Technologies at IBM Zürich for their useful feedback and inputs in the validation of the 3D thermal modeling and liquid cooling technology. This work has been supported in part by the Swiss NanoTera NTF Project - CMOSAIC, and a FPGA donation of the OpenSPARC University Program of Sun Microsystems. REFERENCES [1] D. Pham et al., Design and Implementation of a First-Generation Cell Processor., Proc. ISSCC, 2005. [2] P. Kongetira et al.,Niagara: A 32-way multithreaded SPARC processor., IEEE Micro, 2005. [3] Tilera Corporation, Tilera’s 64-core architecture, 2008, www.tilera.com/products/processors.php [4] W. Davis, et al., Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Des&Test, 2005. [5] M. Healy, et al., Multiobjective microarchitectural floorplanning for 2D and 3D ICs. IEEE Transactions on CAD, 2007 [6] K. Skadron et al., Temperature-aware microarchitecture: Modeling and implementation (Hot-spot simulator), IEEE TACO, 2004 [7] G. Paci et al., Exploring temperature-aware design in low-power MPSoCs, Proc. DATE, 2006. [8] M.-N. Sabry, High-precision thermal models, IEEE TCPT, 2005. [9] Cadence Palladium II, 2005. http://www.cadence.com. [10] ARM integrator AP, 2004. http://www.arm.com. [11] Emulation Engineering. Zebu models, http://www.eve-team.com. [12] T. Brunschwiler et al., Direct liquid-jet impingement cooling with micron-sized nozzle array and distributed return architecture. Proc. ITHERM, 2006. [13] T. Brunschwiler, et al., Interlayer cooling potential in vertically integrated packages, Microsyst. Technologies, 2008. [14] F. Mulas et al., Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures, Proc. DATE, 2008. [15] D. Atienza, et al., A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. Proc. DAC, 2006. [16] B. Richard, et al., Numerical Analysis, Brooks Cole, 2000. [17] A.K. Coskun, et al., Dynamic Thermal Management in 3D Multicore Architectures, Proc. DATE, 2009. [18] A. Jerraya, et al. Multiprocessor SoCs. Morgan Kaufmann, 2005. [19] G. Braun, et al. Processor/memory co-exploration on multiple abstraction levels. Proc. DATE, 2003. [20] P. S. Magnusson, et al. Simics: A full system simulation platform. IEEE Computer, 2002. [21] P. Paulin, et al. Stepnp: A system-level exploration platform for network processors, IEEE Des&Test , 2002. [22] Coware, Convergence and Lisatek product lines, 2006. http://www.coware.com [23] ARM, PrimeXSys platform architecture and methodologies, white paper, 2005, http://www.arm.com/ [24] Heron Engineering, SoCemulation, 2004, http://www.hunteng.co.uk [25] M. D. Nava, et al., An open platform for developing MPSoC, IEEE Computer, 2005. [26] Y. Nakamura, A fast HW/SW co-verification method for SoC by using a C/C++ simulator and FPGA emulator with shared register communication, Proc. of DAC, 2004. [27] Mentor Graphics, Platform express and primecell, 2005, http://www.mentor.com/ [28] Synopsys, Realview Max-sim ESL Exploration Framework, 2004, http://www.synopsys.com/ [29] T.-Y. Chiang, et al, Thermal analysis of heterogeneous 3-D ICs with various integration scenarios, Proc. of IEDM, 2001. [30] A. Rahman, et al., Thermal analysis of three-dimensional integrated circuits, Proc. of IITC, 2001. [31] P. Leduca et al., Challenges for 3d IC integration: bonding quality and thermal management, Proc. of IITC, 2007. [32] K. Puttaswamy, et al., Thermal analysis of a 3d die-stacked highperformance microprocessor, Proc. of GLSVLSI, 2006. [33] A. Jain, et al., Thermal modeling and design of 3D integrated circuits, Proc. of ICTTPES, 2008. ©EDA Publishing/THERMINIC 2009 55 ISBN: 978-2-35500-010-2
7-9 October 2009, Leuven, Belgium Thermal Analysis of Hot Spots in Advanced 3D- Stacked Structures C. Torregiani 1 , B. Vandevelde 1 , H. Oprins 1 , E. Beyne 1 , I. De Wolf 1,2 1 IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium 2 MTM Dept., K.U.Leuven,Kastelpaark Arenberg 10, B-3001 Heverlee, Belgium Email: cristina.torregiani@imec.be Abstract- 3D integration architectures for microelectronic circuits have attracted much interest in the recent past, due to their capabilities for more efficient device integration and faster circuit operation. This type of assembly is formed by bonding multiple active layers through a dielectric material, and employs through-silicon vias for electrical interconnection. In this work we present the thermal analysis of a typical 3Dstack, performed by finite element simulations. The effect of the variation of various parameters on the area of influence of a hot spot and on the overall temperature in the stack has been analyzed. We have also investigated the thermal impact of copper studs in the dielectric: the results suggest that Cu studs with a small pitch in the glue can efficiently reduce the temperature in the Si dies. I. INTRODUCTION Thermal management for electronic devices, circuits, and packages has become an issue of concern during the last years, and even more of a concern for vertically integrated stacked structures. The determination of the temperature distribution in 3D systems has become an increasingly important need: the increase in power dissipation per die and in the number of stacked dies, together with the use of poorly conductive interface layers limits the dissipation of heat generated by electronic devices [1-5]. The problem is made worse by the fact that the power in electronic systems is usually dissipated in localized regions (so called hot spots). This causes an increase in thermal resistance due to heat spreading effects, and it makes the temperature distribution non-homogeneous over the dies. The advanced 3D stacked die assembly considered in this paper can be simply described as a stack of dies separated by interface layers. The assembly is attached to a package with a specified thermal resistance. The ambient conditions define the case-to-ambient thermal resistance. II. METHODOLOGY In this paper a vertically stacked structure is modeled using a finite element code [6]. The structure is composed by three silicon dies including the back-end-of-line (BEOL) layers. The active layers are attached to each other by a polymer, functioning both as glue and dielectric. The reason why the BEOL is also modeled as an additional layer is that it has a relatively low thermal conductivity, which is mainly dominated by the low thermally conductive dielectric [7]. A fixed reference temperature, chosen to be 0 0 C, is considered as boundary condition at the back side of the stacked structure, while the four sidewalls and the top surface are considered adiabatic. These boundary conditions can be viewed as a first order approximation of a real stack embedded in a poorly thermally conductive path at the top and the side, and glued through a bottom package resistance to a heat sink. Figure 1 shows the FEM mesh. Table I lists the thickness and thermal properties of each layer. The silicon thermal conductivity has been considered constant, with its value fixed at the room temperature value. For the temperature excursions considered here the error introduced by using this approximation is small [8]. Fig. 1. 3D model of the stacked structure. TABLE I THICKNESS AND THERMAL PROPERTIES OF THE LAYERS COMPOSING THE STACK Layer thickness (μm) Thermal conductivity, k (W/mK) Die 1 100 150 Die 2 20 150 Die 3 20 150 BEOL 8 0.5 Polymer 1 0.3 III. RESULTS A. Hot spots thermal footprint and impact of parameters variation The study evaluates the steady state thermal performance ©EDA Publishing/THERMINIC 2009 56 ISBN: 978-2-35500-010-2
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