Online proceedings - EDA Publishing Association

spreading of the heat to the cavity walls, and the resulting
lower temperatures. Fig. 6 also indicates that the flow above
the top surface of the stack is primarily dominated by local
natural convection cells, with relatively little communication
with the bulk flow around the sides of the pyramid. The
resulting temperature distribution is shown in Fig. 7.
7-9 October 2009, Leuven, Belgium
used to spread heat more effectively and hence the proposed
idea is easily scalable.
TABLE II
SPREADER SIZE EFFECT ON MAXIMUM CHIP TEMPERATURE
Case
B C D J T max
(mm) (mm) (mm) (mm) (K)
I 60 73.5 85 90 332.7
II 47.5 52.5 57.5 60 340.4
III 45 47.5 50 52.5 343.1
IV 47.5 52.5 57.5 60 334.6
V 45 47.5 50 52.5 337.8
Tmax (K)
355
350
345
340
335
330
Fig. 7. Temperature distribution (in K) in the integrated heat sink
In this example, the maximum temperature within the chip
stack is 337.8 K, which is considerably lower than the
maximum allowable operating temperature of 350 K. At the
same time, the volume footprint of the entire assembly is
only 76.2 mm square by 43.2 mm height. In this
arrangement, the bottom surface of the heat spreader is
insulated and therefore the bottom tier is the warmest, but
this effect is minimized by the pyramid structure, which
helps in achieving more uniform temperatures in the stack.
Note that if the power dissipation of the stack tiers varies,
the heat spreaders can be designed or rearranged to achieve a
more uniform temperature distribution by exploiting local
convection currents within the dielectric fluid.
B. Impact of spreader size
Various platform dimensions of the copper spreaders were
explored with a goal of minimizing the lateral dimension of
the module for optimal heat transfer. The results are
summarized in Table II, where cases I to III are for an
arrangement as shown in Fig. 1 and cases IV and V are for
the setup shown in Fig. 5. It is interesting to note the
usefulness of solid copper filling the no/low-convection
zones between the lateral spreader extensions. T max is
reduced by filling the spaces with extra copper. It is also
noteworthy that the existence of no gaps between the stack
levels prevents the dielectric fluid from accumulating in
domains where the flow is restricted and thus avoids stagnant
localized air pockets that may form due to degassing, or
vapor pockets in two-phase flow.
Fig. 8 shows T max with increasing stack power (combined
power from all the four ICs in the stack). As expected, it
was found to increase nearly linearly with total chip power.
The assumed spreader size (case V) was found to be capable
of dissipating up to 50 W to the fluid, without exceeding the
allowable temperature limit. It can be concluded from Table
II and Fig. 8 that a design with large spreader sizes can be
325
25 30 35 40 45 50 55 60
Total Chip Power (W)
Fig. 8. Total stack power vs. maximum chip temperature (T max)
C. Impact of epoxy thermal conductivity
The foremost path of heat transfer in the proposed solution
is between the chip and the copper spreaders. A large
thermal resistance between these two entities is a bottleneck
for effective heat removal from the chip. Fig. 8 shows the
effect of thermal contact resistance, R c , between the spreader
and the chip on the maximum chip temperature. It can be
seen from the figure that thermal resistance at the contact
between the spreader and the clamp is significant only when
an air gap is present. If an interface material with a thermal
conductivity > 0.1 W/m.K is used to fill the gap (assumed as
125 micrometers), the resistance becomes negligible.
Fig. 8. Effect of contact resistance (R c) between the spreader and the chip on
chip maximum temperature (T max)
The insignificant effect of R c on T max is because of its
small value, compared to the thermal resistance to heat
©EDA Publishing/THERMINIC 2009 189
ISBN: 978-2-35500-010-2